gwj / at91sam9263 · Commits

Commit 88920f344d5352dc0bb57539c4639344e9e0e0fe

Authored by bellard
1 parent f7cce898

ARM shift fix (Paul Brook) 


git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@1167 c046a42c-6fe2-441c-8c8c-71466251a162
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Showing 2 changed files with 18 additions and 0 deletions
target-arm/op.c
  View file @88920f3
... ... @@ -485,6 +485,11 @@ void OPPROTO op_rorl_T1_im(void)
485 485 T1 = ((uint32_t)T1 >> shift) | (T1 << (32 - shift));
486 486 }
487 487  
  488 +void OPPROTO op_rrxl_T1(void)
  489 +{
  490 + T1 = ((uint32_t)T1 >> 1) | ((uint32_t)env->CF << 31);
  491 +}
  492 +
488 493 /* T1 based, set C flag */
489 494 void OPPROTO op_shll_T1_im_cc(void)
490 495 {
... ... @@ -512,6 +517,14 @@ void OPPROTO op_rorl_T1_im_cc(void)
512 517 T1 = ((uint32_t)T1 >> shift) | (T1 << (32 - shift));
513 518 }
514 519  
  520 +void OPPROTO op_rrxl_T1_cc(void)
  521 +{
  522 + uint32_t c;
  523 + c = T1 & 1;
  524 + T1 = ((uint32_t)T1 >> 1) | ((uint32_t)env->CF << 31);
  525 + env->CF = c;
  526 +}
  527 +
515 528 /* T2 based */
516 529 void OPPROTO op_shll_T2_im(void)
517 530 {
... ...
target-arm/translate.c
  View file @88920f3
... ... @@ -365,6 +365,11 @@ static void disas_arm_insn(DisasContext *s)
365 365 } else {
366 366 gen_shift_T1_im[shiftop](shift);
367 367 }
  368 + } else if (shiftop == 3) {
  369 + if (logic_cc)
  370 + gen_op_rrxl_T1_cc();
  371 + else
  372 + gen_op_rrxl_T1();
368 373 }
369 374 } else {
370 375 rs = (insn >> 8) & 0xf;
... ...