Commit 86dbdd4012427fe6b39664d5153abab05579a2f2

Authored by aurel32
1 parent 5d40cd63

tcg/x86_64: add bswap16_i{32,64} and bswap32_i64 ops

Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6838 c046a42c-6fe2-441c-8c8c-71466251a162
tcg/x86_64/tcg-target.c
... ... @@ -1094,7 +1094,14 @@ static inline void tcg_out_op(TCGContext *s, int opc, const TCGArg *args,
1094 1094 args[3], P_REXW);
1095 1095 break;
1096 1096  
  1097 + case INDEX_op_bswap16_i32:
  1098 + case INDEX_op_bswap16_i64:
  1099 + tcg_out8(s, 0x66);
  1100 + tcg_out_modrm(s, 0xc1, SHIFT_ROL, args[0]);
  1101 + tcg_out8(s, 8);
  1102 + break;
1097 1103 case INDEX_op_bswap32_i32:
  1104 + case INDEX_op_bswap32_i64:
1098 1105 tcg_out_opc(s, (0xc8 + (args[0] & 7)) | P_EXT, 0, args[0], 0);
1099 1106 break;
1100 1107 case INDEX_op_bswap64_i64:
... ... @@ -1287,7 +1294,10 @@ static const TCGTargetOpDef x86_64_op_defs[] = {
1287 1294  
1288 1295 { INDEX_op_brcond_i64, { "r", "re" } },
1289 1296  
  1297 + { INDEX_op_bswap16_i32, { "r", "0" } },
  1298 + { INDEX_op_bswap16_i64, { "r", "0" } },
1290 1299 { INDEX_op_bswap32_i32, { "r", "0" } },
  1300 + { INDEX_op_bswap32_i64, { "r", "0" } },
1291 1301 { INDEX_op_bswap64_i64, { "r", "0" } },
1292 1302  
1293 1303 { INDEX_op_neg_i32, { "r", "0" } },
... ...
tcg/x86_64/tcg-target.h
... ... @@ -56,7 +56,10 @@ enum {
56 56 #define TCG_TARGET_CALL_STACK_OFFSET 0
57 57  
58 58 /* optional instructions */
  59 +#define TCG_TARGET_HAS_bswap16_i32
  60 +#define TCG_TARGET_HAS_bswap16_i64
59 61 #define TCG_TARGET_HAS_bswap32_i32
  62 +#define TCG_TARGET_HAS_bswap32_i64
60 63 #define TCG_TARGET_HAS_bswap64_i64
61 64 #define TCG_TARGET_HAS_neg_i32
62 65 #define TCG_TARGET_HAS_neg_i64
... ...