gwj / at91sam9263 · Commits

Commit 85c4adf65f20437c428a1ebf2d3293dd56a53596

Authored by bellard
1 parent b69fedff

PowerPC merge 


git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@860 c046a42c-6fe2-441c-8c8c-71466251a162
Inline Side-by-side
Showing 1 changed file with 50 additions and 3 deletions
target-ppc/cpu.h
  View file @85c4adf
... ... @@ -74,6 +74,10 @@ enum {
74 74  
75 75 #define PPC_COMMON (PPC_INTEGER | PPC_FLOAT | PPC_FLOW | PPC_MEM | \
76 76 PPC_RES | PPC_CACHE | PPC_MISC | PPC_SEGMENT)
  77 +/* PPC 604 */
  78 +#define PPC_604 (PPC_INTEGER | PPC_FLOAT | PPC_FLOW | PPC_MEM | \
  79 + PPC_RES | PPC_CACHE | PPC_MISC | PPC_EXTERN | PPC_SEGMENT \
  80 + PPC_MEM_OPT)
77 81 /* PPC 740/745/750/755 (aka G3) has external access instructions */
78 82 #define PPC_750 (PPC_INTEGER | PPC_FLOAT | PPC_FLOW | PPC_MEM | \
79 83 PPC_RES | PPC_CACHE | PPC_MISC | PPC_EXTERN | PPC_SEGMENT)
... ... @@ -202,6 +206,8 @@ void _store_xer (CPUPPCState *env, uint32_t value);
202 206 uint32_t _load_msr (CPUPPCState *env);
203 207 void _store_msr (CPUPPCState *env, uint32_t value);
204 208  
  209 +int cpu_ppc_register (CPUPPCState *env, uint32_t pvr);
  210 +
205 211 /* Time-base and decrementer management */
206 212 #ifndef NO_CPU_IO_DEFS
207 213 uint32_t cpu_ppc_load_tbl (CPUPPCState *env);
... ... @@ -235,7 +241,10 @@ void cpu_ppc_store_decr (CPUPPCState *env, uint32_t value);
235 241 #define xer_ca env->xer[1]
236 242 #define xer_bc env->xer[0]
237 243  
  244 +#define MQ SPR_ENCODE(0)
238 245 #define XER SPR_ENCODE(1)
  246 +#define RTCUR SPR_ENCODE(4)
  247 +#define RTCLR SPR_ENCODE(5)
239 248 #define LR SPR_ENCODE(8)
240 249 #define CTR SPR_ENCODE(9)
241 250 /* VEA mode SPR */
... ... @@ -244,6 +253,8 @@ void cpu_ppc_store_decr (CPUPPCState *env, uint32_t value);
244 253 /* supervisor mode SPR */
245 254 #define DSISR SPR_ENCODE(18)
246 255 #define DAR SPR_ENCODE(19)
  256 +#define RTCUW SPR_ENCODE(20)
  257 +#define RTCLW SPR_ENCODE(21)
247 258 #define DECR SPR_ENCODE(22)
248 259 #define SDR1 SPR_ENCODE(25)
249 260 #define SRR0 SPR_ENCODE(26)
... ... @@ -293,14 +304,50 @@ void cpu_ppc_store_decr (CPUPPCState *env, uint32_t value);
293 304 #define DBAT6L SPR_ENCODE(573)
294 305 #define DBAT7U SPR_ENCODE(574)
295 306 #define DBAT7L SPR_ENCODE(575)
  307 +#define UMMCR0 SPR_ENCODE(936)
  308 +#define UPMC1 SPR_ENCODE(937)
  309 +#define UPMC2 SPR_ENCODE(938)
  310 +#define USIA SPR_ENCODE(939)
  311 +#define UMMCR1 SPR_ENCODE(940)
  312 +#define UPMC3 SPR_ENCODE(941)
  313 +#define UPMC4 SPR_ENCODE(942)
  314 +#define MMCR0 SPR_ENCODE(952)
  315 +#define PMC1 SPR_ENCODE(953)
  316 +#define PMC2 SPR_ENCODE(954)
  317 +#define SIA SPR_ENCODE(955)
  318 +#define MMCR1 SPR_ENCODE(956)
  319 +#define PMC3 SPR_ENCODE(957)
  320 +#define PMC4 SPR_ENCODE(958)
  321 +#define SDA SPR_ENCODE(959)
  322 +#define DMISS SPR_ENCODE(976)
  323 +#define DCMP SPR_ENCODE(977)
  324 +#define DHASH1 SPR_ENCODE(978)
  325 +#define DHASH2 SPR_ENCODE(979)
  326 +#define IMISS SPR_ENCODE(980)
  327 +#define ICMP SPR_ENCODE(981)
  328 +#define RPA SPR_ENCODE(982)
  329 +#define TCR SPR_ENCODE(984)
  330 +#define IBR SPR_ENCODE(986)
  331 +#define ESASRR SPR_ENCODE(987)
  332 +#define SEBR SPR_ENCODE(990)
  333 +#define SER SPR_ENCODE(991)
  334 +#define HID0 SPR_ENCODE(1008)
  335 +#define HID1 SPR_ENCODE(1009)
  336 +#define IABR SPR_ENCODE(1010)
  337 +#define HID2 SPR_ENCODE(1011)
296 338 #define DABR SPR_ENCODE(1013)
  339 +#define L2PM SPR_ENCODE(1016)
  340 +#define L2CR SPR_ENCODE(1017)
  341 +#define ICTC SPR_ENCODE(1019)
  342 +#define THRM1 SPR_ENCODE(1020)
  343 +#define THRM2 SPR_ENCODE(1021)
  344 +#define THRM3 SPR_ENCODE(1022)
  345 +#define SP SPR_ENCODE(1021)
  346 +#define LP SPR_ENCODE(1022)
297 347 #define DABR_MASK 0xFFFFFFF8
298 348 #define FPECR SPR_ENCODE(1022)
299 349 #define PIR SPR_ENCODE(1023)
300 350  
301   -#define TARGET_PAGE_BITS 12
302   -#include "cpu-all.h"
303   -
304 351 /* Memory access type :
305 352 * may be needed for precise access rights control and precise exceptions.
306 353 */
... ...