gwj / at91sam9263 · Commits

Commit 8508b89e366906ec4f1b15fdd2e9ce5fab2b1bd6

Authored by blueswir1
1 parent 384ccb5d

Add dummy THC and TEC registers to TCX 


git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@2775 c046a42c-6fe2-441c-8c8c-71466251a162
Inline Side-by-side
Showing 1 changed file with 36 additions and 3 deletions
hw/tcx.c
  View file @8508b89
@@ -26,6 +26,9 @@ @@ -26,6 +26,9 @@
26 #define MAXX 1024 26 #define MAXX 1024
27 #define MAXY 768 27 #define MAXY 768
28 #define TCX_DAC_NREGS 16 28 #define TCX_DAC_NREGS 16
  29 +#define TCX_THC_NREGS_8 0x081c
  30 +#define TCX_THC_NREGS_24 0x1000
  31 +#define TCX_TEC_NREGS 0x1000
29 32
30 typedef struct TCXState { 33 typedef struct TCXState {
31 uint32_t addr; 34 uint32_t addr;
@@ -467,12 +470,34 @@ static CPUWriteMemoryFunc *tcx_dac_write[3] = { @@ -467,12 +470,34 @@ static CPUWriteMemoryFunc *tcx_dac_write[3] = {
467 tcx_dac_writel, 470 tcx_dac_writel,
468 }; 471 };
469 472
  473 +static uint32_t tcx_dummy_readl(void *opaque, target_phys_addr_t addr)
  474 +{
  475 + return 0;
  476 +}
  477 +
  478 +static void tcx_dummy_writel(void *opaque, target_phys_addr_t addr,
  479 + uint32_t val)
  480 +{
  481 +}
  482 +
  483 +static CPUReadMemoryFunc *tcx_dummy_read[3] = {
  484 + tcx_dummy_readl,
  485 + tcx_dummy_readl,
  486 + tcx_dummy_readl,
  487 +};
  488 +
  489 +static CPUWriteMemoryFunc *tcx_dummy_write[3] = {
  490 + tcx_dummy_writel,
  491 + tcx_dummy_writel,
  492 + tcx_dummy_writel,
  493 +};
  494 +
470 void tcx_init(DisplayState *ds, uint32_t addr, uint8_t *vram_base, 495 void tcx_init(DisplayState *ds, uint32_t addr, uint8_t *vram_base,
471 unsigned long vram_offset, int vram_size, int width, int height, 496 unsigned long vram_offset, int vram_size, int width, int height,
472 int depth) 497 int depth)
473 { 498 {
474 TCXState *s; 499 TCXState *s;
475 - int io_memory; 500 + int io_memory, dummy_memory;
476 int size; 501 int size;
477 502
478 s = qemu_mallocz(sizeof(TCXState)); 503 s = qemu_mallocz(sizeof(TCXState));
@@ -495,6 +520,10 @@ void tcx_init(DisplayState *ds, uint32_t addr, uint8_t *vram_base, @@ -495,6 +520,10 @@ void tcx_init(DisplayState *ds, uint32_t addr, uint8_t *vram_base,
495 io_memory = cpu_register_io_memory(0, tcx_dac_read, tcx_dac_write, s); 520 io_memory = cpu_register_io_memory(0, tcx_dac_read, tcx_dac_write, s);
496 cpu_register_physical_memory(addr + 0x00200000, TCX_DAC_NREGS, io_memory); 521 cpu_register_physical_memory(addr + 0x00200000, TCX_DAC_NREGS, io_memory);
497 522
  523 + dummy_memory = cpu_register_io_memory(0, tcx_dummy_read, tcx_dummy_write,
  524 + s);
  525 + cpu_register_physical_memory(addr + 0x00700000, TCX_TEC_NREGS,
  526 + dummy_memory);
498 if (depth == 24) { 527 if (depth == 24) {
499 // 24-bit plane 528 // 24-bit plane
500 size = vram_size * 4; 529 size = vram_size * 4;
@@ -509,9 +538,13 @@ void tcx_init(DisplayState *ds, uint32_t addr, uint8_t *vram_base, @@ -509,9 +538,13 @@ void tcx_init(DisplayState *ds, uint32_t addr, uint8_t *vram_base,
509 s->cplane = (uint32_t *)vram_base; 538 s->cplane = (uint32_t *)vram_base;
510 s->cplane_offset = vram_offset; 539 s->cplane_offset = vram_offset;
511 cpu_register_physical_memory(addr + 0x0a000000, size, vram_offset); 540 cpu_register_physical_memory(addr + 0x0a000000, size, vram_offset);
512 - graphic_console_init(s->ds, tcx24_update_display, tcx24_invalidate_display,  
513 - tcx24_screen_dump, s); 541 + cpu_register_physical_memory(addr + 0x00301000, TCX_THC_NREGS_24,
  542 + dummy_memory);
  543 + graphic_console_init(s->ds, tcx24_update_display,
  544 + tcx24_invalidate_display, tcx24_screen_dump, s);
514 } else { 545 } else {
  546 + cpu_register_physical_memory(addr + 0x00300000, TCX_THC_NREGS_8,
  547 + dummy_memory);
515 graphic_console_init(s->ds, tcx_update_display, tcx_invalidate_display, 548 graphic_console_init(s->ds, tcx_update_display, tcx_invalidate_display,
516 tcx_screen_dump, s); 549 tcx_screen_dump, s);
517 } 550 }