gwj / at91sam9263 · Commits

Commit 81b5b816e23450c4659411f77d9c7b54681e07dc

Authored by blueswir1
1 parent 741a7444

Use andc, orc, nor and nand 

Also fix which argument gets negated in fandnot[12] and fornot[12]


git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5662 c046a42c-6fe2-441c-8c8c-71466251a162
Inline Side-by-side
Showing 1 changed file with 36 additions and 52 deletions
target-sparc/translate.c
  View file @81b5b81
@@ -3079,14 +3079,12 @@ static void disas_sparc_insn(DisasContext * dc) @@ -3079,14 +3079,12 @@ static void disas_sparc_insn(DisasContext * dc)
3079 tcg_gen_sub_tl(cpu_dst, cpu_src1, cpu_src2); 3079 tcg_gen_sub_tl(cpu_dst, cpu_src1, cpu_src2);
3080 break; 3080 break;
3081 case 0x5: 3081 case 0x5:
3082 - tcg_gen_xori_tl(cpu_tmp0, cpu_src2, -1);  
3083 - tcg_gen_and_tl(cpu_dst, cpu_src1, cpu_tmp0); 3082 + tcg_gen_andc_tl(cpu_dst, cpu_src1, cpu_src2);
3084 if (xop & 0x10) 3083 if (xop & 0x10)
3085 gen_op_logic_cc(cpu_dst); 3084 gen_op_logic_cc(cpu_dst);
3086 break; 3085 break;
3087 case 0x6: 3086 case 0x6:
3088 - tcg_gen_xori_tl(cpu_tmp0, cpu_src2, -1);  
3089 - tcg_gen_or_tl(cpu_dst, cpu_src1, cpu_tmp0); 3087 + tcg_gen_orc_tl(cpu_dst, cpu_src1, cpu_src2);
3090 if (xop & 0x10) 3088 if (xop & 0x10)
3091 gen_op_logic_cc(cpu_dst); 3089 gen_op_logic_cc(cpu_dst);
3092 break; 3090 break;
@@ -3907,31 +3905,26 @@ static void disas_sparc_insn(DisasContext * dc) @@ -3907,31 +3905,26 @@ static void disas_sparc_insn(DisasContext * dc)
3907 break; 3905 break;
3908 case 0x062: /* VIS I fnor */ 3906 case 0x062: /* VIS I fnor */
3909 CHECK_FPU_FEATURE(dc, VIS1); 3907 CHECK_FPU_FEATURE(dc, VIS1);
3910 - tcg_gen_or_i32(cpu_tmp32, cpu_fpr[DFPREG(rs1)],  
3911 - cpu_fpr[DFPREG(rs2)]);  
3912 - tcg_gen_xori_i32(cpu_fpr[DFPREG(rd)], cpu_tmp32, -1);  
3913 - tcg_gen_or_i32(cpu_tmp32, cpu_fpr[DFPREG(rs1) + 1],  
3914 - cpu_fpr[DFPREG(rs2) + 1]);  
3915 - tcg_gen_xori_i32(cpu_fpr[DFPREG(rd) + 1], cpu_tmp32, -1); 3908 + tcg_gen_nor_i32(cpu_tmp32, cpu_fpr[DFPREG(rs1)],
  3909 + cpu_fpr[DFPREG(rs2)]);
  3910 + tcg_gen_nor_i32(cpu_tmp32, cpu_fpr[DFPREG(rs1) + 1],
  3911 + cpu_fpr[DFPREG(rs2) + 1]);
3916 break; 3912 break;
3917 case 0x063: /* VIS I fnors */ 3913 case 0x063: /* VIS I fnors */
3918 CHECK_FPU_FEATURE(dc, VIS1); 3914 CHECK_FPU_FEATURE(dc, VIS1);
3919 - tcg_gen_or_i32(cpu_tmp32, cpu_fpr[rs1], cpu_fpr[rs2]);  
3920 - tcg_gen_xori_i32(cpu_fpr[rd], cpu_tmp32, -1); 3915 + tcg_gen_nor_i32(cpu_tmp32, cpu_fpr[rs1], cpu_fpr[rs2]);
3921 break; 3916 break;
3922 case 0x064: /* VIS I fandnot2 */ 3917 case 0x064: /* VIS I fandnot2 */
3923 CHECK_FPU_FEATURE(dc, VIS1); 3918 CHECK_FPU_FEATURE(dc, VIS1);
3924 - tcg_gen_xori_i32(cpu_tmp32, cpu_fpr[DFPREG(rs1)], -1);  
3925 - tcg_gen_and_i32(cpu_fpr[DFPREG(rd)], cpu_tmp32,  
3926 - cpu_fpr[DFPREG(rs2)]);  
3927 - tcg_gen_xori_i32(cpu_tmp32, cpu_fpr[DFPREG(rs1) + 1], -1);  
3928 - tcg_gen_and_i32(cpu_fpr[DFPREG(rd) + 1], cpu_tmp32,  
3929 - cpu_fpr[DFPREG(rs2) + 1]); 3919 + tcg_gen_andc_i32(cpu_fpr[DFPREG(rd)], cpu_fpr[DFPREG(rs1)],
  3920 + cpu_fpr[DFPREG(rs2)]);
  3921 + tcg_gen_andc_i32(cpu_fpr[DFPREG(rd) + 1],
  3922 + cpu_fpr[DFPREG(rs1) + 1],
  3923 + cpu_fpr[DFPREG(rs2) + 1]);
3930 break; 3924 break;
3931 case 0x065: /* VIS I fandnot2s */ 3925 case 0x065: /* VIS I fandnot2s */
3932 CHECK_FPU_FEATURE(dc, VIS1); 3926 CHECK_FPU_FEATURE(dc, VIS1);
3933 - tcg_gen_xori_i32(cpu_tmp32, cpu_fpr[rs1], -1);  
3934 - tcg_gen_and_i32(cpu_fpr[rd], cpu_tmp32, cpu_fpr[rs2]); 3927 + tcg_gen_andc_i32(cpu_fpr[rd], cpu_fpr[rs1], cpu_fpr[rs2]);
3935 break; 3928 break;
3936 case 0x066: /* VIS I fnot2 */ 3929 case 0x066: /* VIS I fnot2 */
3937 CHECK_FPU_FEATURE(dc, VIS1); 3930 CHECK_FPU_FEATURE(dc, VIS1);
@@ -3946,17 +3939,15 @@ static void disas_sparc_insn(DisasContext * dc) @@ -3946,17 +3939,15 @@ static void disas_sparc_insn(DisasContext * dc)
3946 break; 3939 break;
3947 case 0x068: /* VIS I fandnot1 */ 3940 case 0x068: /* VIS I fandnot1 */
3948 CHECK_FPU_FEATURE(dc, VIS1); 3941 CHECK_FPU_FEATURE(dc, VIS1);
3949 - tcg_gen_xori_i32(cpu_tmp32, cpu_fpr[DFPREG(rs2)], -1);  
3950 - tcg_gen_and_i32(cpu_fpr[DFPREG(rd)], cpu_tmp32,  
3951 - cpu_fpr[DFPREG(rs1)]);  
3952 - tcg_gen_xori_i32(cpu_tmp32, cpu_fpr[DFPREG(rs2)], -1);  
3953 - tcg_gen_and_i32(cpu_fpr[DFPREG(rd) + 1], cpu_tmp32,  
3954 - cpu_fpr[DFPREG(rs1) + 1]); 3942 + tcg_gen_andc_i32(cpu_fpr[DFPREG(rd)], cpu_fpr[DFPREG(rs2)],
  3943 + cpu_fpr[DFPREG(rs1)]);
  3944 + tcg_gen_andc_i32(cpu_fpr[DFPREG(rd) + 1],
  3945 + cpu_fpr[DFPREG(rs2) + 1],
  3946 + cpu_fpr[DFPREG(rs1) + 1]);
3955 break; 3947 break;
3956 case 0x069: /* VIS I fandnot1s */ 3948 case 0x069: /* VIS I fandnot1s */
3957 CHECK_FPU_FEATURE(dc, VIS1); 3949 CHECK_FPU_FEATURE(dc, VIS1);
3958 - tcg_gen_xori_i32(cpu_tmp32, cpu_fpr[rs2], -1);  
3959 - tcg_gen_and_i32(cpu_fpr[rd], cpu_tmp32, cpu_fpr[rs1]); 3950 + tcg_gen_andc_i32(cpu_fpr[rd], cpu_fpr[rs2], cpu_fpr[rs1]);
3960 break; 3951 break;
3961 case 0x06a: /* VIS I fnot1 */ 3952 case 0x06a: /* VIS I fnot1 */
3962 CHECK_FPU_FEATURE(dc, VIS1); 3953 CHECK_FPU_FEATURE(dc, VIS1);
@@ -3983,17 +3974,14 @@ static void disas_sparc_insn(DisasContext * dc) @@ -3983,17 +3974,14 @@ static void disas_sparc_insn(DisasContext * dc)
3983 break; 3974 break;
3984 case 0x06e: /* VIS I fnand */ 3975 case 0x06e: /* VIS I fnand */
3985 CHECK_FPU_FEATURE(dc, VIS1); 3976 CHECK_FPU_FEATURE(dc, VIS1);
3986 - tcg_gen_and_i32(cpu_tmp32, cpu_fpr[DFPREG(rs1)],  
3987 - cpu_fpr[DFPREG(rs2)]);  
3988 - tcg_gen_xori_i32(cpu_fpr[DFPREG(rd)], cpu_tmp32, -1);  
3989 - tcg_gen_and_i32(cpu_tmp32, cpu_fpr[DFPREG(rs1) + 1],  
3990 - cpu_fpr[DFPREG(rs2) + 1]);  
3991 - tcg_gen_xori_i32(cpu_fpr[DFPREG(rd) + 1], cpu_tmp32, -1); 3977 + tcg_gen_nand_i32(cpu_tmp32, cpu_fpr[DFPREG(rs1)],
  3978 + cpu_fpr[DFPREG(rs2)]);
  3979 + tcg_gen_nand_i32(cpu_tmp32, cpu_fpr[DFPREG(rs1) + 1],
  3980 + cpu_fpr[DFPREG(rs2) + 1]);
3992 break; 3981 break;
3993 case 0x06f: /* VIS I fnands */ 3982 case 0x06f: /* VIS I fnands */
3994 CHECK_FPU_FEATURE(dc, VIS1); 3983 CHECK_FPU_FEATURE(dc, VIS1);
3995 - tcg_gen_and_i32(cpu_tmp32, cpu_fpr[rs1], cpu_fpr[rs2]);  
3996 - tcg_gen_xori_i32(cpu_fpr[rd], cpu_tmp32, -1); 3984 + tcg_gen_nand_i32(cpu_tmp32, cpu_fpr[rs1], cpu_fpr[rs2]);
3997 break; 3985 break;
3998 case 0x070: /* VIS I fand */ 3986 case 0x070: /* VIS I fand */
3999 CHECK_FPU_FEATURE(dc, VIS1); 3987 CHECK_FPU_FEATURE(dc, VIS1);
@@ -4033,17 +4021,15 @@ static void disas_sparc_insn(DisasContext * dc) @@ -4033,17 +4021,15 @@ static void disas_sparc_insn(DisasContext * dc)
4033 break; 4021 break;
4034 case 0x076: /* VIS I fornot2 */ 4022 case 0x076: /* VIS I fornot2 */
4035 CHECK_FPU_FEATURE(dc, VIS1); 4023 CHECK_FPU_FEATURE(dc, VIS1);
4036 - tcg_gen_xori_i32(cpu_tmp32, cpu_fpr[DFPREG(rs1)], -1);  
4037 - tcg_gen_or_i32(cpu_fpr[DFPREG(rd)], cpu_tmp32,  
4038 - cpu_fpr[DFPREG(rs2)]);  
4039 - tcg_gen_xori_i32(cpu_tmp32, cpu_fpr[DFPREG(rs1) + 1], -1);  
4040 - tcg_gen_or_i32(cpu_fpr[DFPREG(rd) + 1], cpu_tmp32,  
4041 - cpu_fpr[DFPREG(rs2) + 1]); 4024 + tcg_gen_orc_i32(cpu_fpr[DFPREG(rd)], cpu_fpr[DFPREG(rs1)],
  4025 + cpu_fpr[DFPREG(rs2)]);
  4026 + tcg_gen_orc_i32(cpu_fpr[DFPREG(rd) + 1],
  4027 + cpu_fpr[DFPREG(rs1) + 1],
  4028 + cpu_fpr[DFPREG(rs2) + 1]);
4042 break; 4029 break;
4043 case 0x077: /* VIS I fornot2s */ 4030 case 0x077: /* VIS I fornot2s */
4044 CHECK_FPU_FEATURE(dc, VIS1); 4031 CHECK_FPU_FEATURE(dc, VIS1);
4045 - tcg_gen_xori_i32(cpu_tmp32, cpu_fpr[rs1], -1);  
4046 - tcg_gen_or_i32(cpu_fpr[rd], cpu_tmp32, cpu_fpr[rs2]); 4032 + tcg_gen_orc_i32(cpu_fpr[rd], cpu_fpr[rs1], cpu_fpr[rs2]);
4047 break; 4033 break;
4048 case 0x078: /* VIS I fsrc2 */ 4034 case 0x078: /* VIS I fsrc2 */
4049 CHECK_FPU_FEATURE(dc, VIS1); 4035 CHECK_FPU_FEATURE(dc, VIS1);
@@ -4056,17 +4042,15 @@ static void disas_sparc_insn(DisasContext * dc) @@ -4056,17 +4042,15 @@ static void disas_sparc_insn(DisasContext * dc)
4056 break; 4042 break;
4057 case 0x07a: /* VIS I fornot1 */ 4043 case 0x07a: /* VIS I fornot1 */
4058 CHECK_FPU_FEATURE(dc, VIS1); 4044 CHECK_FPU_FEATURE(dc, VIS1);
4059 - tcg_gen_xori_i32(cpu_tmp32, cpu_fpr[DFPREG(rs2)], -1);  
4060 - tcg_gen_or_i32(cpu_fpr[DFPREG(rd)], cpu_tmp32,  
4061 - cpu_fpr[DFPREG(rs1)]);  
4062 - tcg_gen_xori_i32(cpu_tmp32, cpu_fpr[DFPREG(rs2) + 1], -1);  
4063 - tcg_gen_or_i32(cpu_fpr[DFPREG(rd) + 1], cpu_tmp32,  
4064 - cpu_fpr[DFPREG(rs1) + 1]); 4045 + tcg_gen_orc_i32(cpu_fpr[DFPREG(rd)], cpu_fpr[DFPREG(rs2)],
  4046 + cpu_fpr[DFPREG(rs1)]);
  4047 + tcg_gen_orc_i32(cpu_fpr[DFPREG(rd) + 1],
  4048 + cpu_fpr[DFPREG(rs2) + 1],
  4049 + cpu_fpr[DFPREG(rs1) + 1]);
4065 break; 4050 break;
4066 case 0x07b: /* VIS I fornot1s */ 4051 case 0x07b: /* VIS I fornot1s */
4067 CHECK_FPU_FEATURE(dc, VIS1); 4052 CHECK_FPU_FEATURE(dc, VIS1);
4068 - tcg_gen_xori_i32(cpu_tmp32, cpu_fpr[rs2], -1);  
4069 - tcg_gen_or_i32(cpu_fpr[rd], cpu_tmp32, cpu_fpr[rs1]); 4053 + tcg_gen_orc_i32(cpu_fpr[rd], cpu_fpr[rs2], cpu_fpr[rs1]);
4070 break; 4054 break;
4071 case 0x07c: /* VIS I for */ 4055 case 0x07c: /* VIS I for */
4072 CHECK_FPU_FEATURE(dc, VIS1); 4056 CHECK_FPU_FEATURE(dc, VIS1);