Commit 7ff4d2180b27b3356379ca66738da10ad8b2f73a
1 parent
e88de099
CF generator for constant operands
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@1267 c046a42c-6fe2-441c-8c8c-71466251a162
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2 changed files
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7 additions
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1 deletions
target-arm/op.c
| @@ -105,6 +105,11 @@ void OPPROTO op_movl_T1_im(void) | @@ -105,6 +105,11 @@ void OPPROTO op_movl_T1_im(void) | ||
| 105 | T1 = PARAM1; | 105 | T1 = PARAM1; |
| 106 | } | 106 | } |
| 107 | 107 | ||
| 108 | +void OPPROTO op_mov_CF_T1(void) | ||
| 109 | +{ | ||
| 110 | + env->CF = ((uint32_t)T1) >> 31; | ||
| 111 | +} | ||
| 112 | + | ||
| 108 | void OPPROTO op_movl_T2_im(void) | 113 | void OPPROTO op_movl_T2_im(void) |
| 109 | { | 114 | { |
| 110 | T2 = PARAM1; | 115 | T2 = PARAM1; |
target-arm/translate.c
| @@ -536,7 +536,8 @@ static void disas_arm_insn(DisasContext *s) | @@ -536,7 +536,8 @@ static void disas_arm_insn(DisasContext *s) | ||
| 536 | if (shift) | 536 | if (shift) |
| 537 | val = (val >> shift) | (val << (32 - shift)); | 537 | val = (val >> shift) | (val << (32 - shift)); |
| 538 | gen_op_movl_T1_im(val); | 538 | gen_op_movl_T1_im(val); |
| 539 | - /* XXX: is CF modified ? */ | 539 | + if (logic_cc && shift) |
| 540 | + gen_op_mov_CF_T1(); | ||
| 540 | } else { | 541 | } else { |
| 541 | /* register */ | 542 | /* register */ |
| 542 | rm = (insn) & 0xf; | 543 | rm = (insn) & 0xf; |