Commit 7fc067350cb5a9218c607fce0a29af612ba48324
1 parent
871e6c35
Sparc32: convert SBI to qdev
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
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3 changed files
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54 additions
and
21 deletions
hw/sbi.c
| @@ -21,9 +21,11 @@ | @@ -21,9 +21,11 @@ | ||
| 21 | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN | 21 | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN |
| 22 | * THE SOFTWARE. | 22 | * THE SOFTWARE. |
| 23 | */ | 23 | */ |
| 24 | + | ||
| 24 | #include "hw.h" | 25 | #include "hw.h" |
| 25 | #include "sun4m.h" | 26 | #include "sun4m.h" |
| 26 | #include "console.h" | 27 | #include "console.h" |
| 28 | +#include "sysbus.h" | ||
| 27 | 29 | ||
| 28 | //#define DEBUG_IRQ | 30 | //#define DEBUG_IRQ |
| 29 | 31 | ||
| @@ -39,9 +41,10 @@ | @@ -39,9 +41,10 @@ | ||
| 39 | #define SBI_NREGS 16 | 41 | #define SBI_NREGS 16 |
| 40 | 42 | ||
| 41 | typedef struct SBIState { | 43 | typedef struct SBIState { |
| 44 | + SysBusDevice busdev; | ||
| 42 | uint32_t regs[SBI_NREGS]; | 45 | uint32_t regs[SBI_NREGS]; |
| 43 | uint32_t intreg_pending[MAX_CPUS]; | 46 | uint32_t intreg_pending[MAX_CPUS]; |
| 44 | - qemu_irq *cpu_irqs[MAX_CPUS]; | 47 | + qemu_irq cpu_irqs[MAX_CPUS]; |
| 45 | uint32_t pil_out[MAX_CPUS]; | 48 | uint32_t pil_out[MAX_CPUS]; |
| 46 | } SBIState; | 49 | } SBIState; |
| 47 | 50 | ||
| @@ -51,10 +54,6 @@ static void sbi_set_irq(void *opaque, int irq, int level) | @@ -51,10 +54,6 @@ static void sbi_set_irq(void *opaque, int irq, int level) | ||
| 51 | { | 54 | { |
| 52 | } | 55 | } |
| 53 | 56 | ||
| 54 | -static void sbi_set_timer_irq_cpu(void *opaque, int cpu, int level) | ||
| 55 | -{ | ||
| 56 | -} | ||
| 57 | - | ||
| 58 | static uint32_t sbi_mem_readl(void *opaque, target_phys_addr_t addr) | 57 | static uint32_t sbi_mem_readl(void *opaque, target_phys_addr_t addr) |
| 59 | { | 58 | { |
| 60 | SBIState *s = opaque; | 59 | SBIState *s = opaque; |
| @@ -132,27 +131,54 @@ static void sbi_reset(void *opaque) | @@ -132,27 +131,54 @@ static void sbi_reset(void *opaque) | ||
| 132 | } | 131 | } |
| 133 | } | 132 | } |
| 134 | 133 | ||
| 135 | -void *sbi_init(target_phys_addr_t addr, qemu_irq **irq, qemu_irq **cpu_irq, | ||
| 136 | - qemu_irq **parent_irq) | 134 | +DeviceState *sbi_init(target_phys_addr_t addr, qemu_irq **parent_irq) |
| 137 | { | 135 | { |
| 136 | + DeviceState *dev; | ||
| 137 | + SysBusDevice *s; | ||
| 138 | unsigned int i; | 138 | unsigned int i; |
| 139 | - int sbi_io_memory; | ||
| 140 | - SBIState *s; | ||
| 141 | 139 | ||
| 142 | - s = qemu_mallocz(sizeof(SBIState)); | 140 | + dev = qdev_create(NULL, "sbi"); |
| 141 | + qdev_init(dev); | ||
| 142 | + | ||
| 143 | + s = sysbus_from_qdev(dev); | ||
| 143 | 144 | ||
| 144 | for (i = 0; i < MAX_CPUS; i++) { | 145 | for (i = 0; i < MAX_CPUS; i++) { |
| 145 | - s->cpu_irqs[i] = parent_irq[i]; | 146 | + sysbus_connect_irq(s, i, *parent_irq[i]); |
| 147 | + } | ||
| 148 | + | ||
| 149 | + sysbus_mmio_map(s, 0, addr); | ||
| 150 | + | ||
| 151 | + return dev; | ||
| 152 | +} | ||
| 153 | + | ||
| 154 | +static void sbi_init1(SysBusDevice *dev) | ||
| 155 | +{ | ||
| 156 | + SBIState *s = FROM_SYSBUS(SBIState, dev); | ||
| 157 | + int sbi_io_memory; | ||
| 158 | + unsigned int i; | ||
| 159 | + | ||
| 160 | + qdev_init_gpio_in(&dev->qdev, sbi_set_irq, 32 + MAX_CPUS); | ||
| 161 | + for (i = 0; i < MAX_CPUS; i++) { | ||
| 162 | + sysbus_init_irq(dev, &s->cpu_irqs[i]); | ||
| 146 | } | 163 | } |
| 147 | 164 | ||
| 148 | sbi_io_memory = cpu_register_io_memory(sbi_mem_read, sbi_mem_write, s); | 165 | sbi_io_memory = cpu_register_io_memory(sbi_mem_read, sbi_mem_write, s); |
| 149 | - cpu_register_physical_memory(addr, SBI_SIZE, sbi_io_memory); | 166 | + sysbus_init_mmio(dev, SBI_SIZE, sbi_io_memory); |
| 150 | 167 | ||
| 151 | - register_savevm("sbi", addr, 1, sbi_save, sbi_load, s); | 168 | + register_savevm("sbi", -1, 1, sbi_save, sbi_load, s); |
| 152 | qemu_register_reset(sbi_reset, s); | 169 | qemu_register_reset(sbi_reset, s); |
| 153 | - *irq = qemu_allocate_irqs(sbi_set_irq, s, 32); | ||
| 154 | - *cpu_irq = qemu_allocate_irqs(sbi_set_timer_irq_cpu, s, MAX_CPUS); | ||
| 155 | sbi_reset(s); | 170 | sbi_reset(s); |
| 171 | +} | ||
| 172 | + | ||
| 173 | +static SysBusDeviceInfo sbi_info = { | ||
| 174 | + .init = sbi_init1, | ||
| 175 | + .qdev.name = "sbi", | ||
| 176 | + .qdev.size = sizeof(SBIState), | ||
| 177 | +}; | ||
| 156 | 178 | ||
| 157 | - return s; | 179 | +static void sbi_register_devices(void) |
| 180 | +{ | ||
| 181 | + sysbus_register_withprop(&sbi_info); | ||
| 158 | } | 182 | } |
| 183 | + | ||
| 184 | +device_init(sbi_register_devices) |
hw/sun4m.c
| @@ -1322,12 +1322,13 @@ static void sun4d_hw_init(const struct sun4d_hwdef *hwdef, ram_addr_t RAM_size, | @@ -1322,12 +1322,13 @@ static void sun4d_hw_init(const struct sun4d_hwdef *hwdef, ram_addr_t RAM_size, | ||
| 1322 | { | 1322 | { |
| 1323 | CPUState *envs[MAX_CPUS]; | 1323 | CPUState *envs[MAX_CPUS]; |
| 1324 | unsigned int i; | 1324 | unsigned int i; |
| 1325 | - void *iounits[MAX_IOUNITS], *espdma, *ledma, *nvram, *sbi; | ||
| 1326 | - qemu_irq *cpu_irqs[MAX_CPUS], *sbi_irq, *sbi_cpu_irq, | 1325 | + void *iounits[MAX_IOUNITS], *espdma, *ledma, *nvram; |
| 1326 | + qemu_irq *cpu_irqs[MAX_CPUS], sbi_irq[32], sbi_cpu_irq[MAX_CPUS], | ||
| 1327 | espdma_irq, ledma_irq; | 1327 | espdma_irq, ledma_irq; |
| 1328 | qemu_irq *esp_reset, *le_reset; | 1328 | qemu_irq *esp_reset, *le_reset; |
| 1329 | unsigned long kernel_size; | 1329 | unsigned long kernel_size; |
| 1330 | void *fw_cfg; | 1330 | void *fw_cfg; |
| 1331 | + DeviceState *dev; | ||
| 1331 | 1332 | ||
| 1332 | /* init CPUs */ | 1333 | /* init CPUs */ |
| 1333 | if (!cpu_model) | 1334 | if (!cpu_model) |
| @@ -1345,7 +1346,14 @@ static void sun4d_hw_init(const struct sun4d_hwdef *hwdef, ram_addr_t RAM_size, | @@ -1345,7 +1346,14 @@ static void sun4d_hw_init(const struct sun4d_hwdef *hwdef, ram_addr_t RAM_size, | ||
| 1345 | 1346 | ||
| 1346 | prom_init(hwdef->slavio_base, bios_name); | 1347 | prom_init(hwdef->slavio_base, bios_name); |
| 1347 | 1348 | ||
| 1348 | - sbi = sbi_init(hwdef->sbi_base, &sbi_irq, &sbi_cpu_irq, cpu_irqs); | 1349 | + dev = sbi_init(hwdef->sbi_base, cpu_irqs); |
| 1350 | + | ||
| 1351 | + for (i = 0; i < 32; i++) { | ||
| 1352 | + sbi_irq[i] = qdev_get_gpio_in(dev, i); | ||
| 1353 | + } | ||
| 1354 | + for (i = 0; i < MAX_CPUS; i++) { | ||
| 1355 | + sbi_cpu_irq[i] = qdev_get_gpio_in(dev, 32 + i); | ||
| 1356 | + } | ||
| 1349 | 1357 | ||
| 1350 | for (i = 0; i < MAX_IOUNITS; i++) | 1358 | for (i = 0; i < MAX_IOUNITS; i++) |
| 1351 | if (hwdef->iounit_bases[i] != (target_phys_addr_t)-1) | 1359 | if (hwdef->iounit_bases[i] != (target_phys_addr_t)-1) |
hw/sun4m.h
| @@ -36,8 +36,7 @@ void slavio_pic_info(Monitor *mon, void *opaque); | @@ -36,8 +36,7 @@ void slavio_pic_info(Monitor *mon, void *opaque); | ||
| 36 | void slavio_irq_info(Monitor *mon, void *opaque); | 36 | void slavio_irq_info(Monitor *mon, void *opaque); |
| 37 | 37 | ||
| 38 | /* sbi.c */ | 38 | /* sbi.c */ |
| 39 | -void *sbi_init(target_phys_addr_t addr, qemu_irq **irq, qemu_irq **cpu_irq, | ||
| 40 | - qemu_irq **parent_irq); | 39 | +DeviceState *sbi_init(target_phys_addr_t addr, qemu_irq **parent_irq); |
| 41 | 40 | ||
| 42 | /* sun4c_intctl.c */ | 41 | /* sun4c_intctl.c */ |
| 43 | void *sun4c_intctl_init(target_phys_addr_t addr, qemu_irq **irq, | 42 | void *sun4c_intctl_init(target_phys_addr_t addr, qemu_irq **irq, |