gwj / at91sam9263 · Commits

Commit 7fa76c0bf3b4d6d2d189587aa118fc5fbbef1238

Authored by blueswir1
1 parent db502b61

Complete the TCG conversion 

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4323 c046a42c-6fe2-441c-8c8c-71466251a162
Inline Side-by-side
Showing 6 changed files with 139 additions and 42 deletions
configure
  View file @7fa76c0
... ... @@ -1291,24 +1291,30 @@ case "$target_cpu" in
1291 1291 ;;
1292 1292 sparc)
1293 1293 echo "TARGET_ARCH=sparc" >> $config_mak
  1294 + echo "CONFIG_NO_DYNGEN_OP=yes" >> $config_mak
1294 1295 echo "#define TARGET_ARCH \"sparc\"" >> $config_h
1295 1296 echo "#define TARGET_SPARC 1" >> $config_h
  1297 + echo "#define CONFIG_NO_DYNGEN_OP 1" >> $config_h
1296 1298 ;;
1297 1299 sparc64)
1298 1300 echo "TARGET_ARCH=sparc64" >> $config_mak
  1301 + echo "CONFIG_NO_DYNGEN_OP=yes" >> $config_mak
1299 1302 echo "#define TARGET_ARCH \"sparc64\"" >> $config_h
1300 1303 echo "#define TARGET_SPARC 1" >> $config_h
1301 1304 echo "#define TARGET_SPARC64 1" >> $config_h
  1305 + echo "#define CONFIG_NO_DYNGEN_OP 1" >> $config_h
1302 1306 elfload32="yes"
1303 1307 ;;
1304 1308 sparc32plus)
1305 1309 echo "TARGET_ARCH=sparc64" >> $config_mak
1306 1310 echo "TARGET_ABI_DIR=sparc" >> $config_mak
1307 1311 echo "TARGET_ARCH2=sparc32plus" >> $config_mak
  1312 + echo "CONFIG_NO_DYNGEN_OP=yes" >> $config_mak
1308 1313 echo "#define TARGET_ARCH \"sparc64\"" >> $config_h
1309 1314 echo "#define TARGET_SPARC 1" >> $config_h
1310 1315 echo "#define TARGET_SPARC64 1" >> $config_h
1311 1316 echo "#define TARGET_ABI32 1" >> $config_h
  1317 + echo "#define CONFIG_NO_DYNGEN_OP 1" >> $config_h
1312 1318 ;;
1313 1319 *)
1314 1320 echo "Unsupported target CPU"
... ...
target-sparc/cpu.h
  View file @7fa76c0
... ... @@ -250,7 +250,7 @@ typedef struct CPUSPARCState {
250 250 float_status fp_status;
251 251 #if defined(TARGET_SPARC64)
252 252 #define MAXTL 4
253   - uint64_t t0, t1, t2;
  253 + uint64_t t0;
254 254 trap_state *tsptr;
255 255 trap_state ts[MAXTL];
256 256 uint32_t xcc; /* Extended integer condition codes */
... ... @@ -271,9 +271,7 @@ typedef struct CPUSPARCState {
271 271 uint64_t hpstate, htstate[MAXTL], hintp, htba, hver, hstick_cmpr, ssr;
272 272 void *hstick; // UA 2005
273 273 #endif
274   -#if !defined(TARGET_SPARC64) && !defined(reg_T2)
275   - target_ulong t2;
276   -#endif
  274 + target_ulong t1, t2;
277 275 } CPUSPARCState;
278 276 #if defined(TARGET_SPARC64)
279 277 #define GET_FSR32(env) (env->fsr & 0xcfc1ffff)
... ...
target-sparc/exec.h
  View file @7fa76c0
... ... @@ -7,12 +7,10 @@ register struct CPUSPARCState *env asm(AREG0);
7 7  
8 8 #ifdef TARGET_SPARC64
9 9 #define T0 (env->t0)
10   -#define T1 (env->t1)
11 10 #define T2 (env->t2)
12 11 #define REGWPTR env->regwptr
13 12 #else
14 13 register uint32_t T0 asm(AREG1);
15   -register uint32_t T1 asm(AREG2);
16 14  
17 15 #undef REG_REGWPTR // Broken
18 16 #ifdef REG_REGWPTR
... ...
target-sparc/helper.h
  View file @7fa76c0
... ... @@ -45,6 +45,13 @@ void TCG_HELPER_PROTO helper_flush(target_ulong addr);
45 45 target_ulong TCG_HELPER_PROTO helper_udiv(target_ulong a, target_ulong b);
46 46 target_ulong TCG_HELPER_PROTO helper_sdiv(target_ulong a, target_ulong b);
47 47 uint64_t TCG_HELPER_PROTO helper_pack64(target_ulong high, target_ulong low);
  48 +void TCG_HELPER_PROTO helper_std_i386(target_ulong addr, int mem_idx);
  49 +void TCG_HELPER_PROTO helper_stdf(target_ulong addr, int mem_idx);
  50 +void TCG_HELPER_PROTO helper_lddf(target_ulong addr, int mem_idx);
  51 +#if defined(CONFIG_USER_ONLY)
  52 +void TCG_HELPER_PROTO helper_ldqf(target_ulong addr);
  53 +void TCG_HELPER_PROTO helper_stqf(target_ulong addr);
  54 +#endif
48 55 uint64_t TCG_HELPER_PROTO helper_ld_asi(target_ulong addr, int asi,
49 56 int size, int sign);
50 57 void TCG_HELPER_PROTO helper_st_asi(target_ulong addr, uint64_t val, int asi,
... ...
target-sparc/op_helper.c
  View file @7fa76c0
... ... @@ -2217,6 +2217,109 @@ uint64_t helper_pack64(target_ulong high, target_ulong low)
2217 2217 return ((uint64_t)high << 32) | (uint64_t)(low & 0xffffffff);
2218 2218 }
2219 2219  
  2220 +#ifdef TARGET_ABI32
  2221 +#define ADDR(x) ((x) & 0xffffffff)
  2222 +#else
  2223 +#define ADDR(x) (x)
  2224 +#endif
  2225 +
  2226 +#ifdef __i386__
  2227 +void helper_std_i386(target_ulong addr, int mem_idx)
  2228 +{
  2229 + uint64_t tmp = ((uint64_t)env->t1 << 32) | (uint64_t)(env->t2 & 0xffffffff);
  2230 +
  2231 +#if !defined(CONFIG_USER_ONLY)
  2232 + switch (mem_idx) {
  2233 + case 0:
  2234 + stq_user(ADDR(addr), tmp);
  2235 + break;
  2236 + case 1:
  2237 + stq_kernel(ADDR(addr), tmp);
  2238 + break;
  2239 +#ifdef TARGET_SPARC64
  2240 + case 2:
  2241 + stq_hypv(ADDR(addr), tmp);
  2242 + break;
  2243 +#endif
  2244 + default:
  2245 + break;
  2246 + }
  2247 +#else
  2248 + stq_raw(ADDR(addr), tmp);
  2249 +#endif
  2250 +}
  2251 +#endif /* __i386__ */
  2252 +
  2253 +void helper_stdf(target_ulong addr, int mem_idx)
  2254 +{
  2255 +#if !defined(CONFIG_USER_ONLY)
  2256 + switch (mem_idx) {
  2257 + case 0:
  2258 + stfq_user(ADDR(addr), DT0);
  2259 + break;
  2260 + case 1:
  2261 + stfq_kernel(ADDR(addr), DT0);
  2262 + break;
  2263 +#ifdef TARGET_SPARC64
  2264 + case 2:
  2265 + stfq_hypv(ADDR(addr), DT0);
  2266 + break;
  2267 +#endif
  2268 + default:
  2269 + break;
  2270 + }
  2271 +#else
  2272 + stfq_raw(ADDR(addr), DT0);
  2273 +#endif
  2274 +}
  2275 +
  2276 +void helper_lddf(target_ulong addr, int mem_idx)
  2277 +{
  2278 +#if !defined(CONFIG_USER_ONLY)
  2279 + switch (mem_idx) {
  2280 + case 0:
  2281 + DT0 = ldfq_user(ADDR(addr));
  2282 + break;
  2283 + case 1:
  2284 + DT0 = ldfq_kernel(ADDR(addr));
  2285 + break;
  2286 +#ifdef TARGET_SPARC64
  2287 + case 2:
  2288 + DT0 = ldfq_hypv(ADDR(addr));
  2289 + break;
  2290 +#endif
  2291 + default:
  2292 + break;
  2293 + }
  2294 +#else
  2295 + DT0 = ldfq_raw(ADDR(addr));
  2296 +#endif
  2297 +}
  2298 +
  2299 +#if defined(CONFIG_USER_ONLY)
  2300 +void helper_ldqf(target_ulong addr)
  2301 +{
  2302 + // XXX add 128 bit load
  2303 + CPU_QuadU u;
  2304 +
  2305 + u.ll.upper = ldq_raw(ADDR(addr));
  2306 + u.ll.lower = ldq_raw(ADDR(addr + 8));
  2307 + QT0 = u.q;
  2308 +}
  2309 +
  2310 +void helper_stqf(target_ulong addr)
  2311 +{
  2312 + // XXX add 128 bit store
  2313 + CPU_QuadU u;
  2314 +
  2315 + u.q = QT0;
  2316 + stq_raw(ADDR(addr), u.ll.upper);
  2317 + stq_raw(ADDR(addr + 8), u.ll.lower);
  2318 +}
  2319 +#endif
  2320 +
  2321 +#undef ADDR
  2322 +
2220 2323 void helper_ldfsr(void)
2221 2324 {
2222 2325 int rnd_mode;
... ...
target-sparc/translate.c
  View file @7fa76c0
... ... @@ -184,33 +184,12 @@ static void gen_op_store_QT0_fpr(unsigned int dst)
184 184 #ifdef TARGET_SPARC64
185 185 #define hypervisor(dc) 0
186 186 #endif
187   -#define gen_op_ldst(name) gen_op_##name##_raw()
188 187 #else
189 188 #define supervisor(dc) (dc->mem_idx >= 1)
190 189 #ifdef TARGET_SPARC64
191 190 #define hypervisor(dc) (dc->mem_idx == 2)
192   -#define OP_LD_TABLE(width) \
193   - static GenOpFunc * const gen_op_##width[] = { \
194   - &gen_op_##width##_user, \
195   - &gen_op_##width##_kernel, \
196   - &gen_op_##width##_hypv, \
197   - };
198 191 #else
199   -#define OP_LD_TABLE(width) \
200   - static GenOpFunc * const gen_op_##width[] = { \
201   - &gen_op_##width##_user, \
202   - &gen_op_##width##_kernel, \
203   - };
204 192 #endif
205   -#define gen_op_ldst(name) (*gen_op_##name[dc->mem_idx])()
206   -#endif
207   -
208   -#ifndef CONFIG_USER_ONLY
209   -#ifdef __i386__
210   -OP_LD_TABLE(std);
211   -#endif /* __i386__ */
212   -OP_LD_TABLE(stdf);
213   -OP_LD_TABLE(lddf);
214 193 #endif
215 194  
216 195 #ifdef TARGET_ABI32
... ... @@ -4209,16 +4188,19 @@ static void disas_sparc_insn(DisasContext * dc)
4209 4188 break;
4210 4189 case 0x22: /* load quad fpreg */
4211 4190 #if defined(CONFIG_USER_ONLY)
4212   - tcg_gen_helper_0_2(helper_check_align, cpu_addr, tcg_const_i32(7));
4213   - gen_op_ldst(ldqf);
  4191 + tcg_gen_helper_0_2(helper_check_align, cpu_addr,
  4192 + tcg_const_i32(7));
  4193 + tcg_gen_helper_0_1(helper_ldqf, cpu_addr);
4214 4194 gen_op_store_QT0_fpr(QFPREG(rd));
4215 4195 break;
4216 4196 #else
4217 4197 goto nfpu_insn;
4218 4198 #endif
4219 4199 case 0x23: /* load double fpreg */
4220   - tcg_gen_helper_0_2(helper_check_align, cpu_addr, tcg_const_i32(7));
4221   - gen_op_ldst(lddf);
  4200 + tcg_gen_helper_0_2(helper_check_align, cpu_addr,
  4201 + tcg_const_i32(7));
  4202 + tcg_gen_helper_0_2(helper_lddf, cpu_addr,
  4203 + tcg_const_i32(dc->mem_idx));
4222 4204 gen_op_store_DT0_fpr(DFPREG(rd));
4223 4205 break;
4224 4206 default:
... ... @@ -4245,23 +4227,23 @@ static void disas_sparc_insn(DisasContext * dc)
4245 4227 case 0x7: /* store double word */
4246 4228 if (rd & 1)
4247 4229 goto illegal_insn;
4248   -#ifndef __i386__
4249 4230 else {
4250 4231 TCGv r_low;
4251 4232  
4252 4233 tcg_gen_helper_0_2(helper_check_align, cpu_addr, tcg_const_i32(7));
4253 4234 r_low = tcg_temp_new(TCG_TYPE_I32);
4254 4235 gen_movl_reg_TN(rd + 1, r_low);
  4236 +#ifndef __i386__
4255 4237 tcg_gen_helper_1_2(helper_pack64, cpu_tmp64, cpu_val,
4256 4238 r_low);
4257 4239 tcg_gen_qemu_st64(cpu_tmp64, cpu_addr, dc->mem_idx);
4258   - }
4259 4240 #else /* __i386__ */
4260   - tcg_gen_helper_0_2(helper_check_align, cpu_addr, tcg_const_i32(7));
4261   - flush_cond(dc, cpu_cond);
4262   - gen_movl_reg_TN(rd + 1, cpu_cond);
4263   - gen_op_ldst(std);
  4241 + tcg_gen_st_tl(cpu_val, cpu_env, offsetof(CPUState, t1));
  4242 + tcg_gen_st_tl(r_low, cpu_env, offsetof(CPUState, t2));
  4243 + tcg_gen_helper_0_2(helper_std_i386, cpu_addr,
  4244 + tcg_const_i32(dc->mem_idx));
4264 4245 #endif /* __i386__ */
  4246 + }
4265 4247 break;
4266 4248 #if !defined(CONFIG_USER_ONLY) || defined(TARGET_SPARC64)
4267 4249 case 0x14: /* store word alternate */
... ... @@ -4345,9 +4327,10 @@ static void disas_sparc_insn(DisasContext * dc)
4345 4327 #ifdef TARGET_SPARC64
4346 4328 #if defined(CONFIG_USER_ONLY)
4347 4329 /* V9 stqf, store quad fpreg */
4348   - tcg_gen_helper_0_2(helper_check_align, cpu_addr, tcg_const_i32(7));
  4330 + tcg_gen_helper_0_2(helper_check_align, cpu_addr,
  4331 + tcg_const_i32(7));
4349 4332 gen_op_load_fpr_QT0(QFPREG(rd));
4350   - gen_op_ldst(stqf);
  4333 + tcg_gen_helper_0_1(helper_stqf, cpu_addr);
4351 4334 break;
4352 4335 #else
4353 4336 goto nfpu_insn;
... ... @@ -4364,10 +4347,12 @@ static void disas_sparc_insn(DisasContext * dc)
4364 4347 goto nfq_insn;
4365 4348 #endif
4366 4349 #endif
4367   - case 0x27:
4368   - tcg_gen_helper_0_2(helper_check_align, cpu_addr, tcg_const_i32(7));
  4350 + case 0x27: /* store double fpreg */
  4351 + tcg_gen_helper_0_2(helper_check_align, cpu_addr,
  4352 + tcg_const_i32(7));
4369 4353 gen_op_load_fpr_DT0(DFPREG(rd));
4370   - gen_op_ldst(stdf);
  4354 + tcg_gen_helper_0_2(helper_stdf, cpu_addr,
  4355 + tcg_const_i32(dc->mem_idx));
4371 4356 break;
4372 4357 default:
4373 4358 goto illegal_insn;
... ...