gwj / at91sam9263 · Commits

Commit 7e4597d7aea6a085f5ebfcfe56654d4c46a2ede7

Authored by bellard
1 parent 437a88a5

added debug_insn_start debug instruction 

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4531 c046a42c-6fe2-441c-8c8c-71466251a162
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Showing 3 changed files with 43 additions and 3 deletions
tcg/tcg-op.h
  View file @7e4597d
... ... @@ -1291,6 +1291,18 @@ static inline void tcg_gen_macro_2(TCGv ret0, TCGv ret1, int macro_id)
1291 1291 #error must include QEMU headers
1292 1292 #endif
1293 1293  
  1294 +/* debug info: write the PC of the corresponding QEMU CPU instruction */
  1295 +static inline void tcg_gen_debug_insn_start(uint64_t pc)
  1296 +{
  1297 + /* XXX: must really use a 32 bit size for TCGArg in all cases */
  1298 +#if TARGET_LONG_BITS > TCG_TARGET_REG_BITS
  1299 + tcg_gen_op2i(INDEX_op_debug_insn_start,
  1300 + (uint32_t)(pc), (uint32_t)(pc >> 32));
  1301 +#else
  1302 + tcg_gen_op1i(INDEX_op_debug_insn_start, pc);
  1303 +#endif
  1304 +}
  1305 +
1294 1306 static inline void tcg_gen_exit_tb(tcg_target_long val)
1295 1307 {
1296 1308 tcg_gen_op1i(INDEX_op_exit_tb, val);
... ...
tcg/tcg-opc.h
  View file @7e4597d
... ... @@ -156,6 +156,11 @@ DEF2(neg_i64, 1, 1, 0, 0)
156 156 #endif
157 157  
158 158 /* QEMU specific */
  159 +#if TARGET_LONG_BITS > TCG_TARGET_REG_BITS
  160 +DEF2(debug_insn_start, 0, 0, 2, 0)
  161 +#else
  162 +DEF2(debug_insn_start, 0, 0, 1, 0)
  163 +#endif
159 164 DEF2(exit_tb, 0, 0, 1, TCG_OPF_BB_END | TCG_OPF_SIDE_EFFECTS)
160 165 DEF2(goto_tb, 0, 0, 1, TCG_OPF_BB_END | TCG_OPF_SIDE_EFFECTS)
161 166 /* Note: even if TARGET_LONG_BITS is not defined, the INDEX_op
... ...
tcg/tcg.c
  View file @7e4597d
... ... @@ -743,17 +743,31 @@ void tcg_dump_ops(TCGContext *s, FILE *outfile)
743 743 const uint16_t *opc_ptr;
744 744 const TCGArg *args;
745 745 TCGArg arg;
746   - int c, i, k, nb_oargs, nb_iargs, nb_cargs;
  746 + int c, i, k, nb_oargs, nb_iargs, nb_cargs, first_insn;
747 747 const TCGOpDef *def;
748 748 char buf[128];
749 749  
  750 + first_insn = 1;
750 751 opc_ptr = gen_opc_buf;
751 752 args = gen_opparam_buf;
752 753 while (opc_ptr < gen_opc_ptr) {
753 754 c = *opc_ptr++;
754 755 def = &tcg_op_defs[c];
755   - fprintf(outfile, " %s ", def->name);
756   - if (c == INDEX_op_call) {
  756 + if (c == INDEX_op_debug_insn_start) {
  757 + uint64_t pc;
  758 +#if TARGET_LONG_BITS > TCG_TARGET_REG_BITS
  759 + pc = ((uint64_t)args[1] << 32) | args[0];
  760 +#else
  761 + pc = args[0];
  762 +#endif
  763 + if (!first_insn)
  764 + fprintf(outfile, "\n");
  765 + fprintf(outfile, " ---- 0x%" PRIx64, pc);
  766 + first_insn = 0;
  767 + nb_oargs = def->nb_oargs;
  768 + nb_iargs = def->nb_iargs;
  769 + nb_cargs = def->nb_cargs;
  770 + } else if (c == INDEX_op_call) {
757 771 TCGArg arg;
758 772  
759 773 /* variable number of arguments */
... ... @@ -762,6 +776,8 @@ void tcg_dump_ops(TCGContext *s, FILE *outfile)
762 776 nb_iargs = arg & 0xffff;
763 777 nb_cargs = def->nb_cargs;
764 778  
  779 + fprintf(outfile, " %s ", def->name);
  780 +
765 781 /* function name */
766 782 fprintf(outfile, "%s",
767 783 tcg_get_helper_str_idx(s, buf, sizeof(buf), args[nb_oargs + nb_iargs - 1]));
... ... @@ -785,6 +801,7 @@ void tcg_dump_ops(TCGContext *s, FILE *outfile)
785 801 }
786 802 }
787 803 } else {
  804 + fprintf(outfile, " %s ", def->name);
788 805 if (c == INDEX_op_nopn) {
789 806 /* variable number of arguments */
790 807 nb_cargs = *args;
... ... @@ -1037,6 +1054,9 @@ void tcg_liveness_analysis(TCGContext *s)
1037 1054 /* mark end of basic block */
1038 1055 tcg_la_bb_end(s, dead_temps);
1039 1056 break;
  1057 + case INDEX_op_debug_insn_start:
  1058 + args -= def->nb_args;
  1059 + break;
1040 1060 case INDEX_op_nopn:
1041 1061 nb_args = args[-1];
1042 1062 args -= nb_args;
... ... @@ -1840,6 +1860,9 @@ static inline int tcg_gen_code_common(TCGContext *s, uint8_t *gen_code_buf,
1840 1860 dead_iargs = s->op_dead_iargs[op_index];
1841 1861 tcg_reg_alloc_mov(s, def, args, dead_iargs);
1842 1862 break;
  1863 + case INDEX_op_debug_insn_start:
  1864 + /* debug instruction */
  1865 + break;
1843 1866 case INDEX_op_nop:
1844 1867 case INDEX_op_nop1:
1845 1868 case INDEX_op_nop2:
... ...