Commit 7d83131cc5ea95d7bb98658ac958a901ba4269de
1 parent
66e85a21
use inline function
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@263 c046a42c-6fe2-441c-8c8c-71466251a162
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11 additions
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1 deletions
translate-arm.c
| @@ -655,7 +655,7 @@ static void disas_arm_insn(DisasContext *s) | @@ -655,7 +655,7 @@ static void disas_arm_insn(DisasContext *s) | ||
| 655 | /* generate intermediate code in gen_opc_buf and gen_opparam_buf for | 655 | /* generate intermediate code in gen_opc_buf and gen_opparam_buf for |
| 656 | basic block 'tb'. If search_pc is TRUE, also generate PC | 656 | basic block 'tb'. If search_pc is TRUE, also generate PC |
| 657 | information for each intermediate instruction. */ | 657 | information for each intermediate instruction. */ |
| 658 | -int gen_intermediate_code(TranslationBlock *tb, int search_pc) | 658 | +static inline int gen_intermediate_code_internal(TranslationBlock *tb, int search_pc) |
| 659 | { | 659 | { |
| 660 | DisasContext dc1, *dc = &dc1; | 660 | DisasContext dc1, *dc = &dc1; |
| 661 | uint16_t *gen_opc_end; | 661 | uint16_t *gen_opc_end; |
| @@ -717,6 +717,16 @@ int gen_intermediate_code(TranslationBlock *tb, int search_pc) | @@ -717,6 +717,16 @@ int gen_intermediate_code(TranslationBlock *tb, int search_pc) | ||
| 717 | return 0; | 717 | return 0; |
| 718 | } | 718 | } |
| 719 | 719 | ||
| 720 | +int gen_intermediate_code(TranslationBlock *tb) | ||
| 721 | +{ | ||
| 722 | + return gen_intermediate_code_internal(tb, 0); | ||
| 723 | +} | ||
| 724 | + | ||
| 725 | +int gen_intermediate_code_pc(TranslationBlock *tb) | ||
| 726 | +{ | ||
| 727 | + return gen_intermediate_code_internal(tb, 1); | ||
| 728 | +} | ||
| 729 | + | ||
| 720 | CPUARMState *cpu_arm_init(void) | 730 | CPUARMState *cpu_arm_init(void) |
| 721 | { | 731 | { |
| 722 | CPUARMState *env; | 732 | CPUARMState *env; |