gwj / at91sam9263 · Commits

Commit 7cc0dd20e1cc43529aac51b7680be857fad90065

Authored by aurel32
1 parent cf3ebac7

Malta & OMAP: add a name to char devices 

(fixes regression introduced by r5575)

Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5585 c046a42c-6fe2-441c-8c8c-71466251a162
Inline Side-by-side
Showing 3 changed files with 5 additions and 5 deletions
hw/mips_malta.c
  View file @7cc0dd2
... ... @@ -435,7 +435,7 @@ static MaltaFPGAState *malta_fpga_init(target_phys_addr_t base, CPUState *env)
435 435 cpu_register_physical_memory(base, 0x900, malta);
436 436 cpu_register_physical_memory(base + 0xa00, 0x100000 - 0xa00, malta);
437 437  
438   - s->display = qemu_chr_open("vc:320x200");
  438 + s->display = qemu_chr_open("fpga", "vc:320x200");
439 439 qemu_chr_printf(s->display, "\e[HMalta LEDBAR\r\n");
440 440 qemu_chr_printf(s->display, "+--------+\r\n");
441 441 qemu_chr_printf(s->display, "+ +\r\n");
... ... @@ -446,7 +446,7 @@ static MaltaFPGAState *malta_fpga_init(target_phys_addr_t base, CPUState *env)
446 446 qemu_chr_printf(s->display, "+ +\r\n");
447 447 qemu_chr_printf(s->display, "+--------+\r\n");
448 448  
449   - uart_chr = qemu_chr_open("vc:80Cx24C");
  449 + uart_chr = qemu_chr_open("cbus", "vc:80Cx24C");
450 450 qemu_chr_printf(uart_chr, "CBUS UART\r\n");
451 451 s->uart =
452 452 serial_mm_init(base + 0x900, 3, env->irq[2], 230400, uart_chr, 1);
... ...
hw/omap1.c
  View file @7cc0dd2
... ... @@ -2017,7 +2017,7 @@ struct omap_uart_s *omap_uart_init(target_phys_addr_t base,
2017 2017 s->fclk = fclk;
2018 2018 s->irq = irq;
2019 2019 s->serial = serial_mm_init(base, 2, irq, omap_clk_getrate(fclk)/16,
2020   - chr ?: qemu_chr_open("null"), 1);
  2020 + chr ?: qemu_chr_open("null", "null"), 1);
2021 2021  
2022 2022 return s;
2023 2023 }
... ... @@ -2128,7 +2128,7 @@ void omap_uart_attach(struct omap_uart_s *s, CharDriverState *chr)
2128 2128 /* TODO: Should reuse or destroy current s->serial */
2129 2129 s->serial = serial_mm_init(s->base, 2, s->irq,
2130 2130 omap_clk_getrate(s->fclk) / 16,
2131   - chr ?: qemu_chr_open("null"), 1);
  2131 + chr ?: qemu_chr_open("null", "null"), 1);
2132 2132 }
2133 2133  
2134 2134 /* MPU Clock/Reset/Power Mode Control */
... ...
hw/omap2.c
  View file @7cc0dd2
... ... @@ -2185,7 +2185,7 @@ static struct omap_sti_s *omap_sti_init(struct omap_target_agent_s *ta,
2185 2185 s->irq = irq;
2186 2186 omap_sti_reset(s);
2187 2187  
2188   - s->chr = chr ?: qemu_chr_open("null");
  2188 + s->chr = chr ?: qemu_chr_open("null", "null");
2189 2189  
2190 2190 iomemtype = l4_register_io_memory(0, omap_sti_readfn,
2191 2191 omap_sti_writefn, s);
... ...