Commit 7c23b8920329180f48b8a147b629d8837709d201
1 parent
dd48594e
E1000 NIC emulation (Nir Peleg, patch from Dor Laor).
Applied %s/^\([^I ]*\)^I/\1 /g on e1000.c and added e1000 to help message. git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3949 c046a42c-6fe2-441c-8c8c-71466251a162
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2 deletions
Makefile.target
@@ -524,6 +524,7 @@ OBJS += eepro100.o | @@ -524,6 +524,7 @@ OBJS += eepro100.o | ||
524 | OBJS += ne2000.o | 524 | OBJS += ne2000.o |
525 | OBJS += pcnet.o | 525 | OBJS += pcnet.o |
526 | OBJS += rtl8139.o | 526 | OBJS += rtl8139.o |
527 | +OBJS += e1000.o | ||
527 | 528 | ||
528 | ifeq ($(TARGET_BASE_ARCH), i386) | 529 | ifeq ($(TARGET_BASE_ARCH), i386) |
529 | # Hardware support | 530 | # Hardware support |
hw/e1000.c
0 → 100644
1 | +/* | ||
2 | + * QEMU e1000 emulation | ||
3 | + * | ||
4 | + * Nir Peleg, Tutis Systems Ltd. for Qumranet Inc. | ||
5 | + * Copyright (c) 2008 Qumranet | ||
6 | + * Based on work done by: | ||
7 | + * Copyright (c) 2007 Dan Aloni | ||
8 | + * Copyright (c) 2004 Antony T Curtis | ||
9 | + * | ||
10 | + * This library is free software; you can redistribute it and/or | ||
11 | + * modify it under the terms of the GNU Lesser General Public | ||
12 | + * License as published by the Free Software Foundation; either | ||
13 | + * version 2 of the License, or (at your option) any later version. | ||
14 | + * | ||
15 | + * This library is distributed in the hope that it will be useful, | ||
16 | + * but WITHOUT ANY WARRANTY; without even the implied warranty of | ||
17 | + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU | ||
18 | + * Lesser General Public License for more details. | ||
19 | + * | ||
20 | + * You should have received a copy of the GNU Lesser General Public | ||
21 | + * License along with this library; if not, write to the Free Software | ||
22 | + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | ||
23 | + */ | ||
24 | + | ||
25 | + | ||
26 | +#include "hw.h" | ||
27 | +#include "pci.h" | ||
28 | +#include "net.h" | ||
29 | + | ||
30 | +#define __iomem | ||
31 | +typedef int boolean_t; | ||
32 | +#include "e1000_hw.h" | ||
33 | + | ||
34 | +#define DEBUG | ||
35 | + | ||
36 | +#ifdef DEBUG | ||
37 | +enum { | ||
38 | + DEBUG_GENERAL, DEBUG_IO, DEBUG_MMIO, DEBUG_INTERRUPT, | ||
39 | + DEBUG_RX, DEBUG_TX, DEBUG_MDIC, DEBUG_EEPROM, | ||
40 | + DEBUG_UNKNOWN, DEBUG_TXSUM, DEBUG_TXERR, DEBUG_RXERR, | ||
41 | + DEBUG_RXFILTER, DEBUG_NOTYET, | ||
42 | +}; | ||
43 | +#define DBGBIT(x) (1<<DEBUG_##x) | ||
44 | +static int debugflags = DBGBIT(TXERR) | DBGBIT(GENERAL); | ||
45 | + | ||
46 | +#define DBGOUT(what, fmt, params...) do { \ | ||
47 | + if (debugflags & DBGBIT(what)) \ | ||
48 | + fprintf(stderr, "e1000: " fmt, ##params); \ | ||
49 | + } while (0) | ||
50 | +#else | ||
51 | +#define DBGOUT(what, fmt, params...) do {} while (0) | ||
52 | +#endif | ||
53 | + | ||
54 | +#define IOPORT_SIZE 0x40 | ||
55 | +#define PNPMMIO_SIZE 0x60000 | ||
56 | + | ||
57 | +/* | ||
58 | + * HW models: | ||
59 | + * E1000_DEV_ID_82540EM works with Windows and Linux | ||
60 | + * E1000_DEV_ID_82573L OK with windoze and Linux 2.6.22, | ||
61 | + * appears to perform better than 82540EM, but breaks with Linux 2.6.18 | ||
62 | + * E1000_DEV_ID_82544GC_COPPER appears to work; not well tested | ||
63 | + * Others never tested | ||
64 | + */ | ||
65 | +enum { E1000_DEVID = E1000_DEV_ID_82540EM }; | ||
66 | + | ||
67 | +/* | ||
68 | + * May need to specify additional MAC-to-PHY entries -- | ||
69 | + * Intel's Windows driver refuses to initialize unless they match | ||
70 | + */ | ||
71 | +enum { | ||
72 | + PHY_ID2_INIT = E1000_DEVID == E1000_DEV_ID_82573L ? 0xcc2 : | ||
73 | + E1000_DEVID == E1000_DEV_ID_82544GC_COPPER ? 0xc30 : | ||
74 | + /* default to E1000_DEV_ID_82540EM */ 0xc20 | ||
75 | +}; | ||
76 | + | ||
77 | +typedef struct E1000State_st { | ||
78 | + PCIDevice dev; | ||
79 | + VLANClientState *vc; | ||
80 | + NICInfo *nd; | ||
81 | + uint32_t instance; | ||
82 | + uint32_t mmio_base; | ||
83 | + int mmio_index; | ||
84 | + | ||
85 | + uint32_t mac_reg[0x8000]; | ||
86 | + uint16_t phy_reg[0x20]; | ||
87 | + uint16_t eeprom_data[64]; | ||
88 | + | ||
89 | + uint32_t rxbuf_size; | ||
90 | + uint32_t rxbuf_min_shift; | ||
91 | + int check_rxov; | ||
92 | + struct e1000_tx { | ||
93 | + unsigned char header[256]; | ||
94 | + unsigned char data[0x10000]; | ||
95 | + uint16_t size; | ||
96 | + unsigned char sum_needed; | ||
97 | + uint8_t ipcss; | ||
98 | + uint8_t ipcso; | ||
99 | + uint16_t ipcse; | ||
100 | + uint8_t tucss; | ||
101 | + uint8_t tucso; | ||
102 | + uint16_t tucse; | ||
103 | + uint8_t hdr_len; | ||
104 | + uint16_t mss; | ||
105 | + uint32_t paylen; | ||
106 | + uint16_t tso_frames; | ||
107 | + char tse; | ||
108 | + char ip; | ||
109 | + char tcp; | ||
110 | + } tx; | ||
111 | + | ||
112 | + struct { | ||
113 | + uint32_t val_in; // shifted in from guest driver | ||
114 | + uint16_t bitnum_in; | ||
115 | + uint16_t bitnum_out; | ||
116 | + uint16_t reading; | ||
117 | + uint32_t old_eecd; | ||
118 | + } eecd_state; | ||
119 | +} E1000State; | ||
120 | + | ||
121 | +#define defreg(x) x = (E1000_##x>>2) | ||
122 | +enum { | ||
123 | + defreg(CTRL), defreg(EECD), defreg(EERD), defreg(GPRC), | ||
124 | + defreg(GPTC), defreg(ICR), defreg(ICS), defreg(IMC), | ||
125 | + defreg(IMS), defreg(LEDCTL), defreg(MANC), defreg(MDIC), | ||
126 | + defreg(MPC), defreg(PBA), defreg(RCTL), defreg(RDBAH), | ||
127 | + defreg(RDBAL), defreg(RDH), defreg(RDLEN), defreg(RDT), | ||
128 | + defreg(STATUS), defreg(SWSM), defreg(TCTL), defreg(TDBAH), | ||
129 | + defreg(TDBAL), defreg(TDH), defreg(TDLEN), defreg(TDT), | ||
130 | + defreg(TORH), defreg(TORL), defreg(TOTH), defreg(TOTL), | ||
131 | + defreg(TPR), defreg(TPT), defreg(TXDCTL), defreg(WUFC), | ||
132 | + defreg(RA), defreg(MTA), defreg(CRCERRS), | ||
133 | +}; | ||
134 | + | ||
135 | +enum { PHY_R = 1, PHY_W = 2, PHY_RW = PHY_R | PHY_W }; | ||
136 | +static char phy_regcap[0x20] = { | ||
137 | + [PHY_STATUS] = PHY_R, [M88E1000_EXT_PHY_SPEC_CTRL] = PHY_RW, | ||
138 | + [PHY_ID1] = PHY_R, [M88E1000_PHY_SPEC_CTRL] = PHY_RW, | ||
139 | + [PHY_CTRL] = PHY_RW, [PHY_1000T_CTRL] = PHY_RW, | ||
140 | + [PHY_LP_ABILITY] = PHY_R, [PHY_1000T_STATUS] = PHY_R, | ||
141 | + [PHY_AUTONEG_ADV] = PHY_RW, [M88E1000_RX_ERR_CNTR] = PHY_R, | ||
142 | + [PHY_ID2] = PHY_R, | ||
143 | +}; | ||
144 | + | ||
145 | +static void | ||
146 | +ioport_map(PCIDevice *pci_dev, int region_num, uint32_t addr, | ||
147 | + uint32_t size, int type) | ||
148 | +{ | ||
149 | + DBGOUT(IO, "e1000_ioport_map addr=0x%04x size=0x%08x\n", addr, size); | ||
150 | +} | ||
151 | + | ||
152 | +static void | ||
153 | +set_interrupt_cause(E1000State *s, int index, uint32_t val) | ||
154 | +{ | ||
155 | + if (val) | ||
156 | + val |= E1000_ICR_INT_ASSERTED; | ||
157 | + s->mac_reg[ICR] = val; | ||
158 | + qemu_set_irq(s->dev.irq[0], (s->mac_reg[IMS] & s->mac_reg[ICR]) != 0); | ||
159 | +} | ||
160 | + | ||
161 | +static void | ||
162 | +set_ics(E1000State *s, int index, uint32_t val) | ||
163 | +{ | ||
164 | + DBGOUT(INTERRUPT, "set_ics %x, ICR %x, IMR %x\n", val, s->mac_reg[ICR], | ||
165 | + s->mac_reg[IMS]); | ||
166 | + set_interrupt_cause(s, 0, val | s->mac_reg[ICR]); | ||
167 | +} | ||
168 | + | ||
169 | +static int | ||
170 | +rxbufsize(uint32_t v) | ||
171 | +{ | ||
172 | + v &= E1000_RCTL_BSEX | E1000_RCTL_SZ_16384 | E1000_RCTL_SZ_8192 | | ||
173 | + E1000_RCTL_SZ_4096 | E1000_RCTL_SZ_2048 | E1000_RCTL_SZ_1024 | | ||
174 | + E1000_RCTL_SZ_512 | E1000_RCTL_SZ_256; | ||
175 | + switch (v) { | ||
176 | + case E1000_RCTL_BSEX | E1000_RCTL_SZ_16384: | ||
177 | + return 16384; | ||
178 | + case E1000_RCTL_BSEX | E1000_RCTL_SZ_8192: | ||
179 | + return 8192; | ||
180 | + case E1000_RCTL_BSEX | E1000_RCTL_SZ_4096: | ||
181 | + return 4096; | ||
182 | + case E1000_RCTL_SZ_1024: | ||
183 | + return 1024; | ||
184 | + case E1000_RCTL_SZ_512: | ||
185 | + return 512; | ||
186 | + case E1000_RCTL_SZ_256: | ||
187 | + return 256; | ||
188 | + } | ||
189 | + return 2048; | ||
190 | +} | ||
191 | + | ||
192 | +static void | ||
193 | +set_rx_control(E1000State *s, int index, uint32_t val) | ||
194 | +{ | ||
195 | + s->mac_reg[RCTL] = val; | ||
196 | + s->rxbuf_size = rxbufsize(val); | ||
197 | + s->rxbuf_min_shift = ((val / E1000_RCTL_RDMTS_QUAT) & 3) + 1; | ||
198 | + DBGOUT(RX, "RCTL: %d, mac_reg[RCTL] = 0x%x\n", s->mac_reg[RDT], | ||
199 | + s->mac_reg[RCTL]); | ||
200 | +} | ||
201 | + | ||
202 | +static void | ||
203 | +set_mdic(E1000State *s, int index, uint32_t val) | ||
204 | +{ | ||
205 | + uint32_t data = val & E1000_MDIC_DATA_MASK; | ||
206 | + uint32_t addr = ((val & E1000_MDIC_REG_MASK) >> E1000_MDIC_REG_SHIFT); | ||
207 | + | ||
208 | + if ((val & E1000_MDIC_PHY_MASK) >> E1000_MDIC_PHY_SHIFT != 1) // phy # | ||
209 | + val = s->mac_reg[MDIC] | E1000_MDIC_ERROR; | ||
210 | + else if (val & E1000_MDIC_OP_READ) { | ||
211 | + DBGOUT(MDIC, "MDIC read reg 0x%x\n", addr); | ||
212 | + if (!(phy_regcap[addr] & PHY_R)) { | ||
213 | + DBGOUT(MDIC, "MDIC read reg %x unhandled\n", addr); | ||
214 | + val |= E1000_MDIC_ERROR; | ||
215 | + } else | ||
216 | + val = (val ^ data) | s->phy_reg[addr]; | ||
217 | + } else if (val & E1000_MDIC_OP_WRITE) { | ||
218 | + DBGOUT(MDIC, "MDIC write reg 0x%x, value 0x%x\n", addr, data); | ||
219 | + if (!(phy_regcap[addr] & PHY_W)) { | ||
220 | + DBGOUT(MDIC, "MDIC write reg %x unhandled\n", addr); | ||
221 | + val |= E1000_MDIC_ERROR; | ||
222 | + } else | ||
223 | + s->phy_reg[addr] = data; | ||
224 | + } | ||
225 | + s->mac_reg[MDIC] = val | E1000_MDIC_READY; | ||
226 | + set_ics(s, 0, E1000_ICR_MDAC); | ||
227 | +} | ||
228 | + | ||
229 | +static uint32_t | ||
230 | +get_eecd(E1000State *s, int index) | ||
231 | +{ | ||
232 | + uint32_t ret = E1000_EECD_PRES|E1000_EECD_GNT | s->eecd_state.old_eecd; | ||
233 | + | ||
234 | + DBGOUT(EEPROM, "reading eeprom bit %d (reading %d)\n", | ||
235 | + s->eecd_state.bitnum_out, s->eecd_state.reading); | ||
236 | + if (!s->eecd_state.reading || | ||
237 | + ((s->eeprom_data[(s->eecd_state.bitnum_out >> 4) & 0x3f] >> | ||
238 | + ((s->eecd_state.bitnum_out & 0xf) ^ 0xf))) & 1) | ||
239 | + ret |= E1000_EECD_DO; | ||
240 | + return ret; | ||
241 | +} | ||
242 | + | ||
243 | +static void | ||
244 | +set_eecd(E1000State *s, int index, uint32_t val) | ||
245 | +{ | ||
246 | + uint32_t oldval = s->eecd_state.old_eecd; | ||
247 | + | ||
248 | + s->eecd_state.old_eecd = val & (E1000_EECD_SK | E1000_EECD_CS | | ||
249 | + E1000_EECD_DI|E1000_EECD_FWE_MASK|E1000_EECD_REQ); | ||
250 | + if (!(E1000_EECD_SK & (val ^ oldval))) // no clock edge | ||
251 | + return; | ||
252 | + if (!(E1000_EECD_SK & val)) { // falling edge | ||
253 | + s->eecd_state.bitnum_out++; | ||
254 | + return; | ||
255 | + } | ||
256 | + if (!(val & E1000_EECD_CS)) { // rising, no CS (EEPROM reset) | ||
257 | + memset(&s->eecd_state, 0, sizeof s->eecd_state); | ||
258 | + return; | ||
259 | + } | ||
260 | + s->eecd_state.val_in <<= 1; | ||
261 | + if (val & E1000_EECD_DI) | ||
262 | + s->eecd_state.val_in |= 1; | ||
263 | + if (++s->eecd_state.bitnum_in == 9 && !s->eecd_state.reading) { | ||
264 | + s->eecd_state.bitnum_out = ((s->eecd_state.val_in & 0x3f)<<4)-1; | ||
265 | + s->eecd_state.reading = (((s->eecd_state.val_in >> 6) & 7) == | ||
266 | + EEPROM_READ_OPCODE_MICROWIRE); | ||
267 | + } | ||
268 | + DBGOUT(EEPROM, "eeprom bitnum in %d out %d, reading %d\n", | ||
269 | + s->eecd_state.bitnum_in, s->eecd_state.bitnum_out, | ||
270 | + s->eecd_state.reading); | ||
271 | +} | ||
272 | + | ||
273 | +static uint32_t | ||
274 | +flash_eerd_read(E1000State *s, int x) | ||
275 | +{ | ||
276 | + unsigned int index, r = s->mac_reg[EERD] & ~E1000_EEPROM_RW_REG_START; | ||
277 | + | ||
278 | + if ((index = r >> E1000_EEPROM_RW_ADDR_SHIFT) > EEPROM_CHECKSUM_REG) | ||
279 | + return 0; | ||
280 | + return (s->eeprom_data[index] << E1000_EEPROM_RW_REG_DATA) | | ||
281 | + E1000_EEPROM_RW_REG_DONE | r; | ||
282 | +} | ||
283 | + | ||
284 | +static unsigned int | ||
285 | +do_cksum(uint8_t *dp, uint8_t *de) | ||
286 | +{ | ||
287 | + unsigned int bsum[2] = {0, 0}, i, sum; | ||
288 | + | ||
289 | + for (i = 1; dp < de; bsum[i^=1] += *dp++) | ||
290 | + ; | ||
291 | + sum = (bsum[0] << 8) + bsum[1]; | ||
292 | + sum = (sum >> 16) + (sum & 0xffff); | ||
293 | + return ~(sum + (sum >> 16)); | ||
294 | +} | ||
295 | + | ||
296 | +static void | ||
297 | +putsum(uint8_t *data, uint32_t n, uint32_t sloc, uint32_t css, uint32_t cse) | ||
298 | +{ | ||
299 | + if (cse && cse < n) | ||
300 | + n = cse + 1; | ||
301 | + if (sloc < n-1) | ||
302 | + cpu_to_be16wu((uint16_t *)(data + sloc), | ||
303 | + do_cksum(data + css, data + n)); | ||
304 | +} | ||
305 | + | ||
306 | +static void | ||
307 | +xmit_seg(E1000State *s) | ||
308 | +{ | ||
309 | + uint16_t len, *sp; | ||
310 | + unsigned int frames = s->tx.tso_frames, css, sofar, n; | ||
311 | + struct e1000_tx *tp = &s->tx; | ||
312 | + | ||
313 | + if (tp->tse) { | ||
314 | + css = tp->ipcss; | ||
315 | + DBGOUT(TXSUM, "frames %d size %d ipcss %d\n", | ||
316 | + frames, tp->size, css); | ||
317 | + if (tp->ip) { // IPv4 | ||
318 | + cpu_to_be16wu((uint16_t *)(tp->data+css+2), | ||
319 | + tp->size - css); | ||
320 | + cpu_to_be16wu((uint16_t *)(tp->data+css+4), | ||
321 | + be16_to_cpup((uint16_t *)(tp->data+css+4))+frames); | ||
322 | + } else // IPv6 | ||
323 | + cpu_to_be16wu((uint16_t *)(tp->data+css+4), | ||
324 | + tp->size - css); | ||
325 | + css = tp->tucss; | ||
326 | + len = tp->size - css; | ||
327 | + DBGOUT(TXSUM, "tcp %d tucss %d len %d\n", tp->tcp, css, len); | ||
328 | + if (tp->tcp) { | ||
329 | + sofar = frames * tp->mss; | ||
330 | + cpu_to_be32wu((uint32_t *)(tp->data+css+4), // seq | ||
331 | + be32_to_cpup((uint32_t *)(tp->data+css+4))+sofar); | ||
332 | + if (tp->paylen - sofar > tp->mss) | ||
333 | + tp->data[css + 13] &= ~9; // PSH, FIN | ||
334 | + } else // UDP | ||
335 | + cpu_to_be16wu((uint16_t *)(tp->data+css+4), len); | ||
336 | + if (tp->sum_needed & E1000_TXD_POPTS_TXSM) { | ||
337 | + // add pseudo-header length before checksum calculation | ||
338 | + sp = (uint16_t *)(tp->data + tp->tucso); | ||
339 | + cpu_to_be16wu(sp, be16_to_cpup(sp) + len); | ||
340 | + } | ||
341 | + tp->tso_frames++; | ||
342 | + } | ||
343 | + | ||
344 | + if (tp->sum_needed & E1000_TXD_POPTS_TXSM) | ||
345 | + putsum(tp->data, tp->size, tp->tucso, tp->tucss, tp->tucse); | ||
346 | + if (tp->sum_needed & E1000_TXD_POPTS_IXSM) | ||
347 | + putsum(tp->data, tp->size, tp->ipcso, tp->ipcss, tp->ipcse); | ||
348 | + qemu_send_packet(s->vc, tp->data, tp->size); | ||
349 | + s->mac_reg[TPT]++; | ||
350 | + s->mac_reg[GPTC]++; | ||
351 | + n = s->mac_reg[TOTL]; | ||
352 | + if ((s->mac_reg[TOTL] += s->tx.size) < n) | ||
353 | + s->mac_reg[TOTH]++; | ||
354 | +} | ||
355 | + | ||
356 | +static void | ||
357 | +process_tx_desc(E1000State *s, struct e1000_tx_desc *dp) | ||
358 | +{ | ||
359 | + uint32_t txd_lower = le32_to_cpu(dp->lower.data); | ||
360 | + uint32_t dtype = txd_lower & (E1000_TXD_CMD_DEXT | E1000_TXD_DTYP_D); | ||
361 | + unsigned int split_size = txd_lower & 0xffff, bytes, sz, op; | ||
362 | + unsigned int msh = 0xfffff, hdr = 0; | ||
363 | + uint64_t addr; | ||
364 | + struct e1000_context_desc *xp = (struct e1000_context_desc *)dp; | ||
365 | + struct e1000_tx *tp = &s->tx; | ||
366 | + | ||
367 | + if (dtype == E1000_TXD_CMD_DEXT) { // context descriptor | ||
368 | + op = le32_to_cpu(xp->cmd_and_length); | ||
369 | + tp->ipcss = xp->lower_setup.ip_fields.ipcss; | ||
370 | + tp->ipcso = xp->lower_setup.ip_fields.ipcso; | ||
371 | + tp->ipcse = le16_to_cpu(xp->lower_setup.ip_fields.ipcse); | ||
372 | + tp->tucss = xp->upper_setup.tcp_fields.tucss; | ||
373 | + tp->tucso = xp->upper_setup.tcp_fields.tucso; | ||
374 | + tp->tucse = le16_to_cpu(xp->upper_setup.tcp_fields.tucse); | ||
375 | + tp->paylen = op & 0xfffff; | ||
376 | + tp->hdr_len = xp->tcp_seg_setup.fields.hdr_len; | ||
377 | + tp->mss = le16_to_cpu(xp->tcp_seg_setup.fields.mss); | ||
378 | + tp->ip = (op & E1000_TXD_CMD_IP) ? 1 : 0; | ||
379 | + tp->tcp = (op & E1000_TXD_CMD_TCP) ? 1 : 0; | ||
380 | + tp->tse = (op & E1000_TXD_CMD_TSE) ? 1 : 0; | ||
381 | + tp->tso_frames = 0; | ||
382 | + if (tp->tucso == 0) { // this is probably wrong | ||
383 | + DBGOUT(TXSUM, "TCP/UDP: cso 0!\n"); | ||
384 | + tp->tucso = tp->tucss + (tp->tcp ? 16 : 6); | ||
385 | + } | ||
386 | + return; | ||
387 | + } else if (dtype == (E1000_TXD_CMD_DEXT | E1000_TXD_DTYP_D)) | ||
388 | + tp->sum_needed = le32_to_cpu(dp->upper.data) >> 8; | ||
389 | + | ||
390 | + addr = le64_to_cpu(dp->buffer_addr); | ||
391 | + if (tp->tse) { | ||
392 | + hdr = tp->hdr_len; | ||
393 | + msh = hdr + tp->mss; | ||
394 | + } | ||
395 | + do { | ||
396 | + bytes = split_size; | ||
397 | + if (tp->size + bytes > msh) | ||
398 | + bytes = msh - tp->size; | ||
399 | + cpu_physical_memory_read(addr, tp->data + tp->size, bytes); | ||
400 | + if ((sz = tp->size + bytes) >= hdr && tp->size < hdr) | ||
401 | + memmove(tp->header, tp->data, hdr); | ||
402 | + tp->size = sz; | ||
403 | + addr += bytes; | ||
404 | + if (sz == msh) { | ||
405 | + xmit_seg(s); | ||
406 | + memmove(tp->data, tp->header, hdr); | ||
407 | + tp->size = hdr; | ||
408 | + } | ||
409 | + } while (split_size -= bytes); | ||
410 | + | ||
411 | + if (!(txd_lower & E1000_TXD_CMD_EOP)) | ||
412 | + return; | ||
413 | + if (tp->size > hdr) | ||
414 | + xmit_seg(s); | ||
415 | + tp->tso_frames = 0; | ||
416 | + tp->sum_needed = 0; | ||
417 | + tp->size = 0; | ||
418 | +} | ||
419 | + | ||
420 | +static uint32_t | ||
421 | +txdesc_writeback(target_phys_addr_t base, struct e1000_tx_desc *dp) | ||
422 | +{ | ||
423 | + uint32_t txd_upper, txd_lower = le32_to_cpu(dp->lower.data); | ||
424 | + | ||
425 | + if (!(txd_lower & (E1000_TXD_CMD_RS|E1000_TXD_CMD_RPS))) | ||
426 | + return 0; | ||
427 | + txd_upper = (le32_to_cpu(dp->upper.data) | E1000_TXD_STAT_DD) & | ||
428 | + ~(E1000_TXD_STAT_EC | E1000_TXD_STAT_LC | E1000_TXD_STAT_TU); | ||
429 | + dp->upper.data = cpu_to_le32(txd_upper); | ||
430 | + cpu_physical_memory_write(base + ((char *)&dp->upper - (char *)dp), | ||
431 | + (void *)&dp->upper, sizeof(dp->upper)); | ||
432 | + return E1000_ICR_TXDW; | ||
433 | +} | ||
434 | + | ||
435 | +static void | ||
436 | +start_xmit(E1000State *s) | ||
437 | +{ | ||
438 | + target_phys_addr_t base; | ||
439 | + struct e1000_tx_desc desc; | ||
440 | + uint32_t tdh_start = s->mac_reg[TDH], cause = E1000_ICS_TXQE; | ||
441 | + | ||
442 | + if (!(s->mac_reg[TCTL] & E1000_TCTL_EN)) { | ||
443 | + DBGOUT(TX, "tx disabled\n"); | ||
444 | + return; | ||
445 | + } | ||
446 | + | ||
447 | + while (s->mac_reg[TDH] != s->mac_reg[TDT]) { | ||
448 | + base = ((uint64_t)s->mac_reg[TDBAH] << 32) + s->mac_reg[TDBAL] + | ||
449 | + sizeof(struct e1000_tx_desc) * s->mac_reg[TDH]; | ||
450 | + cpu_physical_memory_read(base, (void *)&desc, sizeof(desc)); | ||
451 | + | ||
452 | + DBGOUT(TX, "index %d: %p : %x %x\n", s->mac_reg[TDH], | ||
453 | + (void *)desc.buffer_addr, desc.lower.data, | ||
454 | + desc.upper.data); | ||
455 | + | ||
456 | + process_tx_desc(s, &desc); | ||
457 | + cause |= txdesc_writeback(base, &desc); | ||
458 | + | ||
459 | + if (++s->mac_reg[TDH] * sizeof(desc) >= s->mac_reg[TDLEN]) | ||
460 | + s->mac_reg[TDH] = 0; | ||
461 | + /* | ||
462 | + * the following could happen only if guest sw assigns | ||
463 | + * bogus values to TDT/TDLEN. | ||
464 | + * there's nothing too intelligent we could do about this. | ||
465 | + */ | ||
466 | + if (s->mac_reg[TDH] == tdh_start) { | ||
467 | + DBGOUT(TXERR, "TDH wraparound @%x, TDT %x, TDLEN %x\n", | ||
468 | + tdh_start, s->mac_reg[TDT], s->mac_reg[TDLEN]); | ||
469 | + break; | ||
470 | + } | ||
471 | + } | ||
472 | + set_ics(s, 0, cause); | ||
473 | +} | ||
474 | + | ||
475 | +static int | ||
476 | +receive_filter(E1000State *s, const uint8_t *buf, int size) | ||
477 | +{ | ||
478 | + static uint8_t bcast[] = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff}; | ||
479 | + static int mta_shift[] = {4, 3, 2, 0}; | ||
480 | + uint32_t f, rctl = s->mac_reg[RCTL], ra[2], *rp; | ||
481 | + | ||
482 | + if (rctl & E1000_RCTL_UPE) // promiscuous | ||
483 | + return 1; | ||
484 | + | ||
485 | + if ((buf[0] & 1) && (rctl & E1000_RCTL_MPE)) // promiscuous mcast | ||
486 | + return 1; | ||
487 | + | ||
488 | + if ((rctl & E1000_RCTL_BAM) && !memcmp(buf, bcast, sizeof bcast)) | ||
489 | + return 1; | ||
490 | + | ||
491 | + for (rp = s->mac_reg + RA; rp < s->mac_reg + RA + 32; rp += 2) { | ||
492 | + if (!(rp[1] & E1000_RAH_AV)) | ||
493 | + continue; | ||
494 | + ra[0] = cpu_to_le32(rp[0]); | ||
495 | + ra[1] = cpu_to_le32(rp[1]); | ||
496 | + if (!memcmp(buf, (uint8_t *)ra, 6)) { | ||
497 | + DBGOUT(RXFILTER, | ||
498 | + "unicast match[%d]: %02x:%02x:%02x:%02x:%02x:%02x\n", | ||
499 | + (int)(rp - s->mac_reg - RA)/2, | ||
500 | + buf[0], buf[1], buf[2], buf[3], buf[4], buf[5]); | ||
501 | + return 1; | ||
502 | + } | ||
503 | + } | ||
504 | + DBGOUT(RXFILTER, "unicast mismatch: %02x:%02x:%02x:%02x:%02x:%02x\n", | ||
505 | + buf[0], buf[1], buf[2], buf[3], buf[4], buf[5]); | ||
506 | + | ||
507 | + f = mta_shift[(rctl >> E1000_RCTL_MO_SHIFT) & 3]; | ||
508 | + f = (((buf[5] << 8) | buf[4]) >> f) & 0xfff; | ||
509 | + if (s->mac_reg[MTA + (f >> 5)] & (1 << (f & 0x1f))) | ||
510 | + return 1; | ||
511 | + DBGOUT(RXFILTER, | ||
512 | + "dropping, inexact filter mismatch: %02x:%02x:%02x:%02x:%02x:%02x MO %d MTA[%d] %x\n", | ||
513 | + buf[0], buf[1], buf[2], buf[3], buf[4], buf[5], | ||
514 | + (rctl >> E1000_RCTL_MO_SHIFT) & 3, f >> 5, | ||
515 | + s->mac_reg[MTA + (f >> 5)]); | ||
516 | + | ||
517 | + return 0; | ||
518 | +} | ||
519 | + | ||
520 | +static int | ||
521 | +e1000_can_receive(void *opaque) | ||
522 | +{ | ||
523 | + E1000State *s = opaque; | ||
524 | + | ||
525 | + return (!(s->mac_reg[RCTL] & E1000_RCTL_EN) || | ||
526 | + s->mac_reg[RDH] != s->mac_reg[RDT]); | ||
527 | +} | ||
528 | + | ||
529 | +static void | ||
530 | +e1000_receive(void *opaque, const uint8_t *buf, int size) | ||
531 | +{ | ||
532 | + E1000State *s = opaque; | ||
533 | + struct e1000_rx_desc desc; | ||
534 | + target_phys_addr_t base; | ||
535 | + unsigned int n, rdt; | ||
536 | + uint32_t rdh_start; | ||
537 | + | ||
538 | + if (!(s->mac_reg[RCTL] & E1000_RCTL_EN)) | ||
539 | + return; | ||
540 | + | ||
541 | + if (size > s->rxbuf_size) { | ||
542 | + DBGOUT(RX, "packet too large for buffers (%d > %d)\n", size, | ||
543 | + s->rxbuf_size); | ||
544 | + return; | ||
545 | + } | ||
546 | + | ||
547 | + if (!receive_filter(s, buf, size)) | ||
548 | + return; | ||
549 | + | ||
550 | + rdh_start = s->mac_reg[RDH]; | ||
551 | + size += 4; // for the header | ||
552 | + do { | ||
553 | + if (s->mac_reg[RDH] == s->mac_reg[RDT] && s->check_rxov) { | ||
554 | + set_ics(s, 0, E1000_ICS_RXO); | ||
555 | + return; | ||
556 | + } | ||
557 | + base = ((uint64_t)s->mac_reg[RDBAH] << 32) + s->mac_reg[RDBAL] + | ||
558 | + sizeof(desc) * s->mac_reg[RDH]; | ||
559 | + cpu_physical_memory_read(base, (void *)&desc, sizeof(desc)); | ||
560 | + desc.status |= E1000_RXD_STAT_DD; | ||
561 | + if (desc.buffer_addr) { | ||
562 | + cpu_physical_memory_write(le64_to_cpu(desc.buffer_addr), | ||
563 | + (void *)buf, size); | ||
564 | + desc.length = cpu_to_le16(size); | ||
565 | + desc.status |= E1000_RXD_STAT_EOP|E1000_RXD_STAT_IXSM; | ||
566 | + } else // as per intel docs; skip descriptors with null buf addr | ||
567 | + DBGOUT(RX, "Null RX descriptor!!\n"); | ||
568 | + cpu_physical_memory_write(base, (void *)&desc, sizeof(desc)); | ||
569 | + | ||
570 | + if (++s->mac_reg[RDH] * sizeof(desc) >= s->mac_reg[RDLEN]) | ||
571 | + s->mac_reg[RDH] = 0; | ||
572 | + s->check_rxov = 1; | ||
573 | + /* see comment in start_xmit; same here */ | ||
574 | + if (s->mac_reg[RDH] == rdh_start) { | ||
575 | + DBGOUT(RXERR, "RDH wraparound @%x, RDT %x, RDLEN %x\n", | ||
576 | + rdh_start, s->mac_reg[RDT], s->mac_reg[RDLEN]); | ||
577 | + set_ics(s, 0, E1000_ICS_RXO); | ||
578 | + return; | ||
579 | + } | ||
580 | + } while (desc.buffer_addr == 0); | ||
581 | + | ||
582 | + s->mac_reg[GPRC]++; | ||
583 | + s->mac_reg[TPR]++; | ||
584 | + n = s->mac_reg[TORL]; | ||
585 | + if ((s->mac_reg[TORL] += size) < n) | ||
586 | + s->mac_reg[TORH]++; | ||
587 | + | ||
588 | + n = E1000_ICS_RXT0; | ||
589 | + if ((rdt = s->mac_reg[RDT]) < s->mac_reg[RDH]) | ||
590 | + rdt += s->mac_reg[RDLEN] / sizeof(desc); | ||
591 | + if (((rdt - s->mac_reg[RDH]) * sizeof(desc)) << s->rxbuf_min_shift >= | ||
592 | + s->mac_reg[RDLEN]) | ||
593 | + n |= E1000_ICS_RXDMT0; | ||
594 | + | ||
595 | + set_ics(s, 0, n); | ||
596 | +} | ||
597 | + | ||
598 | +static uint32_t | ||
599 | +mac_readreg(E1000State *s, int index) | ||
600 | +{ | ||
601 | + return s->mac_reg[index]; | ||
602 | +} | ||
603 | + | ||
604 | +static uint32_t | ||
605 | +mac_icr_read(E1000State *s, int index) | ||
606 | +{ | ||
607 | + uint32_t ret = s->mac_reg[ICR]; | ||
608 | + | ||
609 | + DBGOUT(INTERRUPT, "ICR read: %x\n", ret); | ||
610 | + set_interrupt_cause(s, 0, 0); | ||
611 | + return ret; | ||
612 | +} | ||
613 | + | ||
614 | +static uint32_t | ||
615 | +mac_read_clr4(E1000State *s, int index) | ||
616 | +{ | ||
617 | + uint32_t ret = s->mac_reg[index]; | ||
618 | + | ||
619 | + s->mac_reg[index] = 0; | ||
620 | + return ret; | ||
621 | +} | ||
622 | + | ||
623 | +static uint32_t | ||
624 | +mac_read_clr8(E1000State *s, int index) | ||
625 | +{ | ||
626 | + uint32_t ret = s->mac_reg[index]; | ||
627 | + | ||
628 | + s->mac_reg[index] = 0; | ||
629 | + s->mac_reg[index-1] = 0; | ||
630 | + return ret; | ||
631 | +} | ||
632 | + | ||
633 | +static void | ||
634 | +mac_writereg(E1000State *s, int index, uint32_t val) | ||
635 | +{ | ||
636 | + s->mac_reg[index] = val; | ||
637 | +} | ||
638 | + | ||
639 | +static void | ||
640 | +set_rdt(E1000State *s, int index, uint32_t val) | ||
641 | +{ | ||
642 | + s->check_rxov = 0; | ||
643 | + s->mac_reg[index] = val & 0xffff; | ||
644 | +} | ||
645 | + | ||
646 | +static void | ||
647 | +set_16bit(E1000State *s, int index, uint32_t val) | ||
648 | +{ | ||
649 | + s->mac_reg[index] = val & 0xffff; | ||
650 | +} | ||
651 | + | ||
652 | +static void | ||
653 | +set_dlen(E1000State *s, int index, uint32_t val) | ||
654 | +{ | ||
655 | + s->mac_reg[index] = val & 0xfff80; | ||
656 | +} | ||
657 | + | ||
658 | +static void | ||
659 | +set_tctl(E1000State *s, int index, uint32_t val) | ||
660 | +{ | ||
661 | + s->mac_reg[index] = val; | ||
662 | + s->mac_reg[TDT] &= 0xffff; | ||
663 | + start_xmit(s); | ||
664 | +} | ||
665 | + | ||
666 | +static void | ||
667 | +set_icr(E1000State *s, int index, uint32_t val) | ||
668 | +{ | ||
669 | + DBGOUT(INTERRUPT, "set_icr %x\n", val); | ||
670 | + set_interrupt_cause(s, 0, s->mac_reg[ICR] & ~val); | ||
671 | +} | ||
672 | + | ||
673 | +static void | ||
674 | +set_imc(E1000State *s, int index, uint32_t val) | ||
675 | +{ | ||
676 | + s->mac_reg[IMS] &= ~val; | ||
677 | + set_ics(s, 0, 0); | ||
678 | +} | ||
679 | + | ||
680 | +static void | ||
681 | +set_ims(E1000State *s, int index, uint32_t val) | ||
682 | +{ | ||
683 | + s->mac_reg[IMS] |= val; | ||
684 | + set_ics(s, 0, 0); | ||
685 | +} | ||
686 | + | ||
687 | +#define getreg(x) [x] = mac_readreg | ||
688 | +static uint32_t (*macreg_readops[])(E1000State *, int) = { | ||
689 | + getreg(PBA), getreg(RCTL), getreg(TDH), getreg(TXDCTL), | ||
690 | + getreg(WUFC), getreg(TDT), getreg(CTRL), getreg(LEDCTL), | ||
691 | + getreg(MANC), getreg(MDIC), getreg(SWSM), getreg(STATUS), | ||
692 | + getreg(TORL), getreg(TOTL), getreg(IMS), getreg(TCTL), | ||
693 | + getreg(RDH), getreg(RDT), | ||
694 | + | ||
695 | + [TOTH] = mac_read_clr8, [TORH] = mac_read_clr8, [GPRC] = mac_read_clr4, | ||
696 | + [GPTC] = mac_read_clr4, [TPR] = mac_read_clr4, [TPT] = mac_read_clr4, | ||
697 | + [ICR] = mac_icr_read, [EECD] = get_eecd, [EERD] = flash_eerd_read, | ||
698 | + [CRCERRS ... MPC] = &mac_readreg, | ||
699 | + [RA ... RA+31] = &mac_readreg, | ||
700 | + [MTA ... MTA+127] = &mac_readreg, | ||
701 | +}; | ||
702 | +enum { NREADOPS = sizeof(macreg_readops) / sizeof(*macreg_readops) }; | ||
703 | + | ||
704 | +#define putreg(x) [x] = mac_writereg | ||
705 | +static void (*macreg_writeops[])(E1000State *, int, uint32_t) = { | ||
706 | + putreg(PBA), putreg(EERD), putreg(SWSM), putreg(WUFC), | ||
707 | + putreg(TDBAL), putreg(TDBAH), putreg(TXDCTL), putreg(RDBAH), | ||
708 | + putreg(RDBAL), putreg(LEDCTL), | ||
709 | + [TDLEN] = set_dlen, [RDLEN] = set_dlen, [TCTL] = set_tctl, | ||
710 | + [TDT] = set_tctl, [MDIC] = set_mdic, [ICS] = set_ics, | ||
711 | + [TDH] = set_16bit, [RDH] = set_16bit, [RDT] = set_rdt, | ||
712 | + [IMC] = set_imc, [IMS] = set_ims, [ICR] = set_icr, | ||
713 | + [EECD] = set_eecd, [RCTL] = set_rx_control, | ||
714 | + [RA ... RA+31] = &mac_writereg, | ||
715 | + [MTA ... MTA+127] = &mac_writereg, | ||
716 | +}; | ||
717 | +enum { NWRITEOPS = sizeof(macreg_writeops) / sizeof(*macreg_writeops) }; | ||
718 | + | ||
719 | +static void | ||
720 | +e1000_mmio_writel(void *opaque, target_phys_addr_t addr, uint32_t val) | ||
721 | +{ | ||
722 | + E1000State *s = opaque; | ||
723 | + unsigned int index = ((addr - s->mmio_base) & 0x1ffff) >> 2; | ||
724 | + | ||
725 | + if (index < NWRITEOPS && macreg_writeops[index]) | ||
726 | + macreg_writeops[index](s, index, le32_to_cpu(val)); | ||
727 | + else if (index < NREADOPS && macreg_readops[index]) | ||
728 | + DBGOUT(MMIO, "e1000_mmio_writel RO %x: 0x%04x\n", index<<2, val); | ||
729 | + else | ||
730 | + DBGOUT(UNKNOWN, "MMIO unknown write addr=0x%08x,val=0x%08x\n", | ||
731 | + index<<2, val); | ||
732 | +} | ||
733 | + | ||
734 | +static void | ||
735 | +e1000_mmio_writew(void *opaque, target_phys_addr_t addr, uint32_t val) | ||
736 | +{ | ||
737 | + // emulate hw without byte enables: no RMW | ||
738 | + e1000_mmio_writel(opaque, addr & ~3, | ||
739 | + cpu_to_le32(le16_to_cpu(val & 0xffff) << (8*(addr & 3)))); | ||
740 | +} | ||
741 | + | ||
742 | +static void | ||
743 | +e1000_mmio_writeb(void *opaque, target_phys_addr_t addr, uint32_t val) | ||
744 | +{ | ||
745 | + // emulate hw without byte enables: no RMW | ||
746 | + e1000_mmio_writel(opaque, addr & ~3, | ||
747 | + cpu_to_le32((val & 0xff) << (8*(addr & 3)))); | ||
748 | +} | ||
749 | + | ||
750 | +static uint32_t | ||
751 | +e1000_mmio_readl(void *opaque, target_phys_addr_t addr) | ||
752 | +{ | ||
753 | + E1000State *s = opaque; | ||
754 | + unsigned int index = ((addr - s->mmio_base) & 0x1ffff) >> 2; | ||
755 | + | ||
756 | + if (index < NREADOPS && macreg_readops[index]) | ||
757 | + return cpu_to_le32(macreg_readops[index](s, index)); | ||
758 | + DBGOUT(UNKNOWN, "MMIO unknown read addr=0x%08x\n", index<<2); | ||
759 | + return 0; | ||
760 | +} | ||
761 | + | ||
762 | +static uint32_t | ||
763 | +e1000_mmio_readb(void *opaque, target_phys_addr_t addr) | ||
764 | +{ | ||
765 | + return (le32_to_cpu(e1000_mmio_readl(opaque, addr & ~3)) >> | ||
766 | + (8 * (addr & 3))) & 0xff; | ||
767 | +} | ||
768 | + | ||
769 | +static uint32_t | ||
770 | +e1000_mmio_readw(void *opaque, target_phys_addr_t addr) | ||
771 | +{ | ||
772 | + return cpu_to_le16((le32_to_cpu(e1000_mmio_readl(opaque, addr & ~3)) >> | ||
773 | + (8 * (addr & 3))) & 0xffff); | ||
774 | +} | ||
775 | + | ||
776 | +int mac_regtosave[] = { | ||
777 | + CTRL, EECD, EERD, GPRC, GPTC, ICR, ICS, IMC, IMS, | ||
778 | + LEDCTL, MANC, MDIC, MPC, PBA, RCTL, RDBAH, RDBAL, RDH, | ||
779 | + RDLEN, RDT, STATUS, SWSM, TCTL, TDBAH, TDBAL, TDH, TDLEN, | ||
780 | + TDT, TORH, TORL, TOTH, TOTL, TPR, TPT, TXDCTL, WUFC, | ||
781 | +}; | ||
782 | +enum { MAC_NSAVE = sizeof mac_regtosave/sizeof *mac_regtosave }; | ||
783 | + | ||
784 | +struct { | ||
785 | + int size; | ||
786 | + int array0; | ||
787 | +} mac_regarraystosave[] = { {32, RA}, {128, MTA} }; | ||
788 | +enum { MAC_NARRAYS = sizeof mac_regarraystosave/sizeof *mac_regarraystosave }; | ||
789 | + | ||
790 | +static void | ||
791 | +nic_save(QEMUFile *f, void *opaque) | ||
792 | +{ | ||
793 | + E1000State *s = (E1000State *)opaque; | ||
794 | + int i, j; | ||
795 | + | ||
796 | + pci_device_save(&s->dev, f); | ||
797 | + qemu_put_be32s(f, &s->instance); | ||
798 | + qemu_put_be32s(f, &s->mmio_base); | ||
799 | + qemu_put_be32s(f, &s->rxbuf_size); | ||
800 | + qemu_put_be32s(f, &s->rxbuf_min_shift); | ||
801 | + qemu_put_be32s(f, &s->eecd_state.val_in); | ||
802 | + qemu_put_be16s(f, &s->eecd_state.bitnum_in); | ||
803 | + qemu_put_be16s(f, &s->eecd_state.bitnum_out); | ||
804 | + qemu_put_be16s(f, &s->eecd_state.reading); | ||
805 | + qemu_put_be32s(f, &s->eecd_state.old_eecd); | ||
806 | + qemu_put_8s(f, &s->tx.ipcss); | ||
807 | + qemu_put_8s(f, &s->tx.ipcso); | ||
808 | + qemu_put_be16s(f, &s->tx.ipcse); | ||
809 | + qemu_put_8s(f, &s->tx.tucss); | ||
810 | + qemu_put_8s(f, &s->tx.tucso); | ||
811 | + qemu_put_be16s(f, &s->tx.tucse); | ||
812 | + qemu_put_be32s(f, &s->tx.paylen); | ||
813 | + qemu_put_8s(f, &s->tx.hdr_len); | ||
814 | + qemu_put_be16s(f, &s->tx.mss); | ||
815 | + qemu_put_be16s(f, &s->tx.size); | ||
816 | + qemu_put_be16s(f, &s->tx.tso_frames); | ||
817 | + qemu_put_8s(f, &s->tx.sum_needed); | ||
818 | + qemu_put_8s(f, &s->tx.ip); | ||
819 | + qemu_put_8s(f, &s->tx.tcp); | ||
820 | + qemu_put_buffer(f, s->tx.header, sizeof s->tx.header); | ||
821 | + qemu_put_buffer(f, s->tx.data, sizeof s->tx.data); | ||
822 | + for (i = 0; i < 64; i++) | ||
823 | + qemu_put_be16s(f, s->eeprom_data + i); | ||
824 | + for (i = 0; i < 0x20; i++) | ||
825 | + qemu_put_be16s(f, s->phy_reg + i); | ||
826 | + for (i = 0; i < MAC_NSAVE; i++) | ||
827 | + qemu_put_be32s(f, s->mac_reg + mac_regtosave[i]); | ||
828 | + for (i = 0; i < MAC_NARRAYS; i++) | ||
829 | + for (j = 0; j < mac_regarraystosave[i].size; j++) | ||
830 | + qemu_put_be32s(f, | ||
831 | + s->mac_reg + mac_regarraystosave[i].array0 + j); | ||
832 | +} | ||
833 | + | ||
834 | +static int | ||
835 | +nic_load(QEMUFile *f, void *opaque, int version_id) | ||
836 | +{ | ||
837 | + E1000State *s = (E1000State *)opaque; | ||
838 | + int i, j, ret; | ||
839 | + | ||
840 | + if ((ret = pci_device_load(&s->dev, f)) < 0) | ||
841 | + return ret; | ||
842 | + qemu_get_be32s(f, &s->instance); | ||
843 | + qemu_get_be32s(f, &s->mmio_base); | ||
844 | + qemu_get_be32s(f, &s->rxbuf_size); | ||
845 | + qemu_get_be32s(f, &s->rxbuf_min_shift); | ||
846 | + qemu_get_be32s(f, &s->eecd_state.val_in); | ||
847 | + qemu_get_be16s(f, &s->eecd_state.bitnum_in); | ||
848 | + qemu_get_be16s(f, &s->eecd_state.bitnum_out); | ||
849 | + qemu_get_be16s(f, &s->eecd_state.reading); | ||
850 | + qemu_get_be32s(f, &s->eecd_state.old_eecd); | ||
851 | + qemu_get_8s(f, &s->tx.ipcss); | ||
852 | + qemu_get_8s(f, &s->tx.ipcso); | ||
853 | + qemu_get_be16s(f, &s->tx.ipcse); | ||
854 | + qemu_get_8s(f, &s->tx.tucss); | ||
855 | + qemu_get_8s(f, &s->tx.tucso); | ||
856 | + qemu_get_be16s(f, &s->tx.tucse); | ||
857 | + qemu_get_be32s(f, &s->tx.paylen); | ||
858 | + qemu_get_8s(f, &s->tx.hdr_len); | ||
859 | + qemu_get_be16s(f, &s->tx.mss); | ||
860 | + qemu_get_be16s(f, &s->tx.size); | ||
861 | + qemu_get_be16s(f, &s->tx.tso_frames); | ||
862 | + qemu_get_8s(f, &s->tx.sum_needed); | ||
863 | + qemu_get_8s(f, &s->tx.ip); | ||
864 | + qemu_get_8s(f, &s->tx.tcp); | ||
865 | + qemu_get_buffer(f, s->tx.header, sizeof s->tx.header); | ||
866 | + qemu_get_buffer(f, s->tx.data, sizeof s->tx.data); | ||
867 | + for (i = 0; i < 64; i++) | ||
868 | + qemu_get_be16s(f, s->eeprom_data + i); | ||
869 | + for (i = 0; i < 0x20; i++) | ||
870 | + qemu_get_be16s(f, s->phy_reg + i); | ||
871 | + for (i = 0; i < MAC_NSAVE; i++) | ||
872 | + qemu_get_be32s(f, s->mac_reg + mac_regtosave[i]); | ||
873 | + for (i = 0; i < MAC_NARRAYS; i++) | ||
874 | + for (j = 0; j < mac_regarraystosave[i].size; j++) | ||
875 | + qemu_get_be32s(f, | ||
876 | + s->mac_reg + mac_regarraystosave[i].array0 + j); | ||
877 | + return 0; | ||
878 | +} | ||
879 | + | ||
880 | +static uint16_t e1000_eeprom_template[64] = { | ||
881 | + 0x0000, 0x0000, 0x0000, 0x0000, 0xffff, 0x0000, 0x0000, 0x0000, | ||
882 | + 0x3000, 0x1000, 0x6403, E1000_DEVID, 0x8086, E1000_DEVID, 0x8086, 0x3040, | ||
883 | + 0x0008, 0x2000, 0x7e14, 0x0048, 0x1000, 0x00d8, 0x0000, 0x2700, | ||
884 | + 0x6cc9, 0x3150, 0x0722, 0x040b, 0x0984, 0x0000, 0xc000, 0x0706, | ||
885 | + 0x1008, 0x0000, 0x0f04, 0x7fff, 0x4d01, 0xffff, 0xffff, 0xffff, | ||
886 | + 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, | ||
887 | + 0x0100, 0x4000, 0x121c, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, | ||
888 | + 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0x0000, | ||
889 | +}; | ||
890 | + | ||
891 | +static uint16_t phy_reg_init[] = { | ||
892 | + [PHY_CTRL] = 0x1140, [PHY_STATUS] = 0x796d, // link initially up | ||
893 | + [PHY_ID1] = 0x141, [PHY_ID2] = PHY_ID2_INIT, | ||
894 | + [PHY_1000T_CTRL] = 0x0e00, [M88E1000_PHY_SPEC_CTRL] = 0x360, | ||
895 | + [M88E1000_EXT_PHY_SPEC_CTRL] = 0x0d60, [PHY_AUTONEG_ADV] = 0xde1, | ||
896 | + [PHY_LP_ABILITY] = 0x1e0, [PHY_1000T_STATUS] = 0x3c00, | ||
897 | +}; | ||
898 | + | ||
899 | +static uint32_t mac_reg_init[] = { | ||
900 | + [PBA] = 0x00100030, | ||
901 | + [LEDCTL] = 0x602, | ||
902 | + [CTRL] = E1000_CTRL_SWDPIN2 | E1000_CTRL_SWDPIN0 | | ||
903 | + E1000_CTRL_SPD_1000 | E1000_CTRL_SLU, | ||
904 | + [STATUS] = 0x80000000 | E1000_STATUS_GIO_MASTER_ENABLE | | ||
905 | + E1000_STATUS_ASDV | E1000_STATUS_MTXCKOK | | ||
906 | + E1000_STATUS_SPEED_1000 | E1000_STATUS_FD | | ||
907 | + E1000_STATUS_LU, | ||
908 | + [MANC] = E1000_MANC_EN_MNG2HOST | E1000_MANC_RCV_TCO_EN | | ||
909 | + E1000_MANC_ARP_EN | E1000_MANC_0298_EN | | ||
910 | + E1000_MANC_RMCP_EN, | ||
911 | +}; | ||
912 | + | ||
913 | +/* PCI interface */ | ||
914 | + | ||
915 | +static CPUWriteMemoryFunc *e1000_mmio_write[] = { | ||
916 | + e1000_mmio_writeb, e1000_mmio_writew, e1000_mmio_writel | ||
917 | +}; | ||
918 | + | ||
919 | +static CPUReadMemoryFunc *e1000_mmio_read[] = { | ||
920 | + e1000_mmio_readb, e1000_mmio_readw, e1000_mmio_readl | ||
921 | +}; | ||
922 | + | ||
923 | +static void | ||
924 | +e1000_mmio_map(PCIDevice *pci_dev, int region_num, | ||
925 | + uint32_t addr, uint32_t size, int type) | ||
926 | +{ | ||
927 | + E1000State *d = (E1000State *)pci_dev; | ||
928 | + | ||
929 | + DBGOUT(MMIO, "e1000_mmio_map addr=0x%08x 0x%08x\n", addr, size); | ||
930 | + | ||
931 | + d->mmio_base = addr; | ||
932 | + cpu_register_physical_memory(addr, PNPMMIO_SIZE, d->mmio_index); | ||
933 | +} | ||
934 | + | ||
935 | +void | ||
936 | +pci_e1000_init(PCIBus *bus, NICInfo *nd, int devfn) | ||
937 | +{ | ||
938 | + E1000State *d; | ||
939 | + uint8_t *pci_conf; | ||
940 | + static int instance; | ||
941 | + uint16_t checksum = 0; | ||
942 | + char *info_str = "e1000"; | ||
943 | + int i; | ||
944 | + | ||
945 | + d = (E1000State *)pci_register_device(bus, "e1000", | ||
946 | + sizeof(E1000State), devfn, NULL, NULL); | ||
947 | + | ||
948 | + pci_conf = d->dev.config; | ||
949 | + memset(pci_conf, 0, 256); | ||
950 | + | ||
951 | + *(uint16_t *)(pci_conf+0x00) = cpu_to_le16(0x8086); | ||
952 | + *(uint16_t *)(pci_conf+0x02) = cpu_to_le16(E1000_DEVID); | ||
953 | + *(uint16_t *)(pci_conf+0x04) = cpu_to_le16(0x0407); | ||
954 | + *(uint16_t *)(pci_conf+0x06) = cpu_to_le16(0x0010); | ||
955 | + pci_conf[0x08] = 0x03; | ||
956 | + pci_conf[0x0a] = 0x00; // ethernet network controller | ||
957 | + pci_conf[0x0b] = 0x02; | ||
958 | + pci_conf[0x0c] = 0x10; | ||
959 | + | ||
960 | + pci_conf[0x3d] = 1; // interrupt pin 0 | ||
961 | + | ||
962 | + d->mmio_index = cpu_register_io_memory(0, e1000_mmio_read, | ||
963 | + e1000_mmio_write, d); | ||
964 | + | ||
965 | + pci_register_io_region((PCIDevice *)d, 0, PNPMMIO_SIZE, | ||
966 | + PCI_ADDRESS_SPACE_MEM, e1000_mmio_map); | ||
967 | + | ||
968 | + pci_register_io_region((PCIDevice *)d, 1, IOPORT_SIZE, | ||
969 | + PCI_ADDRESS_SPACE_IO, ioport_map); | ||
970 | + | ||
971 | + d->instance = instance++; | ||
972 | + | ||
973 | + d->nd = nd; | ||
974 | + memmove(d->eeprom_data, e1000_eeprom_template, | ||
975 | + sizeof e1000_eeprom_template); | ||
976 | + for (i = 0; i < 3; i++) | ||
977 | + d->eeprom_data[i] = (nd->macaddr[2*i+1]<<8) | nd->macaddr[2*i]; | ||
978 | + for (i = 0; i < EEPROM_CHECKSUM_REG; i++) | ||
979 | + checksum += d->eeprom_data[i]; | ||
980 | + checksum = (uint16_t) EEPROM_SUM - checksum; | ||
981 | + d->eeprom_data[EEPROM_CHECKSUM_REG] = checksum; | ||
982 | + | ||
983 | + memset(d->phy_reg, 0, sizeof d->phy_reg); | ||
984 | + memmove(d->phy_reg, phy_reg_init, sizeof phy_reg_init); | ||
985 | + memset(d->mac_reg, 0, sizeof d->mac_reg); | ||
986 | + memmove(d->mac_reg, mac_reg_init, sizeof mac_reg_init); | ||
987 | + d->rxbuf_min_shift = 1; | ||
988 | + memset(&d->tx, 0, sizeof d->tx); | ||
989 | + | ||
990 | + d->vc = qemu_new_vlan_client(nd->vlan, e1000_receive, | ||
991 | + e1000_can_receive, d); | ||
992 | + | ||
993 | + snprintf(d->vc->info_str, sizeof(d->vc->info_str), | ||
994 | + "%s macaddr=%02x:%02x:%02x:%02x:%02x:%02x", info_str, | ||
995 | + d->nd->macaddr[0], d->nd->macaddr[1], d->nd->macaddr[2], | ||
996 | + d->nd->macaddr[3], d->nd->macaddr[4], d->nd->macaddr[5]); | ||
997 | + | ||
998 | + register_savevm(info_str, d->instance, 1, nic_save, nic_load, d); | ||
999 | +} |
hw/e1000_hw.h
0 → 100644
1 | +/******************************************************************************* | ||
2 | + | ||
3 | + Intel PRO/1000 Linux driver | ||
4 | + Copyright(c) 1999 - 2006 Intel Corporation. | ||
5 | + | ||
6 | + This program is free software; you can redistribute it and/or modify it | ||
7 | + under the terms and conditions of the GNU General Public License, | ||
8 | + version 2, as published by the Free Software Foundation. | ||
9 | + | ||
10 | + This program is distributed in the hope it will be useful, but WITHOUT | ||
11 | + ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | ||
12 | + FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | ||
13 | + more details. | ||
14 | + | ||
15 | + You should have received a copy of the GNU General Public License along with | ||
16 | + this program; if not, write to the Free Software Foundation, Inc., | ||
17 | + 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. | ||
18 | + | ||
19 | + The full GNU General Public License is included in this distribution in | ||
20 | + the file called "COPYING". | ||
21 | + | ||
22 | + Contact Information: | ||
23 | + Linux NICS <linux.nics@intel.com> | ||
24 | + e1000-devel Mailing List <e1000-devel@lists.sourceforge.net> | ||
25 | + Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 | ||
26 | + | ||
27 | +*******************************************************************************/ | ||
28 | + | ||
29 | +/* e1000_hw.h | ||
30 | + * Structures, enums, and macros for the MAC | ||
31 | + */ | ||
32 | + | ||
33 | +#ifndef _E1000_HW_H_ | ||
34 | +#define _E1000_HW_H_ | ||
35 | + | ||
36 | + | ||
37 | +/* PCI Device IDs */ | ||
38 | +#define E1000_DEV_ID_82542 0x1000 | ||
39 | +#define E1000_DEV_ID_82543GC_FIBER 0x1001 | ||
40 | +#define E1000_DEV_ID_82543GC_COPPER 0x1004 | ||
41 | +#define E1000_DEV_ID_82544EI_COPPER 0x1008 | ||
42 | +#define E1000_DEV_ID_82544EI_FIBER 0x1009 | ||
43 | +#define E1000_DEV_ID_82544GC_COPPER 0x100C | ||
44 | +#define E1000_DEV_ID_82544GC_LOM 0x100D | ||
45 | +#define E1000_DEV_ID_82540EM 0x100E | ||
46 | +#define E1000_DEV_ID_82540EM_LOM 0x1015 | ||
47 | +#define E1000_DEV_ID_82540EP_LOM 0x1016 | ||
48 | +#define E1000_DEV_ID_82540EP 0x1017 | ||
49 | +#define E1000_DEV_ID_82540EP_LP 0x101E | ||
50 | +#define E1000_DEV_ID_82545EM_COPPER 0x100F | ||
51 | +#define E1000_DEV_ID_82545EM_FIBER 0x1011 | ||
52 | +#define E1000_DEV_ID_82545GM_COPPER 0x1026 | ||
53 | +#define E1000_DEV_ID_82545GM_FIBER 0x1027 | ||
54 | +#define E1000_DEV_ID_82545GM_SERDES 0x1028 | ||
55 | +#define E1000_DEV_ID_82546EB_COPPER 0x1010 | ||
56 | +#define E1000_DEV_ID_82546EB_FIBER 0x1012 | ||
57 | +#define E1000_DEV_ID_82546EB_QUAD_COPPER 0x101D | ||
58 | +#define E1000_DEV_ID_82541EI 0x1013 | ||
59 | +#define E1000_DEV_ID_82541EI_MOBILE 0x1018 | ||
60 | +#define E1000_DEV_ID_82541ER_LOM 0x1014 | ||
61 | +#define E1000_DEV_ID_82541ER 0x1078 | ||
62 | +#define E1000_DEV_ID_82547GI 0x1075 | ||
63 | +#define E1000_DEV_ID_82541GI 0x1076 | ||
64 | +#define E1000_DEV_ID_82541GI_MOBILE 0x1077 | ||
65 | +#define E1000_DEV_ID_82541GI_LF 0x107C | ||
66 | +#define E1000_DEV_ID_82546GB_COPPER 0x1079 | ||
67 | +#define E1000_DEV_ID_82546GB_FIBER 0x107A | ||
68 | +#define E1000_DEV_ID_82546GB_SERDES 0x107B | ||
69 | +#define E1000_DEV_ID_82546GB_PCIE 0x108A | ||
70 | +#define E1000_DEV_ID_82546GB_QUAD_COPPER 0x1099 | ||
71 | +#define E1000_DEV_ID_82547EI 0x1019 | ||
72 | +#define E1000_DEV_ID_82547EI_MOBILE 0x101A | ||
73 | +#define E1000_DEV_ID_82571EB_COPPER 0x105E | ||
74 | +#define E1000_DEV_ID_82571EB_FIBER 0x105F | ||
75 | +#define E1000_DEV_ID_82571EB_SERDES 0x1060 | ||
76 | +#define E1000_DEV_ID_82571EB_QUAD_COPPER 0x10A4 | ||
77 | +#define E1000_DEV_ID_82571PT_QUAD_COPPER 0x10D5 | ||
78 | +#define E1000_DEV_ID_82571EB_QUAD_FIBER 0x10A5 | ||
79 | +#define E1000_DEV_ID_82571EB_QUAD_COPPER_LOWPROFILE 0x10BC | ||
80 | +#define E1000_DEV_ID_82571EB_SERDES_DUAL 0x10D9 | ||
81 | +#define E1000_DEV_ID_82571EB_SERDES_QUAD 0x10DA | ||
82 | +#define E1000_DEV_ID_82572EI_COPPER 0x107D | ||
83 | +#define E1000_DEV_ID_82572EI_FIBER 0x107E | ||
84 | +#define E1000_DEV_ID_82572EI_SERDES 0x107F | ||
85 | +#define E1000_DEV_ID_82572EI 0x10B9 | ||
86 | +#define E1000_DEV_ID_82573E 0x108B | ||
87 | +#define E1000_DEV_ID_82573E_IAMT 0x108C | ||
88 | +#define E1000_DEV_ID_82573L 0x109A | ||
89 | +#define E1000_DEV_ID_82546GB_QUAD_COPPER_KSP3 0x10B5 | ||
90 | +#define E1000_DEV_ID_80003ES2LAN_COPPER_DPT 0x1096 | ||
91 | +#define E1000_DEV_ID_80003ES2LAN_SERDES_DPT 0x1098 | ||
92 | +#define E1000_DEV_ID_80003ES2LAN_COPPER_SPT 0x10BA | ||
93 | +#define E1000_DEV_ID_80003ES2LAN_SERDES_SPT 0x10BB | ||
94 | + | ||
95 | +#define E1000_DEV_ID_ICH8_IGP_M_AMT 0x1049 | ||
96 | +#define E1000_DEV_ID_ICH8_IGP_AMT 0x104A | ||
97 | +#define E1000_DEV_ID_ICH8_IGP_C 0x104B | ||
98 | +#define E1000_DEV_ID_ICH8_IFE 0x104C | ||
99 | +#define E1000_DEV_ID_ICH8_IFE_GT 0x10C4 | ||
100 | +#define E1000_DEV_ID_ICH8_IFE_G 0x10C5 | ||
101 | +#define E1000_DEV_ID_ICH8_IGP_M 0x104D | ||
102 | + | ||
103 | +/* Register Set. (82543, 82544) | ||
104 | + * | ||
105 | + * Registers are defined to be 32 bits and should be accessed as 32 bit values. | ||
106 | + * These registers are physically located on the NIC, but are mapped into the | ||
107 | + * host memory address space. | ||
108 | + * | ||
109 | + * RW - register is both readable and writable | ||
110 | + * RO - register is read only | ||
111 | + * WO - register is write only | ||
112 | + * R/clr - register is read only and is cleared when read | ||
113 | + * A - register array | ||
114 | + */ | ||
115 | +#define E1000_CTRL 0x00000 /* Device Control - RW */ | ||
116 | +#define E1000_CTRL_DUP 0x00004 /* Device Control Duplicate (Shadow) - RW */ | ||
117 | +#define E1000_STATUS 0x00008 /* Device Status - RO */ | ||
118 | +#define E1000_EECD 0x00010 /* EEPROM/Flash Control - RW */ | ||
119 | +#define E1000_EERD 0x00014 /* EEPROM Read - RW */ | ||
120 | +#define E1000_CTRL_EXT 0x00018 /* Extended Device Control - RW */ | ||
121 | +#define E1000_FLA 0x0001C /* Flash Access - RW */ | ||
122 | +#define E1000_MDIC 0x00020 /* MDI Control - RW */ | ||
123 | +#define E1000_SCTL 0x00024 /* SerDes Control - RW */ | ||
124 | +#define E1000_FEXTNVM 0x00028 /* Future Extended NVM register */ | ||
125 | +#define E1000_FCAL 0x00028 /* Flow Control Address Low - RW */ | ||
126 | +#define E1000_FCAH 0x0002C /* Flow Control Address High -RW */ | ||
127 | +#define E1000_FCT 0x00030 /* Flow Control Type - RW */ | ||
128 | +#define E1000_VET 0x00038 /* VLAN Ether Type - RW */ | ||
129 | +#define E1000_ICR 0x000C0 /* Interrupt Cause Read - R/clr */ | ||
130 | +#define E1000_ITR 0x000C4 /* Interrupt Throttling Rate - RW */ | ||
131 | +#define E1000_ICS 0x000C8 /* Interrupt Cause Set - WO */ | ||
132 | +#define E1000_IMS 0x000D0 /* Interrupt Mask Set - RW */ | ||
133 | +#define E1000_IMC 0x000D8 /* Interrupt Mask Clear - WO */ | ||
134 | +#define E1000_IAM 0x000E0 /* Interrupt Acknowledge Auto Mask */ | ||
135 | +#define E1000_RCTL 0x00100 /* RX Control - RW */ | ||
136 | +#define E1000_RDTR1 0x02820 /* RX Delay Timer (1) - RW */ | ||
137 | +#define E1000_RDBAL1 0x02900 /* RX Descriptor Base Address Low (1) - RW */ | ||
138 | +#define E1000_RDBAH1 0x02904 /* RX Descriptor Base Address High (1) - RW */ | ||
139 | +#define E1000_RDLEN1 0x02908 /* RX Descriptor Length (1) - RW */ | ||
140 | +#define E1000_RDH1 0x02910 /* RX Descriptor Head (1) - RW */ | ||
141 | +#define E1000_RDT1 0x02918 /* RX Descriptor Tail (1) - RW */ | ||
142 | +#define E1000_FCTTV 0x00170 /* Flow Control Transmit Timer Value - RW */ | ||
143 | +#define E1000_TXCW 0x00178 /* TX Configuration Word - RW */ | ||
144 | +#define E1000_RXCW 0x00180 /* RX Configuration Word - RO */ | ||
145 | +#define E1000_TCTL 0x00400 /* TX Control - RW */ | ||
146 | +#define E1000_TCTL_EXT 0x00404 /* Extended TX Control - RW */ | ||
147 | +#define E1000_TIPG 0x00410 /* TX Inter-packet gap -RW */ | ||
148 | +#define E1000_TBT 0x00448 /* TX Burst Timer - RW */ | ||
149 | +#define E1000_AIT 0x00458 /* Adaptive Interframe Spacing Throttle - RW */ | ||
150 | +#define E1000_LEDCTL 0x00E00 /* LED Control - RW */ | ||
151 | +#define E1000_EXTCNF_CTRL 0x00F00 /* Extended Configuration Control */ | ||
152 | +#define E1000_EXTCNF_SIZE 0x00F08 /* Extended Configuration Size */ | ||
153 | +#define E1000_PHY_CTRL 0x00F10 /* PHY Control Register in CSR */ | ||
154 | +#define FEXTNVM_SW_CONFIG 0x0001 | ||
155 | +#define E1000_PBA 0x01000 /* Packet Buffer Allocation - RW */ | ||
156 | +#define E1000_PBS 0x01008 /* Packet Buffer Size */ | ||
157 | +#define E1000_EEMNGCTL 0x01010 /* MNG EEprom Control */ | ||
158 | +#define E1000_FLASH_UPDATES 1000 | ||
159 | +#define E1000_EEARBC 0x01024 /* EEPROM Auto Read Bus Control */ | ||
160 | +#define E1000_FLASHT 0x01028 /* FLASH Timer Register */ | ||
161 | +#define E1000_EEWR 0x0102C /* EEPROM Write Register - RW */ | ||
162 | +#define E1000_FLSWCTL 0x01030 /* FLASH control register */ | ||
163 | +#define E1000_FLSWDATA 0x01034 /* FLASH data register */ | ||
164 | +#define E1000_FLSWCNT 0x01038 /* FLASH Access Counter */ | ||
165 | +#define E1000_FLOP 0x0103C /* FLASH Opcode Register */ | ||
166 | +#define E1000_ERT 0x02008 /* Early Rx Threshold - RW */ | ||
167 | +#define E1000_FCRTL 0x02160 /* Flow Control Receive Threshold Low - RW */ | ||
168 | +#define E1000_FCRTH 0x02168 /* Flow Control Receive Threshold High - RW */ | ||
169 | +#define E1000_PSRCTL 0x02170 /* Packet Split Receive Control - RW */ | ||
170 | +#define E1000_RDBAL 0x02800 /* RX Descriptor Base Address Low - RW */ | ||
171 | +#define E1000_RDBAH 0x02804 /* RX Descriptor Base Address High - RW */ | ||
172 | +#define E1000_RDLEN 0x02808 /* RX Descriptor Length - RW */ | ||
173 | +#define E1000_RDH 0x02810 /* RX Descriptor Head - RW */ | ||
174 | +#define E1000_RDT 0x02818 /* RX Descriptor Tail - RW */ | ||
175 | +#define E1000_RDTR 0x02820 /* RX Delay Timer - RW */ | ||
176 | +#define E1000_RDBAL0 E1000_RDBAL /* RX Desc Base Address Low (0) - RW */ | ||
177 | +#define E1000_RDBAH0 E1000_RDBAH /* RX Desc Base Address High (0) - RW */ | ||
178 | +#define E1000_RDLEN0 E1000_RDLEN /* RX Desc Length (0) - RW */ | ||
179 | +#define E1000_RDH0 E1000_RDH /* RX Desc Head (0) - RW */ | ||
180 | +#define E1000_RDT0 E1000_RDT /* RX Desc Tail (0) - RW */ | ||
181 | +#define E1000_RDTR0 E1000_RDTR /* RX Delay Timer (0) - RW */ | ||
182 | +#define E1000_RXDCTL 0x02828 /* RX Descriptor Control queue 0 - RW */ | ||
183 | +#define E1000_RXDCTL1 0x02928 /* RX Descriptor Control queue 1 - RW */ | ||
184 | +#define E1000_RADV 0x0282C /* RX Interrupt Absolute Delay Timer - RW */ | ||
185 | +#define E1000_RSRPD 0x02C00 /* RX Small Packet Detect - RW */ | ||
186 | +#define E1000_RAID 0x02C08 /* Receive Ack Interrupt Delay - RW */ | ||
187 | +#define E1000_TXDMAC 0x03000 /* TX DMA Control - RW */ | ||
188 | +#define E1000_KABGTXD 0x03004 /* AFE Band Gap Transmit Ref Data */ | ||
189 | +#define E1000_TDFH 0x03410 /* TX Data FIFO Head - RW */ | ||
190 | +#define E1000_TDFT 0x03418 /* TX Data FIFO Tail - RW */ | ||
191 | +#define E1000_TDFHS 0x03420 /* TX Data FIFO Head Saved - RW */ | ||
192 | +#define E1000_TDFTS 0x03428 /* TX Data FIFO Tail Saved - RW */ | ||
193 | +#define E1000_TDFPC 0x03430 /* TX Data FIFO Packet Count - RW */ | ||
194 | +#define E1000_TDBAL 0x03800 /* TX Descriptor Base Address Low - RW */ | ||
195 | +#define E1000_TDBAH 0x03804 /* TX Descriptor Base Address High - RW */ | ||
196 | +#define E1000_TDLEN 0x03808 /* TX Descriptor Length - RW */ | ||
197 | +#define E1000_TDH 0x03810 /* TX Descriptor Head - RW */ | ||
198 | +#define E1000_TDT 0x03818 /* TX Descripotr Tail - RW */ | ||
199 | +#define E1000_TIDV 0x03820 /* TX Interrupt Delay Value - RW */ | ||
200 | +#define E1000_TXDCTL 0x03828 /* TX Descriptor Control - RW */ | ||
201 | +#define E1000_TADV 0x0382C /* TX Interrupt Absolute Delay Val - RW */ | ||
202 | +#define E1000_TSPMT 0x03830 /* TCP Segmentation PAD & Min Threshold - RW */ | ||
203 | +#define E1000_TARC0 0x03840 /* TX Arbitration Count (0) */ | ||
204 | +#define E1000_TDBAL1 0x03900 /* TX Desc Base Address Low (1) - RW */ | ||
205 | +#define E1000_TDBAH1 0x03904 /* TX Desc Base Address High (1) - RW */ | ||
206 | +#define E1000_TDLEN1 0x03908 /* TX Desc Length (1) - RW */ | ||
207 | +#define E1000_TDH1 0x03910 /* TX Desc Head (1) - RW */ | ||
208 | +#define E1000_TDT1 0x03918 /* TX Desc Tail (1) - RW */ | ||
209 | +#define E1000_TXDCTL1 0x03928 /* TX Descriptor Control (1) - RW */ | ||
210 | +#define E1000_TARC1 0x03940 /* TX Arbitration Count (1) */ | ||
211 | +#define E1000_CRCERRS 0x04000 /* CRC Error Count - R/clr */ | ||
212 | +#define E1000_ALGNERRC 0x04004 /* Alignment Error Count - R/clr */ | ||
213 | +#define E1000_SYMERRS 0x04008 /* Symbol Error Count - R/clr */ | ||
214 | +#define E1000_RXERRC 0x0400C /* Receive Error Count - R/clr */ | ||
215 | +#define E1000_MPC 0x04010 /* Missed Packet Count - R/clr */ | ||
216 | +#define E1000_SCC 0x04014 /* Single Collision Count - R/clr */ | ||
217 | +#define E1000_ECOL 0x04018 /* Excessive Collision Count - R/clr */ | ||
218 | +#define E1000_MCC 0x0401C /* Multiple Collision Count - R/clr */ | ||
219 | +#define E1000_LATECOL 0x04020 /* Late Collision Count - R/clr */ | ||
220 | +#define E1000_COLC 0x04028 /* Collision Count - R/clr */ | ||
221 | +#define E1000_DC 0x04030 /* Defer Count - R/clr */ | ||
222 | +#define E1000_TNCRS 0x04034 /* TX-No CRS - R/clr */ | ||
223 | +#define E1000_SEC 0x04038 /* Sequence Error Count - R/clr */ | ||
224 | +#define E1000_CEXTERR 0x0403C /* Carrier Extension Error Count - R/clr */ | ||
225 | +#define E1000_RLEC 0x04040 /* Receive Length Error Count - R/clr */ | ||
226 | +#define E1000_XONRXC 0x04048 /* XON RX Count - R/clr */ | ||
227 | +#define E1000_XONTXC 0x0404C /* XON TX Count - R/clr */ | ||
228 | +#define E1000_XOFFRXC 0x04050 /* XOFF RX Count - R/clr */ | ||
229 | +#define E1000_XOFFTXC 0x04054 /* XOFF TX Count - R/clr */ | ||
230 | +#define E1000_FCRUC 0x04058 /* Flow Control RX Unsupported Count- R/clr */ | ||
231 | +#define E1000_PRC64 0x0405C /* Packets RX (64 bytes) - R/clr */ | ||
232 | +#define E1000_PRC127 0x04060 /* Packets RX (65-127 bytes) - R/clr */ | ||
233 | +#define E1000_PRC255 0x04064 /* Packets RX (128-255 bytes) - R/clr */ | ||
234 | +#define E1000_PRC511 0x04068 /* Packets RX (255-511 bytes) - R/clr */ | ||
235 | +#define E1000_PRC1023 0x0406C /* Packets RX (512-1023 bytes) - R/clr */ | ||
236 | +#define E1000_PRC1522 0x04070 /* Packets RX (1024-1522 bytes) - R/clr */ | ||
237 | +#define E1000_GPRC 0x04074 /* Good Packets RX Count - R/clr */ | ||
238 | +#define E1000_BPRC 0x04078 /* Broadcast Packets RX Count - R/clr */ | ||
239 | +#define E1000_MPRC 0x0407C /* Multicast Packets RX Count - R/clr */ | ||
240 | +#define E1000_GPTC 0x04080 /* Good Packets TX Count - R/clr */ | ||
241 | +#define E1000_GORCL 0x04088 /* Good Octets RX Count Low - R/clr */ | ||
242 | +#define E1000_GORCH 0x0408C /* Good Octets RX Count High - R/clr */ | ||
243 | +#define E1000_GOTCL 0x04090 /* Good Octets TX Count Low - R/clr */ | ||
244 | +#define E1000_GOTCH 0x04094 /* Good Octets TX Count High - R/clr */ | ||
245 | +#define E1000_RNBC 0x040A0 /* RX No Buffers Count - R/clr */ | ||
246 | +#define E1000_RUC 0x040A4 /* RX Undersize Count - R/clr */ | ||
247 | +#define E1000_RFC 0x040A8 /* RX Fragment Count - R/clr */ | ||
248 | +#define E1000_ROC 0x040AC /* RX Oversize Count - R/clr */ | ||
249 | +#define E1000_RJC 0x040B0 /* RX Jabber Count - R/clr */ | ||
250 | +#define E1000_MGTPRC 0x040B4 /* Management Packets RX Count - R/clr */ | ||
251 | +#define E1000_MGTPDC 0x040B8 /* Management Packets Dropped Count - R/clr */ | ||
252 | +#define E1000_MGTPTC 0x040BC /* Management Packets TX Count - R/clr */ | ||
253 | +#define E1000_TORL 0x040C0 /* Total Octets RX Low - R/clr */ | ||
254 | +#define E1000_TORH 0x040C4 /* Total Octets RX High - R/clr */ | ||
255 | +#define E1000_TOTL 0x040C8 /* Total Octets TX Low - R/clr */ | ||
256 | +#define E1000_TOTH 0x040CC /* Total Octets TX High - R/clr */ | ||
257 | +#define E1000_TPR 0x040D0 /* Total Packets RX - R/clr */ | ||
258 | +#define E1000_TPT 0x040D4 /* Total Packets TX - R/clr */ | ||
259 | +#define E1000_PTC64 0x040D8 /* Packets TX (64 bytes) - R/clr */ | ||
260 | +#define E1000_PTC127 0x040DC /* Packets TX (65-127 bytes) - R/clr */ | ||
261 | +#define E1000_PTC255 0x040E0 /* Packets TX (128-255 bytes) - R/clr */ | ||
262 | +#define E1000_PTC511 0x040E4 /* Packets TX (256-511 bytes) - R/clr */ | ||
263 | +#define E1000_PTC1023 0x040E8 /* Packets TX (512-1023 bytes) - R/clr */ | ||
264 | +#define E1000_PTC1522 0x040EC /* Packets TX (1024-1522 Bytes) - R/clr */ | ||
265 | +#define E1000_MPTC 0x040F0 /* Multicast Packets TX Count - R/clr */ | ||
266 | +#define E1000_BPTC 0x040F4 /* Broadcast Packets TX Count - R/clr */ | ||
267 | +#define E1000_TSCTC 0x040F8 /* TCP Segmentation Context TX - R/clr */ | ||
268 | +#define E1000_TSCTFC 0x040FC /* TCP Segmentation Context TX Fail - R/clr */ | ||
269 | +#define E1000_IAC 0x04100 /* Interrupt Assertion Count */ | ||
270 | +#define E1000_ICRXPTC 0x04104 /* Interrupt Cause Rx Packet Timer Expire Count */ | ||
271 | +#define E1000_ICRXATC 0x04108 /* Interrupt Cause Rx Absolute Timer Expire Count */ | ||
272 | +#define E1000_ICTXPTC 0x0410C /* Interrupt Cause Tx Packet Timer Expire Count */ | ||
273 | +#define E1000_ICTXATC 0x04110 /* Interrupt Cause Tx Absolute Timer Expire Count */ | ||
274 | +#define E1000_ICTXQEC 0x04118 /* Interrupt Cause Tx Queue Empty Count */ | ||
275 | +#define E1000_ICTXQMTC 0x0411C /* Interrupt Cause Tx Queue Minimum Threshold Count */ | ||
276 | +#define E1000_ICRXDMTC 0x04120 /* Interrupt Cause Rx Descriptor Minimum Threshold Count */ | ||
277 | +#define E1000_ICRXOC 0x04124 /* Interrupt Cause Receiver Overrun Count */ | ||
278 | +#define E1000_RXCSUM 0x05000 /* RX Checksum Control - RW */ | ||
279 | +#define E1000_RFCTL 0x05008 /* Receive Filter Control*/ | ||
280 | +#define E1000_MTA 0x05200 /* Multicast Table Array - RW Array */ | ||
281 | +#define E1000_RA 0x05400 /* Receive Address - RW Array */ | ||
282 | +#define E1000_VFTA 0x05600 /* VLAN Filter Table Array - RW Array */ | ||
283 | +#define E1000_WUC 0x05800 /* Wakeup Control - RW */ | ||
284 | +#define E1000_WUFC 0x05808 /* Wakeup Filter Control - RW */ | ||
285 | +#define E1000_WUS 0x05810 /* Wakeup Status - RO */ | ||
286 | +#define E1000_MANC 0x05820 /* Management Control - RW */ | ||
287 | +#define E1000_IPAV 0x05838 /* IP Address Valid - RW */ | ||
288 | +#define E1000_IP4AT 0x05840 /* IPv4 Address Table - RW Array */ | ||
289 | +#define E1000_IP6AT 0x05880 /* IPv6 Address Table - RW Array */ | ||
290 | +#define E1000_WUPL 0x05900 /* Wakeup Packet Length - RW */ | ||
291 | +#define E1000_WUPM 0x05A00 /* Wakeup Packet Memory - RO A */ | ||
292 | +#define E1000_FFLT 0x05F00 /* Flexible Filter Length Table - RW Array */ | ||
293 | +#define E1000_HOST_IF 0x08800 /* Host Interface */ | ||
294 | +#define E1000_FFMT 0x09000 /* Flexible Filter Mask Table - RW Array */ | ||
295 | +#define E1000_FFVT 0x09800 /* Flexible Filter Value Table - RW Array */ | ||
296 | + | ||
297 | +#define E1000_KUMCTRLSTA 0x00034 /* MAC-PHY interface - RW */ | ||
298 | +#define E1000_MDPHYA 0x0003C /* PHY address - RW */ | ||
299 | +#define E1000_MANC2H 0x05860 /* Managment Control To Host - RW */ | ||
300 | +#define E1000_SW_FW_SYNC 0x05B5C /* Software-Firmware Synchronization - RW */ | ||
301 | + | ||
302 | +#define E1000_GCR 0x05B00 /* PCI-Ex Control */ | ||
303 | +#define E1000_GSCL_1 0x05B10 /* PCI-Ex Statistic Control #1 */ | ||
304 | +#define E1000_GSCL_2 0x05B14 /* PCI-Ex Statistic Control #2 */ | ||
305 | +#define E1000_GSCL_3 0x05B18 /* PCI-Ex Statistic Control #3 */ | ||
306 | +#define E1000_GSCL_4 0x05B1C /* PCI-Ex Statistic Control #4 */ | ||
307 | +#define E1000_FACTPS 0x05B30 /* Function Active and Power State to MNG */ | ||
308 | +#define E1000_SWSM 0x05B50 /* SW Semaphore */ | ||
309 | +#define E1000_FWSM 0x05B54 /* FW Semaphore */ | ||
310 | +#define E1000_FFLT_DBG 0x05F04 /* Debug Register */ | ||
311 | +#define E1000_HICR 0x08F00 /* Host Inteface Control */ | ||
312 | + | ||
313 | +/* RSS registers */ | ||
314 | +#define E1000_CPUVEC 0x02C10 /* CPU Vector Register - RW */ | ||
315 | +#define E1000_MRQC 0x05818 /* Multiple Receive Control - RW */ | ||
316 | +#define E1000_RETA 0x05C00 /* Redirection Table - RW Array */ | ||
317 | +#define E1000_RSSRK 0x05C80 /* RSS Random Key - RW Array */ | ||
318 | +#define E1000_RSSIM 0x05864 /* RSS Interrupt Mask */ | ||
319 | +#define E1000_RSSIR 0x05868 /* RSS Interrupt Request */ | ||
320 | + | ||
321 | +/* PHY 1000 MII Register/Bit Definitions */ | ||
322 | +/* PHY Registers defined by IEEE */ | ||
323 | +#define PHY_CTRL 0x00 /* Control Register */ | ||
324 | +#define PHY_STATUS 0x01 /* Status Regiser */ | ||
325 | +#define PHY_ID1 0x02 /* Phy Id Reg (word 1) */ | ||
326 | +#define PHY_ID2 0x03 /* Phy Id Reg (word 2) */ | ||
327 | +#define PHY_AUTONEG_ADV 0x04 /* Autoneg Advertisement */ | ||
328 | +#define PHY_LP_ABILITY 0x05 /* Link Partner Ability (Base Page) */ | ||
329 | +#define PHY_AUTONEG_EXP 0x06 /* Autoneg Expansion Reg */ | ||
330 | +#define PHY_NEXT_PAGE_TX 0x07 /* Next Page TX */ | ||
331 | +#define PHY_LP_NEXT_PAGE 0x08 /* Link Partner Next Page */ | ||
332 | +#define PHY_1000T_CTRL 0x09 /* 1000Base-T Control Reg */ | ||
333 | +#define PHY_1000T_STATUS 0x0A /* 1000Base-T Status Reg */ | ||
334 | +#define PHY_EXT_STATUS 0x0F /* Extended Status Reg */ | ||
335 | + | ||
336 | +#define MAX_PHY_REG_ADDRESS 0x1F /* 5 bit address bus (0-0x1F) */ | ||
337 | +#define MAX_PHY_MULTI_PAGE_REG 0xF /* Registers equal on all pages */ | ||
338 | + | ||
339 | +/* M88E1000 Specific Registers */ | ||
340 | +#define M88E1000_PHY_SPEC_CTRL 0x10 /* PHY Specific Control Register */ | ||
341 | +#define M88E1000_PHY_SPEC_STATUS 0x11 /* PHY Specific Status Register */ | ||
342 | +#define M88E1000_INT_ENABLE 0x12 /* Interrupt Enable Register */ | ||
343 | +#define M88E1000_INT_STATUS 0x13 /* Interrupt Status Register */ | ||
344 | +#define M88E1000_EXT_PHY_SPEC_CTRL 0x14 /* Extended PHY Specific Control */ | ||
345 | +#define M88E1000_RX_ERR_CNTR 0x15 /* Receive Error Counter */ | ||
346 | + | ||
347 | +#define M88E1000_PHY_EXT_CTRL 0x1A /* PHY extend control register */ | ||
348 | +#define M88E1000_PHY_PAGE_SELECT 0x1D /* Reg 29 for page number setting */ | ||
349 | +#define M88E1000_PHY_GEN_CONTROL 0x1E /* Its meaning depends on reg 29 */ | ||
350 | +#define M88E1000_PHY_VCO_REG_BIT8 0x100 /* Bits 8 & 11 are adjusted for */ | ||
351 | +#define M88E1000_PHY_VCO_REG_BIT11 0x800 /* improved BER performance */ | ||
352 | + | ||
353 | +/* Interrupt Cause Read */ | ||
354 | +#define E1000_ICR_TXDW 0x00000001 /* Transmit desc written back */ | ||
355 | +#define E1000_ICR_TXQE 0x00000002 /* Transmit Queue empty */ | ||
356 | +#define E1000_ICR_LSC 0x00000004 /* Link Status Change */ | ||
357 | +#define E1000_ICR_RXSEQ 0x00000008 /* rx sequence error */ | ||
358 | +#define E1000_ICR_RXDMT0 0x00000010 /* rx desc min. threshold (0) */ | ||
359 | +#define E1000_ICR_RXO 0x00000040 /* rx overrun */ | ||
360 | +#define E1000_ICR_RXT0 0x00000080 /* rx timer intr (ring 0) */ | ||
361 | +#define E1000_ICR_MDAC 0x00000200 /* MDIO access complete */ | ||
362 | +#define E1000_ICR_RXCFG 0x00000400 /* RX /c/ ordered set */ | ||
363 | +#define E1000_ICR_GPI_EN0 0x00000800 /* GP Int 0 */ | ||
364 | +#define E1000_ICR_GPI_EN1 0x00001000 /* GP Int 1 */ | ||
365 | +#define E1000_ICR_GPI_EN2 0x00002000 /* GP Int 2 */ | ||
366 | +#define E1000_ICR_GPI_EN3 0x00004000 /* GP Int 3 */ | ||
367 | +#define E1000_ICR_TXD_LOW 0x00008000 | ||
368 | +#define E1000_ICR_SRPD 0x00010000 | ||
369 | +#define E1000_ICR_ACK 0x00020000 /* Receive Ack frame */ | ||
370 | +#define E1000_ICR_MNG 0x00040000 /* Manageability event */ | ||
371 | +#define E1000_ICR_DOCK 0x00080000 /* Dock/Undock */ | ||
372 | +#define E1000_ICR_INT_ASSERTED 0x80000000 /* If this bit asserted, the driver should claim the interrupt */ | ||
373 | +#define E1000_ICR_RXD_FIFO_PAR0 0x00100000 /* queue 0 Rx descriptor FIFO parity error */ | ||
374 | +#define E1000_ICR_TXD_FIFO_PAR0 0x00200000 /* queue 0 Tx descriptor FIFO parity error */ | ||
375 | +#define E1000_ICR_HOST_ARB_PAR 0x00400000 /* host arb read buffer parity error */ | ||
376 | +#define E1000_ICR_PB_PAR 0x00800000 /* packet buffer parity error */ | ||
377 | +#define E1000_ICR_RXD_FIFO_PAR1 0x01000000 /* queue 1 Rx descriptor FIFO parity error */ | ||
378 | +#define E1000_ICR_TXD_FIFO_PAR1 0x02000000 /* queue 1 Tx descriptor FIFO parity error */ | ||
379 | +#define E1000_ICR_ALL_PARITY 0x03F00000 /* all parity error bits */ | ||
380 | +#define E1000_ICR_DSW 0x00000020 /* FW changed the status of DISSW bit in the FWSM */ | ||
381 | +#define E1000_ICR_PHYINT 0x00001000 /* LAN connected device generates an interrupt */ | ||
382 | +#define E1000_ICR_EPRST 0x00100000 /* ME handware reset occurs */ | ||
383 | + | ||
384 | +/* Interrupt Cause Set */ | ||
385 | +#define E1000_ICS_TXDW E1000_ICR_TXDW /* Transmit desc written back */ | ||
386 | +#define E1000_ICS_TXQE E1000_ICR_TXQE /* Transmit Queue empty */ | ||
387 | +#define E1000_ICS_LSC E1000_ICR_LSC /* Link Status Change */ | ||
388 | +#define E1000_ICS_RXSEQ E1000_ICR_RXSEQ /* rx sequence error */ | ||
389 | +#define E1000_ICS_RXDMT0 E1000_ICR_RXDMT0 /* rx desc min. threshold */ | ||
390 | +#define E1000_ICS_RXO E1000_ICR_RXO /* rx overrun */ | ||
391 | +#define E1000_ICS_RXT0 E1000_ICR_RXT0 /* rx timer intr */ | ||
392 | +#define E1000_ICS_MDAC E1000_ICR_MDAC /* MDIO access complete */ | ||
393 | +#define E1000_ICS_RXCFG E1000_ICR_RXCFG /* RX /c/ ordered set */ | ||
394 | +#define E1000_ICS_GPI_EN0 E1000_ICR_GPI_EN0 /* GP Int 0 */ | ||
395 | +#define E1000_ICS_GPI_EN1 E1000_ICR_GPI_EN1 /* GP Int 1 */ | ||
396 | +#define E1000_ICS_GPI_EN2 E1000_ICR_GPI_EN2 /* GP Int 2 */ | ||
397 | +#define E1000_ICS_GPI_EN3 E1000_ICR_GPI_EN3 /* GP Int 3 */ | ||
398 | +#define E1000_ICS_TXD_LOW E1000_ICR_TXD_LOW | ||
399 | +#define E1000_ICS_SRPD E1000_ICR_SRPD | ||
400 | +#define E1000_ICS_ACK E1000_ICR_ACK /* Receive Ack frame */ | ||
401 | +#define E1000_ICS_MNG E1000_ICR_MNG /* Manageability event */ | ||
402 | +#define E1000_ICS_DOCK E1000_ICR_DOCK /* Dock/Undock */ | ||
403 | +#define E1000_ICS_RXD_FIFO_PAR0 E1000_ICR_RXD_FIFO_PAR0 /* queue 0 Rx descriptor FIFO parity error */ | ||
404 | +#define E1000_ICS_TXD_FIFO_PAR0 E1000_ICR_TXD_FIFO_PAR0 /* queue 0 Tx descriptor FIFO parity error */ | ||
405 | +#define E1000_ICS_HOST_ARB_PAR E1000_ICR_HOST_ARB_PAR /* host arb read buffer parity error */ | ||
406 | +#define E1000_ICS_PB_PAR E1000_ICR_PB_PAR /* packet buffer parity error */ | ||
407 | +#define E1000_ICS_RXD_FIFO_PAR1 E1000_ICR_RXD_FIFO_PAR1 /* queue 1 Rx descriptor FIFO parity error */ | ||
408 | +#define E1000_ICS_TXD_FIFO_PAR1 E1000_ICR_TXD_FIFO_PAR1 /* queue 1 Tx descriptor FIFO parity error */ | ||
409 | +#define E1000_ICS_DSW E1000_ICR_DSW | ||
410 | +#define E1000_ICS_PHYINT E1000_ICR_PHYINT | ||
411 | +#define E1000_ICS_EPRST E1000_ICR_EPRST | ||
412 | + | ||
413 | +/* Interrupt Mask Set */ | ||
414 | +#define E1000_IMS_TXDW E1000_ICR_TXDW /* Transmit desc written back */ | ||
415 | +#define E1000_IMS_TXQE E1000_ICR_TXQE /* Transmit Queue empty */ | ||
416 | +#define E1000_IMS_LSC E1000_ICR_LSC /* Link Status Change */ | ||
417 | +#define E1000_IMS_RXSEQ E1000_ICR_RXSEQ /* rx sequence error */ | ||
418 | +#define E1000_IMS_RXDMT0 E1000_ICR_RXDMT0 /* rx desc min. threshold */ | ||
419 | +#define E1000_IMS_RXO E1000_ICR_RXO /* rx overrun */ | ||
420 | +#define E1000_IMS_RXT0 E1000_ICR_RXT0 /* rx timer intr */ | ||
421 | +#define E1000_IMS_MDAC E1000_ICR_MDAC /* MDIO access complete */ | ||
422 | +#define E1000_IMS_RXCFG E1000_ICR_RXCFG /* RX /c/ ordered set */ | ||
423 | +#define E1000_IMS_GPI_EN0 E1000_ICR_GPI_EN0 /* GP Int 0 */ | ||
424 | +#define E1000_IMS_GPI_EN1 E1000_ICR_GPI_EN1 /* GP Int 1 */ | ||
425 | +#define E1000_IMS_GPI_EN2 E1000_ICR_GPI_EN2 /* GP Int 2 */ | ||
426 | +#define E1000_IMS_GPI_EN3 E1000_ICR_GPI_EN3 /* GP Int 3 */ | ||
427 | +#define E1000_IMS_TXD_LOW E1000_ICR_TXD_LOW | ||
428 | +#define E1000_IMS_SRPD E1000_ICR_SRPD | ||
429 | +#define E1000_IMS_ACK E1000_ICR_ACK /* Receive Ack frame */ | ||
430 | +#define E1000_IMS_MNG E1000_ICR_MNG /* Manageability event */ | ||
431 | +#define E1000_IMS_DOCK E1000_ICR_DOCK /* Dock/Undock */ | ||
432 | +#define E1000_IMS_RXD_FIFO_PAR0 E1000_ICR_RXD_FIFO_PAR0 /* queue 0 Rx descriptor FIFO parity error */ | ||
433 | +#define E1000_IMS_TXD_FIFO_PAR0 E1000_ICR_TXD_FIFO_PAR0 /* queue 0 Tx descriptor FIFO parity error */ | ||
434 | +#define E1000_IMS_HOST_ARB_PAR E1000_ICR_HOST_ARB_PAR /* host arb read buffer parity error */ | ||
435 | +#define E1000_IMS_PB_PAR E1000_ICR_PB_PAR /* packet buffer parity error */ | ||
436 | +#define E1000_IMS_RXD_FIFO_PAR1 E1000_ICR_RXD_FIFO_PAR1 /* queue 1 Rx descriptor FIFO parity error */ | ||
437 | +#define E1000_IMS_TXD_FIFO_PAR1 E1000_ICR_TXD_FIFO_PAR1 /* queue 1 Tx descriptor FIFO parity error */ | ||
438 | +#define E1000_IMS_DSW E1000_ICR_DSW | ||
439 | +#define E1000_IMS_PHYINT E1000_ICR_PHYINT | ||
440 | +#define E1000_IMS_EPRST E1000_ICR_EPRST | ||
441 | + | ||
442 | +/* Interrupt Mask Clear */ | ||
443 | +#define E1000_IMC_TXDW E1000_ICR_TXDW /* Transmit desc written back */ | ||
444 | +#define E1000_IMC_TXQE E1000_ICR_TXQE /* Transmit Queue empty */ | ||
445 | +#define E1000_IMC_LSC E1000_ICR_LSC /* Link Status Change */ | ||
446 | +#define E1000_IMC_RXSEQ E1000_ICR_RXSEQ /* rx sequence error */ | ||
447 | +#define E1000_IMC_RXDMT0 E1000_ICR_RXDMT0 /* rx desc min. threshold */ | ||
448 | +#define E1000_IMC_RXO E1000_ICR_RXO /* rx overrun */ | ||
449 | +#define E1000_IMC_RXT0 E1000_ICR_RXT0 /* rx timer intr */ | ||
450 | +#define E1000_IMC_MDAC E1000_ICR_MDAC /* MDIO access complete */ | ||
451 | +#define E1000_IMC_RXCFG E1000_ICR_RXCFG /* RX /c/ ordered set */ | ||
452 | +#define E1000_IMC_GPI_EN0 E1000_ICR_GPI_EN0 /* GP Int 0 */ | ||
453 | +#define E1000_IMC_GPI_EN1 E1000_ICR_GPI_EN1 /* GP Int 1 */ | ||
454 | +#define E1000_IMC_GPI_EN2 E1000_ICR_GPI_EN2 /* GP Int 2 */ | ||
455 | +#define E1000_IMC_GPI_EN3 E1000_ICR_GPI_EN3 /* GP Int 3 */ | ||
456 | +#define E1000_IMC_TXD_LOW E1000_ICR_TXD_LOW | ||
457 | +#define E1000_IMC_SRPD E1000_ICR_SRPD | ||
458 | +#define E1000_IMC_ACK E1000_ICR_ACK /* Receive Ack frame */ | ||
459 | +#define E1000_IMC_MNG E1000_ICR_MNG /* Manageability event */ | ||
460 | +#define E1000_IMC_DOCK E1000_ICR_DOCK /* Dock/Undock */ | ||
461 | +#define E1000_IMC_RXD_FIFO_PAR0 E1000_ICR_RXD_FIFO_PAR0 /* queue 0 Rx descriptor FIFO parity error */ | ||
462 | +#define E1000_IMC_TXD_FIFO_PAR0 E1000_ICR_TXD_FIFO_PAR0 /* queue 0 Tx descriptor FIFO parity error */ | ||
463 | +#define E1000_IMC_HOST_ARB_PAR E1000_ICR_HOST_ARB_PAR /* host arb read buffer parity error */ | ||
464 | +#define E1000_IMC_PB_PAR E1000_ICR_PB_PAR /* packet buffer parity error */ | ||
465 | +#define E1000_IMC_RXD_FIFO_PAR1 E1000_ICR_RXD_FIFO_PAR1 /* queue 1 Rx descriptor FIFO parity error */ | ||
466 | +#define E1000_IMC_TXD_FIFO_PAR1 E1000_ICR_TXD_FIFO_PAR1 /* queue 1 Tx descriptor FIFO parity error */ | ||
467 | +#define E1000_IMC_DSW E1000_ICR_DSW | ||
468 | +#define E1000_IMC_PHYINT E1000_ICR_PHYINT | ||
469 | +#define E1000_IMC_EPRST E1000_ICR_EPRST | ||
470 | + | ||
471 | +/* Receive Control */ | ||
472 | +#define E1000_RCTL_RST 0x00000001 /* Software reset */ | ||
473 | +#define E1000_RCTL_EN 0x00000002 /* enable */ | ||
474 | +#define E1000_RCTL_SBP 0x00000004 /* store bad packet */ | ||
475 | +#define E1000_RCTL_UPE 0x00000008 /* unicast promiscuous enable */ | ||
476 | +#define E1000_RCTL_MPE 0x00000010 /* multicast promiscuous enab */ | ||
477 | +#define E1000_RCTL_LPE 0x00000020 /* long packet enable */ | ||
478 | +#define E1000_RCTL_LBM_NO 0x00000000 /* no loopback mode */ | ||
479 | +#define E1000_RCTL_LBM_MAC 0x00000040 /* MAC loopback mode */ | ||
480 | +#define E1000_RCTL_LBM_SLP 0x00000080 /* serial link loopback mode */ | ||
481 | +#define E1000_RCTL_LBM_TCVR 0x000000C0 /* tcvr loopback mode */ | ||
482 | +#define E1000_RCTL_DTYP_MASK 0x00000C00 /* Descriptor type mask */ | ||
483 | +#define E1000_RCTL_DTYP_PS 0x00000400 /* Packet Split descriptor */ | ||
484 | +#define E1000_RCTL_RDMTS_HALF 0x00000000 /* rx desc min threshold size */ | ||
485 | +#define E1000_RCTL_RDMTS_QUAT 0x00000100 /* rx desc min threshold size */ | ||
486 | +#define E1000_RCTL_RDMTS_EIGTH 0x00000200 /* rx desc min threshold size */ | ||
487 | +#define E1000_RCTL_MO_SHIFT 12 /* multicast offset shift */ | ||
488 | +#define E1000_RCTL_MO_0 0x00000000 /* multicast offset 11:0 */ | ||
489 | +#define E1000_RCTL_MO_1 0x00001000 /* multicast offset 12:1 */ | ||
490 | +#define E1000_RCTL_MO_2 0x00002000 /* multicast offset 13:2 */ | ||
491 | +#define E1000_RCTL_MO_3 0x00003000 /* multicast offset 15:4 */ | ||
492 | +#define E1000_RCTL_MDR 0x00004000 /* multicast desc ring 0 */ | ||
493 | +#define E1000_RCTL_BAM 0x00008000 /* broadcast enable */ | ||
494 | +/* these buffer sizes are valid if E1000_RCTL_BSEX is 0 */ | ||
495 | +#define E1000_RCTL_SZ_2048 0x00000000 /* rx buffer size 2048 */ | ||
496 | +#define E1000_RCTL_SZ_1024 0x00010000 /* rx buffer size 1024 */ | ||
497 | +#define E1000_RCTL_SZ_512 0x00020000 /* rx buffer size 512 */ | ||
498 | +#define E1000_RCTL_SZ_256 0x00030000 /* rx buffer size 256 */ | ||
499 | +/* these buffer sizes are valid if E1000_RCTL_BSEX is 1 */ | ||
500 | +#define E1000_RCTL_SZ_16384 0x00010000 /* rx buffer size 16384 */ | ||
501 | +#define E1000_RCTL_SZ_8192 0x00020000 /* rx buffer size 8192 */ | ||
502 | +#define E1000_RCTL_SZ_4096 0x00030000 /* rx buffer size 4096 */ | ||
503 | +#define E1000_RCTL_VFE 0x00040000 /* vlan filter enable */ | ||
504 | +#define E1000_RCTL_CFIEN 0x00080000 /* canonical form enable */ | ||
505 | +#define E1000_RCTL_CFI 0x00100000 /* canonical form indicator */ | ||
506 | +#define E1000_RCTL_DPF 0x00400000 /* discard pause frames */ | ||
507 | +#define E1000_RCTL_PMCF 0x00800000 /* pass MAC control frames */ | ||
508 | +#define E1000_RCTL_BSEX 0x02000000 /* Buffer size extension */ | ||
509 | +#define E1000_RCTL_SECRC 0x04000000 /* Strip Ethernet CRC */ | ||
510 | +#define E1000_RCTL_FLXBUF_MASK 0x78000000 /* Flexible buffer size */ | ||
511 | +#define E1000_RCTL_FLXBUF_SHIFT 27 /* Flexible buffer shift */ | ||
512 | + | ||
513 | + | ||
514 | +#define E1000_EEPROM_SWDPIN0 0x0001 /* SWDPIN 0 EEPROM Value */ | ||
515 | +#define E1000_EEPROM_LED_LOGIC 0x0020 /* Led Logic Word */ | ||
516 | +#define E1000_EEPROM_RW_REG_DATA 16 /* Offset to data in EEPROM read/write registers */ | ||
517 | +#define E1000_EEPROM_RW_REG_DONE 2 /* Offset to READ/WRITE done bit */ | ||
518 | +#define E1000_EEPROM_RW_REG_START 1 /* First bit for telling part to start operation */ | ||
519 | +#define E1000_EEPROM_RW_ADDR_SHIFT 2 /* Shift to the address bits */ | ||
520 | +#define E1000_EEPROM_POLL_WRITE 1 /* Flag for polling for write complete */ | ||
521 | +#define E1000_EEPROM_POLL_READ 0 /* Flag for polling for read complete */ | ||
522 | +/* Register Bit Masks */ | ||
523 | +/* Device Control */ | ||
524 | +#define E1000_CTRL_FD 0x00000001 /* Full duplex.0=half; 1=full */ | ||
525 | +#define E1000_CTRL_BEM 0x00000002 /* Endian Mode.0=little,1=big */ | ||
526 | +#define E1000_CTRL_PRIOR 0x00000004 /* Priority on PCI. 0=rx,1=fair */ | ||
527 | +#define E1000_CTRL_GIO_MASTER_DISABLE 0x00000004 /*Blocks new Master requests */ | ||
528 | +#define E1000_CTRL_LRST 0x00000008 /* Link reset. 0=normal,1=reset */ | ||
529 | +#define E1000_CTRL_TME 0x00000010 /* Test mode. 0=normal,1=test */ | ||
530 | +#define E1000_CTRL_SLE 0x00000020 /* Serial Link on 0=dis,1=en */ | ||
531 | +#define E1000_CTRL_ASDE 0x00000020 /* Auto-speed detect enable */ | ||
532 | +#define E1000_CTRL_SLU 0x00000040 /* Set link up (Force Link) */ | ||
533 | +#define E1000_CTRL_ILOS 0x00000080 /* Invert Loss-Of Signal */ | ||
534 | +#define E1000_CTRL_SPD_SEL 0x00000300 /* Speed Select Mask */ | ||
535 | +#define E1000_CTRL_SPD_10 0x00000000 /* Force 10Mb */ | ||
536 | +#define E1000_CTRL_SPD_100 0x00000100 /* Force 100Mb */ | ||
537 | +#define E1000_CTRL_SPD_1000 0x00000200 /* Force 1Gb */ | ||
538 | +#define E1000_CTRL_BEM32 0x00000400 /* Big Endian 32 mode */ | ||
539 | +#define E1000_CTRL_FRCSPD 0x00000800 /* Force Speed */ | ||
540 | +#define E1000_CTRL_FRCDPX 0x00001000 /* Force Duplex */ | ||
541 | +#define E1000_CTRL_D_UD_EN 0x00002000 /* Dock/Undock enable */ | ||
542 | +#define E1000_CTRL_D_UD_POLARITY 0x00004000 /* Defined polarity of Dock/Undock indication in SDP[0] */ | ||
543 | +#define E1000_CTRL_FORCE_PHY_RESET 0x00008000 /* Reset both PHY ports, through PHYRST_N pin */ | ||
544 | +#define E1000_CTRL_EXT_LINK_EN 0x00010000 /* enable link status from external LINK_0 and LINK_1 pins */ | ||
545 | +#define E1000_CTRL_SWDPIN0 0x00040000 /* SWDPIN 0 value */ | ||
546 | +#define E1000_CTRL_SWDPIN1 0x00080000 /* SWDPIN 1 value */ | ||
547 | +#define E1000_CTRL_SWDPIN2 0x00100000 /* SWDPIN 2 value */ | ||
548 | +#define E1000_CTRL_SWDPIN3 0x00200000 /* SWDPIN 3 value */ | ||
549 | +#define E1000_CTRL_SWDPIO0 0x00400000 /* SWDPIN 0 Input or output */ | ||
550 | +#define E1000_CTRL_SWDPIO1 0x00800000 /* SWDPIN 1 input or output */ | ||
551 | +#define E1000_CTRL_SWDPIO2 0x01000000 /* SWDPIN 2 input or output */ | ||
552 | +#define E1000_CTRL_SWDPIO3 0x02000000 /* SWDPIN 3 input or output */ | ||
553 | +#define E1000_CTRL_RST 0x04000000 /* Global reset */ | ||
554 | +#define E1000_CTRL_RFCE 0x08000000 /* Receive Flow Control enable */ | ||
555 | +#define E1000_CTRL_TFCE 0x10000000 /* Transmit flow control enable */ | ||
556 | +#define E1000_CTRL_RTE 0x20000000 /* Routing tag enable */ | ||
557 | +#define E1000_CTRL_VME 0x40000000 /* IEEE VLAN mode enable */ | ||
558 | +#define E1000_CTRL_PHY_RST 0x80000000 /* PHY Reset */ | ||
559 | +#define E1000_CTRL_SW2FW_INT 0x02000000 /* Initiate an interrupt to manageability engine */ | ||
560 | + | ||
561 | +/* Device Status */ | ||
562 | +#define E1000_STATUS_FD 0x00000001 /* Full duplex.0=half,1=full */ | ||
563 | +#define E1000_STATUS_LU 0x00000002 /* Link up.0=no,1=link */ | ||
564 | +#define E1000_STATUS_FUNC_MASK 0x0000000C /* PCI Function Mask */ | ||
565 | +#define E1000_STATUS_FUNC_SHIFT 2 | ||
566 | +#define E1000_STATUS_FUNC_0 0x00000000 /* Function 0 */ | ||
567 | +#define E1000_STATUS_FUNC_1 0x00000004 /* Function 1 */ | ||
568 | +#define E1000_STATUS_TXOFF 0x00000010 /* transmission paused */ | ||
569 | +#define E1000_STATUS_TBIMODE 0x00000020 /* TBI mode */ | ||
570 | +#define E1000_STATUS_SPEED_MASK 0x000000C0 | ||
571 | +#define E1000_STATUS_SPEED_10 0x00000000 /* Speed 10Mb/s */ | ||
572 | +#define E1000_STATUS_SPEED_100 0x00000040 /* Speed 100Mb/s */ | ||
573 | +#define E1000_STATUS_SPEED_1000 0x00000080 /* Speed 1000Mb/s */ | ||
574 | +#define E1000_STATUS_LAN_INIT_DONE 0x00000200 /* Lan Init Completion | ||
575 | + by EEPROM/Flash */ | ||
576 | +#define E1000_STATUS_ASDV 0x00000300 /* Auto speed detect value */ | ||
577 | +#define E1000_STATUS_DOCK_CI 0x00000800 /* Change in Dock/Undock state. Clear on write '0'. */ | ||
578 | +#define E1000_STATUS_GIO_MASTER_ENABLE 0x00080000 /* Status of Master requests. */ | ||
579 | +#define E1000_STATUS_MTXCKOK 0x00000400 /* MTX clock running OK */ | ||
580 | +#define E1000_STATUS_PCI66 0x00000800 /* In 66Mhz slot */ | ||
581 | +#define E1000_STATUS_BUS64 0x00001000 /* In 64 bit slot */ | ||
582 | +#define E1000_STATUS_PCIX_MODE 0x00002000 /* PCI-X mode */ | ||
583 | +#define E1000_STATUS_PCIX_SPEED 0x0000C000 /* PCI-X bus speed */ | ||
584 | +#define E1000_STATUS_BMC_SKU_0 0x00100000 /* BMC USB redirect disabled */ | ||
585 | +#define E1000_STATUS_BMC_SKU_1 0x00200000 /* BMC SRAM disabled */ | ||
586 | +#define E1000_STATUS_BMC_SKU_2 0x00400000 /* BMC SDRAM disabled */ | ||
587 | +#define E1000_STATUS_BMC_CRYPTO 0x00800000 /* BMC crypto disabled */ | ||
588 | +#define E1000_STATUS_BMC_LITE 0x01000000 /* BMC external code execution disabled */ | ||
589 | +#define E1000_STATUS_RGMII_ENABLE 0x02000000 /* RGMII disabled */ | ||
590 | +#define E1000_STATUS_FUSE_8 0x04000000 | ||
591 | +#define E1000_STATUS_FUSE_9 0x08000000 | ||
592 | +#define E1000_STATUS_SERDES0_DIS 0x10000000 /* SERDES disabled on port 0 */ | ||
593 | +#define E1000_STATUS_SERDES1_DIS 0x20000000 /* SERDES disabled on port 1 */ | ||
594 | + | ||
595 | +/* EEPROM/Flash Control */ | ||
596 | +#define E1000_EECD_SK 0x00000001 /* EEPROM Clock */ | ||
597 | +#define E1000_EECD_CS 0x00000002 /* EEPROM Chip Select */ | ||
598 | +#define E1000_EECD_DI 0x00000004 /* EEPROM Data In */ | ||
599 | +#define E1000_EECD_DO 0x00000008 /* EEPROM Data Out */ | ||
600 | +#define E1000_EECD_FWE_MASK 0x00000030 | ||
601 | +#define E1000_EECD_FWE_DIS 0x00000010 /* Disable FLASH writes */ | ||
602 | +#define E1000_EECD_FWE_EN 0x00000020 /* Enable FLASH writes */ | ||
603 | +#define E1000_EECD_FWE_SHIFT 4 | ||
604 | +#define E1000_EECD_REQ 0x00000040 /* EEPROM Access Request */ | ||
605 | +#define E1000_EECD_GNT 0x00000080 /* EEPROM Access Grant */ | ||
606 | +#define E1000_EECD_PRES 0x00000100 /* EEPROM Present */ | ||
607 | +#define E1000_EECD_SIZE 0x00000200 /* EEPROM Size (0=64 word 1=256 word) */ | ||
608 | +#define E1000_EECD_ADDR_BITS 0x00000400 /* EEPROM Addressing bits based on type | ||
609 | + * (0-small, 1-large) */ | ||
610 | +#define E1000_EECD_TYPE 0x00002000 /* EEPROM Type (1-SPI, 0-Microwire) */ | ||
611 | +#ifndef E1000_EEPROM_GRANT_ATTEMPTS | ||
612 | +#define E1000_EEPROM_GRANT_ATTEMPTS 1000 /* EEPROM # attempts to gain grant */ | ||
613 | +#endif | ||
614 | +#define E1000_EECD_AUTO_RD 0x00000200 /* EEPROM Auto Read done */ | ||
615 | +#define E1000_EECD_SIZE_EX_MASK 0x00007800 /* EEprom Size */ | ||
616 | +#define E1000_EECD_SIZE_EX_SHIFT 11 | ||
617 | +#define E1000_EECD_NVADDS 0x00018000 /* NVM Address Size */ | ||
618 | +#define E1000_EECD_SELSHAD 0x00020000 /* Select Shadow RAM */ | ||
619 | +#define E1000_EECD_INITSRAM 0x00040000 /* Initialize Shadow RAM */ | ||
620 | +#define E1000_EECD_FLUPD 0x00080000 /* Update FLASH */ | ||
621 | +#define E1000_EECD_AUPDEN 0x00100000 /* Enable Autonomous FLASH update */ | ||
622 | +#define E1000_EECD_SHADV 0x00200000 /* Shadow RAM Data Valid */ | ||
623 | +#define E1000_EECD_SEC1VAL 0x00400000 /* Sector One Valid */ | ||
624 | +#define E1000_EECD_SECVAL_SHIFT 22 | ||
625 | +#define E1000_STM_OPCODE 0xDB00 | ||
626 | +#define E1000_HICR_FW_RESET 0xC0 | ||
627 | + | ||
628 | +#define E1000_SHADOW_RAM_WORDS 2048 | ||
629 | +#define E1000_ICH_NVM_SIG_WORD 0x13 | ||
630 | +#define E1000_ICH_NVM_SIG_MASK 0xC0 | ||
631 | + | ||
632 | +/* MDI Control */ | ||
633 | +#define E1000_MDIC_DATA_MASK 0x0000FFFF | ||
634 | +#define E1000_MDIC_REG_MASK 0x001F0000 | ||
635 | +#define E1000_MDIC_REG_SHIFT 16 | ||
636 | +#define E1000_MDIC_PHY_MASK 0x03E00000 | ||
637 | +#define E1000_MDIC_PHY_SHIFT 21 | ||
638 | +#define E1000_MDIC_OP_WRITE 0x04000000 | ||
639 | +#define E1000_MDIC_OP_READ 0x08000000 | ||
640 | +#define E1000_MDIC_READY 0x10000000 | ||
641 | +#define E1000_MDIC_INT_EN 0x20000000 | ||
642 | +#define E1000_MDIC_ERROR 0x40000000 | ||
643 | + | ||
644 | +/* EEPROM Commands - Microwire */ | ||
645 | +#define EEPROM_READ_OPCODE_MICROWIRE 0x6 /* EEPROM read opcode */ | ||
646 | +#define EEPROM_WRITE_OPCODE_MICROWIRE 0x5 /* EEPROM write opcode */ | ||
647 | +#define EEPROM_ERASE_OPCODE_MICROWIRE 0x7 /* EEPROM erase opcode */ | ||
648 | +#define EEPROM_EWEN_OPCODE_MICROWIRE 0x13 /* EEPROM erase/write enable */ | ||
649 | +#define EEPROM_EWDS_OPCODE_MICROWIRE 0x10 /* EEPROM erast/write disable */ | ||
650 | + | ||
651 | +/* EEPROM Word Offsets */ | ||
652 | +#define EEPROM_COMPAT 0x0003 | ||
653 | +#define EEPROM_ID_LED_SETTINGS 0x0004 | ||
654 | +#define EEPROM_VERSION 0x0005 | ||
655 | +#define EEPROM_SERDES_AMPLITUDE 0x0006 /* For SERDES output amplitude adjustment. */ | ||
656 | +#define EEPROM_PHY_CLASS_WORD 0x0007 | ||
657 | +#define EEPROM_INIT_CONTROL1_REG 0x000A | ||
658 | +#define EEPROM_INIT_CONTROL2_REG 0x000F | ||
659 | +#define EEPROM_SWDEF_PINS_CTRL_PORT_1 0x0010 | ||
660 | +#define EEPROM_INIT_CONTROL3_PORT_B 0x0014 | ||
661 | +#define EEPROM_INIT_3GIO_3 0x001A | ||
662 | +#define EEPROM_SWDEF_PINS_CTRL_PORT_0 0x0020 | ||
663 | +#define EEPROM_INIT_CONTROL3_PORT_A 0x0024 | ||
664 | +#define EEPROM_CFG 0x0012 | ||
665 | +#define EEPROM_FLASH_VERSION 0x0032 | ||
666 | +#define EEPROM_CHECKSUM_REG 0x003F | ||
667 | + | ||
668 | +#define E1000_EEPROM_CFG_DONE 0x00040000 /* MNG config cycle done */ | ||
669 | +#define E1000_EEPROM_CFG_DONE_PORT_1 0x00080000 /* ...for second port */ | ||
670 | + | ||
671 | +/* Transmit Descriptor */ | ||
672 | +struct e1000_tx_desc { | ||
673 | + uint64_t buffer_addr; /* Address of the descriptor's data buffer */ | ||
674 | + union { | ||
675 | + uint32_t data; | ||
676 | + struct { | ||
677 | + uint16_t length; /* Data buffer length */ | ||
678 | + uint8_t cso; /* Checksum offset */ | ||
679 | + uint8_t cmd; /* Descriptor control */ | ||
680 | + } flags; | ||
681 | + } lower; | ||
682 | + union { | ||
683 | + uint32_t data; | ||
684 | + struct { | ||
685 | + uint8_t status; /* Descriptor status */ | ||
686 | + uint8_t css; /* Checksum start */ | ||
687 | + uint16_t special; | ||
688 | + } fields; | ||
689 | + } upper; | ||
690 | +}; | ||
691 | + | ||
692 | +/* Transmit Descriptor bit definitions */ | ||
693 | +#define E1000_TXD_DTYP_D 0x00100000 /* Data Descriptor */ | ||
694 | +#define E1000_TXD_DTYP_C 0x00000000 /* Context Descriptor */ | ||
695 | +#define E1000_TXD_POPTS_IXSM 0x01 /* Insert IP checksum */ | ||
696 | +#define E1000_TXD_POPTS_TXSM 0x02 /* Insert TCP/UDP checksum */ | ||
697 | +#define E1000_TXD_CMD_EOP 0x01000000 /* End of Packet */ | ||
698 | +#define E1000_TXD_CMD_IFCS 0x02000000 /* Insert FCS (Ethernet CRC) */ | ||
699 | +#define E1000_TXD_CMD_IC 0x04000000 /* Insert Checksum */ | ||
700 | +#define E1000_TXD_CMD_RS 0x08000000 /* Report Status */ | ||
701 | +#define E1000_TXD_CMD_RPS 0x10000000 /* Report Packet Sent */ | ||
702 | +#define E1000_TXD_CMD_DEXT 0x20000000 /* Descriptor extension (0 = legacy) */ | ||
703 | +#define E1000_TXD_CMD_VLE 0x40000000 /* Add VLAN tag */ | ||
704 | +#define E1000_TXD_CMD_IDE 0x80000000 /* Enable Tidv register */ | ||
705 | +#define E1000_TXD_STAT_DD 0x00000001 /* Descriptor Done */ | ||
706 | +#define E1000_TXD_STAT_EC 0x00000002 /* Excess Collisions */ | ||
707 | +#define E1000_TXD_STAT_LC 0x00000004 /* Late Collisions */ | ||
708 | +#define E1000_TXD_STAT_TU 0x00000008 /* Transmit underrun */ | ||
709 | +#define E1000_TXD_CMD_TCP 0x01000000 /* TCP packet */ | ||
710 | +#define E1000_TXD_CMD_IP 0x02000000 /* IP packet */ | ||
711 | +#define E1000_TXD_CMD_TSE 0x04000000 /* TCP Seg enable */ | ||
712 | +#define E1000_TXD_STAT_TC 0x00000004 /* Tx Underrun */ | ||
713 | + | ||
714 | +/* Transmit Control */ | ||
715 | +#define E1000_TCTL_RST 0x00000001 /* software reset */ | ||
716 | +#define E1000_TCTL_EN 0x00000002 /* enable tx */ | ||
717 | +#define E1000_TCTL_BCE 0x00000004 /* busy check enable */ | ||
718 | +#define E1000_TCTL_PSP 0x00000008 /* pad short packets */ | ||
719 | +#define E1000_TCTL_CT 0x00000ff0 /* collision threshold */ | ||
720 | +#define E1000_TCTL_COLD 0x003ff000 /* collision distance */ | ||
721 | +#define E1000_TCTL_SWXOFF 0x00400000 /* SW Xoff transmission */ | ||
722 | +#define E1000_TCTL_PBE 0x00800000 /* Packet Burst Enable */ | ||
723 | +#define E1000_TCTL_RTLC 0x01000000 /* Re-transmit on late collision */ | ||
724 | +#define E1000_TCTL_NRTU 0x02000000 /* No Re-transmit on underrun */ | ||
725 | +#define E1000_TCTL_MULR 0x10000000 /* Multiple request support */ | ||
726 | + | ||
727 | +/* Receive Descriptor */ | ||
728 | +struct e1000_rx_desc { | ||
729 | + uint64_t buffer_addr; /* Address of the descriptor's data buffer */ | ||
730 | + uint16_t length; /* Length of data DMAed into data buffer */ | ||
731 | + uint16_t csum; /* Packet checksum */ | ||
732 | + uint8_t status; /* Descriptor status */ | ||
733 | + uint8_t errors; /* Descriptor Errors */ | ||
734 | + uint16_t special; | ||
735 | +}; | ||
736 | + | ||
737 | +/* Receive Decriptor bit definitions */ | ||
738 | +#define E1000_RXD_STAT_DD 0x01 /* Descriptor Done */ | ||
739 | +#define E1000_RXD_STAT_EOP 0x02 /* End of Packet */ | ||
740 | +#define E1000_RXD_STAT_IXSM 0x04 /* Ignore checksum */ | ||
741 | +#define E1000_RXD_STAT_VP 0x08 /* IEEE VLAN Packet */ | ||
742 | +#define E1000_RXD_STAT_UDPCS 0x10 /* UDP xsum caculated */ | ||
743 | +#define E1000_RXD_STAT_TCPCS 0x20 /* TCP xsum calculated */ | ||
744 | +#define E1000_RXD_STAT_IPCS 0x40 /* IP xsum calculated */ | ||
745 | +#define E1000_RXD_STAT_PIF 0x80 /* passed in-exact filter */ | ||
746 | +#define E1000_RXD_STAT_IPIDV 0x200 /* IP identification valid */ | ||
747 | +#define E1000_RXD_STAT_UDPV 0x400 /* Valid UDP checksum */ | ||
748 | +#define E1000_RXD_STAT_ACK 0x8000 /* ACK Packet indication */ | ||
749 | +#define E1000_RXD_ERR_CE 0x01 /* CRC Error */ | ||
750 | +#define E1000_RXD_ERR_SE 0x02 /* Symbol Error */ | ||
751 | +#define E1000_RXD_ERR_SEQ 0x04 /* Sequence Error */ | ||
752 | +#define E1000_RXD_ERR_CXE 0x10 /* Carrier Extension Error */ | ||
753 | +#define E1000_RXD_ERR_TCPE 0x20 /* TCP/UDP Checksum Error */ | ||
754 | +#define E1000_RXD_ERR_IPE 0x40 /* IP Checksum Error */ | ||
755 | +#define E1000_RXD_ERR_RXE 0x80 /* Rx Data Error */ | ||
756 | +#define E1000_RXD_SPC_VLAN_MASK 0x0FFF /* VLAN ID is in lower 12 bits */ | ||
757 | +#define E1000_RXD_SPC_PRI_MASK 0xE000 /* Priority is in upper 3 bits */ | ||
758 | +#define E1000_RXD_SPC_PRI_SHIFT 13 | ||
759 | +#define E1000_RXD_SPC_CFI_MASK 0x1000 /* CFI is bit 12 */ | ||
760 | +#define E1000_RXD_SPC_CFI_SHIFT 12 | ||
761 | + | ||
762 | +#define E1000_RXDEXT_STATERR_CE 0x01000000 | ||
763 | +#define E1000_RXDEXT_STATERR_SE 0x02000000 | ||
764 | +#define E1000_RXDEXT_STATERR_SEQ 0x04000000 | ||
765 | +#define E1000_RXDEXT_STATERR_CXE 0x10000000 | ||
766 | +#define E1000_RXDEXT_STATERR_TCPE 0x20000000 | ||
767 | +#define E1000_RXDEXT_STATERR_IPE 0x40000000 | ||
768 | +#define E1000_RXDEXT_STATERR_RXE 0x80000000 | ||
769 | + | ||
770 | +#define E1000_RXDPS_HDRSTAT_HDRSP 0x00008000 | ||
771 | +#define E1000_RXDPS_HDRSTAT_HDRLEN_MASK 0x000003FF | ||
772 | + | ||
773 | +/* Receive Address */ | ||
774 | +#define E1000_RAH_AV 0x80000000 /* Receive descriptor valid */ | ||
775 | + | ||
776 | +/* Offload Context Descriptor */ | ||
777 | +struct e1000_context_desc { | ||
778 | + union { | ||
779 | + uint32_t ip_config; | ||
780 | + struct { | ||
781 | + uint8_t ipcss; /* IP checksum start */ | ||
782 | + uint8_t ipcso; /* IP checksum offset */ | ||
783 | + uint16_t ipcse; /* IP checksum end */ | ||
784 | + } ip_fields; | ||
785 | + } lower_setup; | ||
786 | + union { | ||
787 | + uint32_t tcp_config; | ||
788 | + struct { | ||
789 | + uint8_t tucss; /* TCP checksum start */ | ||
790 | + uint8_t tucso; /* TCP checksum offset */ | ||
791 | + uint16_t tucse; /* TCP checksum end */ | ||
792 | + } tcp_fields; | ||
793 | + } upper_setup; | ||
794 | + uint32_t cmd_and_length; /* */ | ||
795 | + union { | ||
796 | + uint32_t data; | ||
797 | + struct { | ||
798 | + uint8_t status; /* Descriptor status */ | ||
799 | + uint8_t hdr_len; /* Header length */ | ||
800 | + uint16_t mss; /* Maximum segment size */ | ||
801 | + } fields; | ||
802 | + } tcp_seg_setup; | ||
803 | +}; | ||
804 | + | ||
805 | +/* Offload data descriptor */ | ||
806 | +struct e1000_data_desc { | ||
807 | + uint64_t buffer_addr; /* Address of the descriptor's buffer address */ | ||
808 | + union { | ||
809 | + uint32_t data; | ||
810 | + struct { | ||
811 | + uint16_t length; /* Data buffer length */ | ||
812 | + uint8_t typ_len_ext; /* */ | ||
813 | + uint8_t cmd; /* */ | ||
814 | + } flags; | ||
815 | + } lower; | ||
816 | + union { | ||
817 | + uint32_t data; | ||
818 | + struct { | ||
819 | + uint8_t status; /* Descriptor status */ | ||
820 | + uint8_t popts; /* Packet Options */ | ||
821 | + uint16_t special; /* */ | ||
822 | + } fields; | ||
823 | + } upper; | ||
824 | +}; | ||
825 | + | ||
826 | +/* Management Control */ | ||
827 | +#define E1000_MANC_SMBUS_EN 0x00000001 /* SMBus Enabled - RO */ | ||
828 | +#define E1000_MANC_ASF_EN 0x00000002 /* ASF Enabled - RO */ | ||
829 | +#define E1000_MANC_R_ON_FORCE 0x00000004 /* Reset on Force TCO - RO */ | ||
830 | +#define E1000_MANC_RMCP_EN 0x00000100 /* Enable RCMP 026Fh Filtering */ | ||
831 | +#define E1000_MANC_0298_EN 0x00000200 /* Enable RCMP 0298h Filtering */ | ||
832 | +#define E1000_MANC_IPV4_EN 0x00000400 /* Enable IPv4 */ | ||
833 | +#define E1000_MANC_IPV6_EN 0x00000800 /* Enable IPv6 */ | ||
834 | +#define E1000_MANC_SNAP_EN 0x00001000 /* Accept LLC/SNAP */ | ||
835 | +#define E1000_MANC_ARP_EN 0x00002000 /* Enable ARP Request Filtering */ | ||
836 | +#define E1000_MANC_NEIGHBOR_EN 0x00004000 /* Enable Neighbor Discovery | ||
837 | + * Filtering */ | ||
838 | +#define E1000_MANC_ARP_RES_EN 0x00008000 /* Enable ARP response Filtering */ | ||
839 | +#define E1000_MANC_TCO_RESET 0x00010000 /* TCO Reset Occurred */ | ||
840 | +#define E1000_MANC_RCV_TCO_EN 0x00020000 /* Receive TCO Packets Enabled */ | ||
841 | +#define E1000_MANC_REPORT_STATUS 0x00040000 /* Status Reporting Enabled */ | ||
842 | +#define E1000_MANC_RCV_ALL 0x00080000 /* Receive All Enabled */ | ||
843 | +#define E1000_MANC_BLK_PHY_RST_ON_IDE 0x00040000 /* Block phy resets */ | ||
844 | +#define E1000_MANC_EN_MAC_ADDR_FILTER 0x00100000 /* Enable MAC address | ||
845 | + * filtering */ | ||
846 | +#define E1000_MANC_EN_MNG2HOST 0x00200000 /* Enable MNG packets to host | ||
847 | + * memory */ | ||
848 | +#define E1000_MANC_EN_IP_ADDR_FILTER 0x00400000 /* Enable IP address | ||
849 | + * filtering */ | ||
850 | +#define E1000_MANC_EN_XSUM_FILTER 0x00800000 /* Enable checksum filtering */ | ||
851 | +#define E1000_MANC_BR_EN 0x01000000 /* Enable broadcast filtering */ | ||
852 | +#define E1000_MANC_SMB_REQ 0x01000000 /* SMBus Request */ | ||
853 | +#define E1000_MANC_SMB_GNT 0x02000000 /* SMBus Grant */ | ||
854 | +#define E1000_MANC_SMB_CLK_IN 0x04000000 /* SMBus Clock In */ | ||
855 | +#define E1000_MANC_SMB_DATA_IN 0x08000000 /* SMBus Data In */ | ||
856 | +#define E1000_MANC_SMB_DATA_OUT 0x10000000 /* SMBus Data Out */ | ||
857 | +#define E1000_MANC_SMB_CLK_OUT 0x20000000 /* SMBus Clock Out */ | ||
858 | + | ||
859 | +#define E1000_MANC_SMB_DATA_OUT_SHIFT 28 /* SMBus Data Out Shift */ | ||
860 | +#define E1000_MANC_SMB_CLK_OUT_SHIFT 29 /* SMBus Clock Out Shift */ | ||
861 | + | ||
862 | +/* For checksumming, the sum of all words in the EEPROM should equal 0xBABA. */ | ||
863 | +#define EEPROM_SUM 0xBABA | ||
864 | + | ||
865 | +#endif /* _E1000_HW_H_ */ |
hw/pci.c
@@ -636,11 +636,13 @@ void pci_nic_init(PCIBus *bus, NICInfo *nd, int devfn) | @@ -636,11 +636,13 @@ void pci_nic_init(PCIBus *bus, NICInfo *nd, int devfn) | ||
636 | pci_i82559er_init(bus, nd, devfn); | 636 | pci_i82559er_init(bus, nd, devfn); |
637 | } else if (strcmp(nd->model, "rtl8139") == 0) { | 637 | } else if (strcmp(nd->model, "rtl8139") == 0) { |
638 | pci_rtl8139_init(bus, nd, devfn); | 638 | pci_rtl8139_init(bus, nd, devfn); |
639 | + } else if (strcmp(nd->model, "e1000") == 0) { | ||
640 | + pci_e1000_init(bus, nd, devfn); | ||
639 | } else if (strcmp(nd->model, "pcnet") == 0) { | 641 | } else if (strcmp(nd->model, "pcnet") == 0) { |
640 | pci_pcnet_init(bus, nd, devfn); | 642 | pci_pcnet_init(bus, nd, devfn); |
641 | } else if (strcmp(nd->model, "?") == 0) { | 643 | } else if (strcmp(nd->model, "?") == 0) { |
642 | fprintf(stderr, "qemu: Supported PCI NICs: i82551 i82557b i82559er" | 644 | fprintf(stderr, "qemu: Supported PCI NICs: i82551 i82557b i82559er" |
643 | - " ne2k_pci pcnet rtl8139\n"); | 645 | + " ne2k_pci pcnet rtl8139 e1000\n"); |
644 | exit (1); | 646 | exit (1); |
645 | } else { | 647 | } else { |
646 | fprintf(stderr, "qemu: Unsupported NIC: %s\n", nd->model); | 648 | fprintf(stderr, "qemu: Unsupported NIC: %s\n", nd->model); |
hw/pci.h
@@ -126,6 +126,9 @@ void pci_ne2000_init(PCIBus *bus, NICInfo *nd, int devfn); | @@ -126,6 +126,9 @@ void pci_ne2000_init(PCIBus *bus, NICInfo *nd, int devfn); | ||
126 | 126 | ||
127 | void pci_rtl8139_init(PCIBus *bus, NICInfo *nd, int devfn); | 127 | void pci_rtl8139_init(PCIBus *bus, NICInfo *nd, int devfn); |
128 | 128 | ||
129 | +/* e1000.c */ | ||
130 | +void pci_e1000_init(PCIBus *bus, NICInfo *nd, int devfn); | ||
131 | + | ||
129 | /* pcnet.c */ | 132 | /* pcnet.c */ |
130 | void pci_pcnet_init(PCIBus *bus, NICInfo *nd, int devfn); | 133 | void pci_pcnet_init(PCIBus *bus, NICInfo *nd, int devfn); |
131 | 134 |
qemu-doc.texi
@@ -549,7 +549,7 @@ Qemu can emulate several different models of network card. | @@ -549,7 +549,7 @@ Qemu can emulate several different models of network card. | ||
549 | Valid values for @var{type} are | 549 | Valid values for @var{type} are |
550 | @code{i82551}, @code{i82557b}, @code{i82559er}, | 550 | @code{i82551}, @code{i82557b}, @code{i82559er}, |
551 | @code{ne2k_pci}, @code{ne2k_isa}, @code{pcnet}, @code{rtl8139}, | 551 | @code{ne2k_pci}, @code{ne2k_isa}, @code{pcnet}, @code{rtl8139}, |
552 | -@code{smc91c111}, @code{lance} and @code{mcf_fec}. | 552 | +@code{e1000}, @code{smc91c111}, @code{lance} and @code{mcf_fec}. |
553 | Not all devices are supported on all targets. Use -net nic,model=? | 553 | Not all devices are supported on all targets. Use -net nic,model=? |
554 | for a list of available devices for your target. | 554 | for a list of available devices for your target. |
555 | 555 |