Commit 7b936c0c42933b8b6bc308e71a6e20904f512eb4
1 parent
819385c5
sparc64 fixes (Blue Swirl)
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@1574 c046a42c-6fe2-441c-8c8c-71466251a162
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monitor.c
... | ... | @@ -1060,10 +1060,12 @@ static target_long monitor_get_tbl (struct MonitorDef *md, int val) |
1060 | 1060 | #endif |
1061 | 1061 | |
1062 | 1062 | #if defined(TARGET_SPARC) |
1063 | +#ifndef TARGET_SPARC64 | |
1063 | 1064 | static target_long monitor_get_psr (struct MonitorDef *md, int val) |
1064 | 1065 | { |
1065 | 1066 | return GET_PSR(cpu_single_env); |
1066 | 1067 | } |
1068 | +#endif | |
1067 | 1069 | |
1068 | 1070 | static target_long monitor_get_reg(struct MonitorDef *md, int val) |
1069 | 1071 | { |
... | ... | @@ -1202,8 +1204,10 @@ static MonitorDef monitor_defs[] = { |
1202 | 1204 | { "pc", offsetof(CPUState, pc) }, |
1203 | 1205 | { "npc", offsetof(CPUState, npc) }, |
1204 | 1206 | { "y", offsetof(CPUState, y) }, |
1207 | +#ifndef TARGET_SPARC64 | |
1205 | 1208 | { "psr", 0, &monitor_get_psr, }, |
1206 | 1209 | { "wim", offsetof(CPUState, wim) }, |
1210 | +#endif | |
1207 | 1211 | { "tbr", offsetof(CPUState, tbr) }, |
1208 | 1212 | { "fsr", offsetof(CPUState, fsr) }, |
1209 | 1213 | { "f0", offsetof(CPUState, fpr[0]) }, |
... | ... | @@ -1238,6 +1242,32 @@ static MonitorDef monitor_defs[] = { |
1238 | 1242 | { "f29", offsetof(CPUState, fpr[29]) }, |
1239 | 1243 | { "f30", offsetof(CPUState, fpr[30]) }, |
1240 | 1244 | { "f31", offsetof(CPUState, fpr[31]) }, |
1245 | +#ifdef TARGET_SPARC64 | |
1246 | + { "f32", offsetof(CPUState, fpr[32]) }, | |
1247 | + { "f34", offsetof(CPUState, fpr[34]) }, | |
1248 | + { "f36", offsetof(CPUState, fpr[36]) }, | |
1249 | + { "f38", offsetof(CPUState, fpr[38]) }, | |
1250 | + { "f40", offsetof(CPUState, fpr[40]) }, | |
1251 | + { "f42", offsetof(CPUState, fpr[42]) }, | |
1252 | + { "f44", offsetof(CPUState, fpr[44]) }, | |
1253 | + { "f46", offsetof(CPUState, fpr[46]) }, | |
1254 | + { "f48", offsetof(CPUState, fpr[48]) }, | |
1255 | + { "f50", offsetof(CPUState, fpr[50]) }, | |
1256 | + { "f52", offsetof(CPUState, fpr[52]) }, | |
1257 | + { "f54", offsetof(CPUState, fpr[54]) }, | |
1258 | + { "f56", offsetof(CPUState, fpr[56]) }, | |
1259 | + { "f58", offsetof(CPUState, fpr[58]) }, | |
1260 | + { "f60", offsetof(CPUState, fpr[60]) }, | |
1261 | + { "f62", offsetof(CPUState, fpr[62]) }, | |
1262 | + { "asi", offsetof(CPUState, asi) }, | |
1263 | + { "pstate", offsetof(CPUState, pstate) }, | |
1264 | + { "cansave", offsetof(CPUState, cansave) }, | |
1265 | + { "canrestore", offsetof(CPUState, canrestore) }, | |
1266 | + { "otherwin", offsetof(CPUState, otherwin) }, | |
1267 | + { "wstate", offsetof(CPUState, wstate) }, | |
1268 | + { "cleanwin", offsetof(CPUState, cleanwin) }, | |
1269 | + { "fprs", offsetof(CPUState, fprs) }, | |
1270 | +#endif | |
1241 | 1271 | #endif |
1242 | 1272 | { NULL }, |
1243 | 1273 | }; | ... | ... |