gwj / at91sam9263 · Commits

Commit 7b16968757973a64da8034c449d7b5aaccd683a2

Authored by blueswir1
1 parent f3c62823

add Arbiter Enable Register support to sparc iommu (Robert Reif) 


git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6118 c046a42c-6fe2-441c-8c8c-71466251a162
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Showing 1 changed file with 17 additions and 0 deletions
hw/iommu.c
  View file @7b16968
@@ -78,6 +78,19 @@ do { printf("IOMMU: " fmt , ##args); } while (0) @@ -78,6 +78,19 @@ do { printf("IOMMU: " fmt , ##args); } while (0)
78 78
79 #define IOMMU_AFAR (0x1004 >> 2) 79 #define IOMMU_AFAR (0x1004 >> 2)
80 80
  81 +#define IOMMU_AER (0x1008 >> 2) /* Arbiter Enable Register */
  82 +#define IOMMU_AER_EN_P0_ARB 0x00000001 /* MBus master 0x8 (Always 1) */
  83 +#define IOMMU_AER_EN_P1_ARB 0x00000002 /* MBus master 0x9 */
  84 +#define IOMMU_AER_EN_P2_ARB 0x00000004 /* MBus master 0xa */
  85 +#define IOMMU_AER_EN_P3_ARB 0x00000008 /* MBus master 0xb */
  86 +#define IOMMU_AER_EN_0 0x00010000 /* SBus slot 0 */
  87 +#define IOMMU_AER_EN_1 0x00020000 /* SBus slot 1 */
  88 +#define IOMMU_AER_EN_2 0x00040000 /* SBus slot 2 */
  89 +#define IOMMU_AER_EN_3 0x00080000 /* SBus slot 3 */
  90 +#define IOMMU_AER_EN_F 0x00100000 /* SBus on-board */
  91 +#define IOMMU_AER_SBW 0x80000000 /* S-to-M asynchronous writes */
  92 +#define IOMMU_AER_MASK 0x801f000f
  93 +
81 #define IOMMU_SBCFG0 (0x1010 >> 2) /* SBUS configration per-slot */ 94 #define IOMMU_SBCFG0 (0x1010 >> 2) /* SBUS configration per-slot */
82 #define IOMMU_SBCFG1 (0x1014 >> 2) /* SBUS configration per-slot */ 95 #define IOMMU_SBCFG1 (0x1014 >> 2) /* SBUS configration per-slot */
83 #define IOMMU_SBCFG2 (0x1018 >> 2) /* SBUS configration per-slot */ 96 #define IOMMU_SBCFG2 (0x1018 >> 2) /* SBUS configration per-slot */
@@ -196,6 +209,9 @@ static void iommu_mem_writel(void *opaque, target_phys_addr_t addr, @@ -196,6 +209,9 @@ static void iommu_mem_writel(void *opaque, target_phys_addr_t addr,
196 s->regs[saddr] = val; 209 s->regs[saddr] = val;
197 qemu_irq_lower(s->irq); 210 qemu_irq_lower(s->irq);
198 break; 211 break;
  212 + case IOMMU_AER:
  213 + s->regs[saddr] = (val & IOMMU_AER_MASK) | IOMMU_AER_EN_P0_ARB;
  214 + break;
199 case IOMMU_AFSR: 215 case IOMMU_AFSR:
200 s->regs[saddr] = (val & IOMMU_AFSR_MASK) | IOMMU_AFSR_RESV; 216 s->regs[saddr] = (val & IOMMU_AFSR_MASK) | IOMMU_AFSR_RESV;
201 qemu_irq_lower(s->irq); 217 qemu_irq_lower(s->irq);
@@ -344,6 +360,7 @@ static void iommu_reset(void *opaque) @@ -344,6 +360,7 @@ static void iommu_reset(void *opaque)
344 s->regs[IOMMU_CTRL] = s->version; 360 s->regs[IOMMU_CTRL] = s->version;
345 s->regs[IOMMU_ARBEN] = IOMMU_MID; 361 s->regs[IOMMU_ARBEN] = IOMMU_MID;
346 s->regs[IOMMU_AFSR] = IOMMU_AFSR_RESV; 362 s->regs[IOMMU_AFSR] = IOMMU_AFSR_RESV;
  363 + s->regs[IOMMU_AER] = IOMMU_AER_EN_P0_ARB | IOMMU_AER_EN_P1_ARB;
347 s->regs[IOMMU_MASK_ID] = IOMMU_TS_MASK; 364 s->regs[IOMMU_MASK_ID] = IOMMU_TS_MASK;
348 qemu_irq_lower(s->irq); 365 qemu_irq_lower(s->irq);
349 } 366 }