Commit 7ac256b8725304aabae78bf012c25b6416509c46
1 parent
d8871c5a
Fix gdb stub for MIPS64.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3435 c046a42c-6fe2-441c-8c8c-71466251a162
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1 changed file
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28 additions
and
11 deletions
gdbstub.c
| ... | ... | @@ -563,7 +563,7 @@ static int cpu_gdb_read_registers(CPUState *env, uint8_t *mem_buf) |
| 563 | 563 | ptr += sizeof(target_ulong); |
| 564 | 564 | } |
| 565 | 565 | |
| 566 | - *(target_ulong *)ptr = tswapl(env->CP0_Status); | |
| 566 | + *(target_ulong *)ptr = (int32_t)tswap32(env->CP0_Status); | |
| 567 | 567 | ptr += sizeof(target_ulong); |
| 568 | 568 | |
| 569 | 569 | *(target_ulong *)ptr = tswapl(env->LO[0][env->current_tc]); |
| ... | ... | @@ -575,7 +575,7 @@ static int cpu_gdb_read_registers(CPUState *env, uint8_t *mem_buf) |
| 575 | 575 | *(target_ulong *)ptr = tswapl(env->CP0_BadVAddr); |
| 576 | 576 | ptr += sizeof(target_ulong); |
| 577 | 577 | |
| 578 | - *(target_ulong *)ptr = tswapl(env->CP0_Cause); | |
| 578 | + *(target_ulong *)ptr = (int32_t)tswap32(env->CP0_Cause); | |
| 579 | 579 | ptr += sizeof(target_ulong); |
| 580 | 580 | |
| 581 | 581 | *(target_ulong *)ptr = tswapl(env->PC[env->current_tc]); |
| ... | ... | @@ -585,19 +585,34 @@ static int cpu_gdb_read_registers(CPUState *env, uint8_t *mem_buf) |
| 585 | 585 | { |
| 586 | 586 | for (i = 0; i < 32; i++) |
| 587 | 587 | { |
| 588 | - *(target_ulong *)ptr = tswapl(env->fpu->fpr[i].fs[FP_ENDIAN_IDX]); | |
| 588 | + if (env->CP0_Status & (1 << CP0St_FR)) | |
| 589 | + *(target_ulong *)ptr = tswapl(env->fpu->fpr[i].d); | |
| 590 | + else | |
| 591 | + *(target_ulong *)ptr = tswap32(env->fpu->fpr[i].w[FP_ENDIAN_IDX]); | |
| 589 | 592 | ptr += sizeof(target_ulong); |
| 590 | 593 | } |
| 591 | 594 | |
| 592 | - *(target_ulong *)ptr = tswapl(env->fpu->fcr31); | |
| 595 | + *(target_ulong *)ptr = (int32_t)tswap32(env->fpu->fcr31); | |
| 593 | 596 | ptr += sizeof(target_ulong); |
| 594 | 597 | |
| 595 | - *(target_ulong *)ptr = tswapl(env->fpu->fcr0); | |
| 598 | + *(target_ulong *)ptr = (int32_t)tswap32(env->fpu->fcr0); | |
| 596 | 599 | ptr += sizeof(target_ulong); |
| 597 | 600 | } |
| 598 | 601 | |
| 599 | - /* 32 FP registers, fsr, fir, fp. Not yet implemented. */ | |
| 600 | - /* what's 'fp' mean here? */ | |
| 602 | + /* "fp", pseudo frame pointer. Not yet implemented in gdb. */ | |
| 603 | + *(target_ulong *)ptr = 0; | |
| 604 | + ptr += sizeof(target_ulong); | |
| 605 | + | |
| 606 | + /* Registers for embedded use, we just pad them. */ | |
| 607 | + for (i = 0; i < 16; i++) | |
| 608 | + { | |
| 609 | + *(target_ulong *)ptr = 0; | |
| 610 | + ptr += sizeof(target_ulong); | |
| 611 | + } | |
| 612 | + | |
| 613 | + /* Processor ID. */ | |
| 614 | + *(target_ulong *)ptr = (int32_t)tswap32(env->CP0_PRid); | |
| 615 | + ptr += sizeof(target_ulong); | |
| 601 | 616 | |
| 602 | 617 | return ptr - mem_buf; |
| 603 | 618 | } |
| ... | ... | @@ -647,15 +662,17 @@ static void cpu_gdb_write_registers(CPUState *env, uint8_t *mem_buf, int size) |
| 647 | 662 | { |
| 648 | 663 | for (i = 0; i < 32; i++) |
| 649 | 664 | { |
| 650 | - env->fpu->fpr[i].fs[FP_ENDIAN_IDX] = tswapl(*(target_ulong *)ptr); | |
| 665 | + if (env->CP0_Status & (1 << CP0St_FR)) | |
| 666 | + env->fpu->fpr[i].d = tswapl(*(target_ulong *)ptr); | |
| 667 | + else | |
| 668 | + env->fpu->fpr[i].w[FP_ENDIAN_IDX] = tswapl(*(target_ulong *)ptr); | |
| 651 | 669 | ptr += sizeof(target_ulong); |
| 652 | 670 | } |
| 653 | 671 | |
| 654 | - env->fpu->fcr31 = tswapl(*(target_ulong *)ptr) & 0x0183FFFF; | |
| 672 | + env->fpu->fcr31 = tswapl(*(target_ulong *)ptr) & 0xFF83FFFF; | |
| 655 | 673 | ptr += sizeof(target_ulong); |
| 656 | 674 | |
| 657 | - env->fpu->fcr0 = tswapl(*(target_ulong *)ptr); | |
| 658 | - ptr += sizeof(target_ulong); | |
| 675 | + /* The remaining registers are assumed to be read-only. */ | |
| 659 | 676 | |
| 660 | 677 | /* set rounding mode */ |
| 661 | 678 | RESTORE_ROUNDING_MODE; | ... | ... |