Commit 7a9b96cf2165357c4ddc58c37395431adc1f3050
1 parent
a9c11522
target-ppc: add Altivec logical operations
Use opc2/opc3 instead of one big xo field. Do this consistency with the rest of translate.c Signed-off-by: Nathan Froyd <froydnj@codesourcery.com> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net> git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6087 c046a42c-6fe2-441c-8c8c-71466251a162
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target-ppc/translate.c
| @@ -6139,6 +6139,24 @@ GEN_VR_STX(svx, 0x07, 0x07); | @@ -6139,6 +6139,24 @@ GEN_VR_STX(svx, 0x07, 0x07); | ||
| 6139 | /* As we don't emulate the cache, stvxl is stricly equivalent to stvx */ | 6139 | /* As we don't emulate the cache, stvxl is stricly equivalent to stvx */ |
| 6140 | GEN_VR_STX(svxl, 0x07, 0x0F); | 6140 | GEN_VR_STX(svxl, 0x07, 0x0F); |
| 6141 | 6141 | ||
| 6142 | +/* Logical operations */ | ||
| 6143 | +#define GEN_VX_LOGICAL(name, tcg_op, opc2, opc3) \ | ||
| 6144 | +GEN_HANDLER(name, 0x04, opc2, opc3, 0x00000000, PPC_ALTIVEC) \ | ||
| 6145 | +{ \ | ||
| 6146 | + if (unlikely(!ctx->altivec_enabled)) { \ | ||
| 6147 | + gen_exception(ctx, POWERPC_EXCP_VPU); \ | ||
| 6148 | + return; \ | ||
| 6149 | + } \ | ||
| 6150 | + tcg_op(cpu_avrh[rD(ctx->opcode)], cpu_avrh[rA(ctx->opcode)], cpu_avrh[rB(ctx->opcode)]); \ | ||
| 6151 | + tcg_op(cpu_avrl[rD(ctx->opcode)], cpu_avrl[rA(ctx->opcode)], cpu_avrl[rB(ctx->opcode)]); \ | ||
| 6152 | +} | ||
| 6153 | + | ||
| 6154 | +GEN_VX_LOGICAL(vand, tcg_gen_and_i64, 2, 16); | ||
| 6155 | +GEN_VX_LOGICAL(vandc, tcg_gen_andc_i64, 2, 17); | ||
| 6156 | +GEN_VX_LOGICAL(vor, tcg_gen_or_i64, 2, 18); | ||
| 6157 | +GEN_VX_LOGICAL(vxor, tcg_gen_xor_i64, 2, 19); | ||
| 6158 | +GEN_VX_LOGICAL(vnor, tcg_gen_nor_i64, 2, 20); | ||
| 6159 | + | ||
| 6142 | /*** SPE extension ***/ | 6160 | /*** SPE extension ***/ |
| 6143 | /* Register moves */ | 6161 | /* Register moves */ |
| 6144 | 6162 |