gwj / at91sam9263 · Commits

Commit 7a962d3087d24fa0ea377cbde39ab97f81457ff6

Authored by bellard
1 parent e1d9a508

use MIPS_TLB_NB constant (Ralf Baechle) 


git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@1479 c046a42c-6fe2-441c-8c8c-71466251a162
Inline Side-by-side
Showing 2 changed files with 8 additions and 6 deletions
target-mips/helper.c
  View file @7a962d3
... ... @@ -33,7 +33,7 @@ static int map_address (CPUState *env, target_ulong *physical, int *prot,
33 33 ret = -2;
34 34 tag = (address & 0xFFFFE000);
35 35 ASID = env->CP0_EntryHi & 0x000000FF;
36   - for (i = 0; i < 16; i++) {
  36 + for (i = 0; i < MIPS_TLB_NB; i++) {
37 37 tlb = &env->tlb[i];
38 38 /* Check ASID, virtual page number & size */
39 39 if ((tlb->G == 1 || tlb->ASID == ASID) &&
... ...
target-mips/op_helper.c
  View file @7a962d3
... ... @@ -531,8 +531,10 @@ static void fill_tb (int idx)
531 531  
532 532 void do_tlbwi (void)
533 533 {
534   - invalidate_tb(env->CP0_index & 0xF);
535   - fill_tb(env->CP0_index & 0xF);
  534 + /* Wildly undefined effects for CP0_index containing a too high value and
  535 + MIPS_TLB_NB not being a power of two. But so does real silicon. */
  536 + invalidate_tb(env->CP0_index & (MIPS_TLB_NB - 1));
  537 + fill_tb(env->CP0_index & (MIPS_TLB_NB - 1));
536 538 }
537 539  
538 540 void do_tlbwr (void)
... ... @@ -552,7 +554,7 @@ void do_tlbp (void)
552 554  
553 555 tag = (env->CP0_EntryHi & 0xFFFFE000);
554 556 ASID = env->CP0_EntryHi & 0x000000FF;
555   - for (i = 0; i < 16; i++) {
  557 + for (i = 0; i < MIPS_TLB_NB; i++) {
556 558 tlb = &env->tlb[i];
557 559 /* Check ASID, virtual page number & size */
558 560 if ((tlb->G == 1 || tlb->ASID == ASID) && tlb->VPN == tag) {
... ... @@ -561,7 +563,7 @@ void do_tlbp (void)
561 563 break;
562 564 }
563 565 }
564   - if (i == 16) {
  566 + if (i == MIPS_TLB_NB) {
565 567 env->CP0_index |= 0x80000000;
566 568 }
567 569 }
... ... @@ -571,7 +573,7 @@ void do_tlbr (void)
571 573 tlb_t *tlb;
572 574 int size;
573 575  
574   - tlb = &env->tlb[env->CP0_index & 0xF];
  576 + tlb = &env->tlb[env->CP0_index & (MIPS_TLB_NB - 1)];
575 577 env->CP0_EntryHi = tlb->VPN | tlb->ASID;
576 578 size = (tlb->end - tlb->VPN) >> 12;
577 579 env->CP0_PageMask = (size - 1) << 13;
... ...