gwj / at91sam9263 · Commits

Commit 7997d92f2c75cf56e8142be8e4c1fb5b8dbcc2a4

Authored by balrog
1 parent 22478e79

ARM: fix CPS masks (Vincent Palatin). 

According to ARM Reference Manual (DDI0100 A4.1.16),
bit 5 is fixed to 0 (bit 4 is the MSB of the mode), so the instruction mask
should be  0x0ff10020 not 0x0ff10010.
Besides, mmod flag is bit 17 (b14 is SBZ)


git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4899 c046a42c-6fe2-441c-8c8c-71466251a162
Inline Side-by-side
Showing 1 changed file with 2 additions and 2 deletions
target-arm/translate.c
  View file @7997d92
... ... @@ -5813,7 +5813,7 @@ static void disas_arm_insn(CPUState * env, DisasContext *s)
5813 5813 /* Coprocessor double register transfer. */
5814 5814 } else if ((insn & 0x0f000010) == 0x0e000010) {
5815 5815 /* Additional coprocessor register transfer. */
5816   - } else if ((insn & 0x0ff10010) == 0x01000000) {
  5816 + } else if ((insn & 0x0ff10020) == 0x01000000) {
5817 5817 uint32_t mask;
5818 5818 uint32_t val;
5819 5819 /* cps (privileged) */
... ... @@ -5830,7 +5830,7 @@ static void disas_arm_insn(CPUState * env, DisasContext *s)
5830 5830 if (insn & (1 << 18))
5831 5831 val |= mask;
5832 5832 }
5833   - if (insn & (1 << 14)) {
  5833 + if (insn & (1 << 17)) {
5834 5834 mask |= CPSR_M;
5835 5835 val |= (insn & 0x1f);
5836 5836 }
... ...