gwj / at91sam9263 · Commits

Commit 785f451b62c8008428343d84549d175cd4f9d099

Authored by aurel32
1 parent 8142cddd

target-ppc: Add m{f,t}vscr instructions. 

Based on a patch by Nathan Froyd <froydnj@codesourcery.com>

Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6190 c046a42c-6fe2-441c-8c8c-71466251a162
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Showing 1 changed file with 27 additions and 0 deletions
target-ppc/translate.c
  View file @785f451
... ... @@ -6228,6 +6228,33 @@ GEN_HANDLER(lvsr, 0x1f, 0x06, 0x01, 0x00000001, PPC_ALTIVEC)
6228 6228 tcg_temp_free_ptr(rd);
6229 6229 }
6230 6230  
  6231 +GEN_HANDLER(mfvscr, 0x04, 0x2, 0x18, 0x001ff800, PPC_ALTIVEC)
  6232 +{
  6233 + TCGv_i32 t;
  6234 + if (unlikely(!ctx->altivec_enabled)) {
  6235 + gen_exception(ctx, POWERPC_EXCP_VPU);
  6236 + return;
  6237 + }
  6238 + tcg_gen_movi_i64(cpu_avrh[rD(ctx->opcode)], 0);
  6239 + t = tcg_temp_new_i32();
  6240 + tcg_gen_ld_i32(t, cpu_env, offsetof(CPUState, vscr));
  6241 + tcg_gen_extu_i32_i64(cpu_avrl[rD(ctx->opcode)], t);
  6242 + tcg_temp_free(t);
  6243 +}
  6244 +
  6245 +GEN_HANDLER(mtvscr, 0x04, 0x2, 0x19, 0x03ff0000, PPC_ALTIVEC)
  6246 +{
  6247 + TCGv_i32 t;
  6248 + if (unlikely(!ctx->altivec_enabled)) {
  6249 + gen_exception(ctx, POWERPC_EXCP_VPU);
  6250 + return;
  6251 + }
  6252 + t = tcg_temp_new_i32();
  6253 + tcg_gen_trunc_i64_i32(t, cpu_avrl[rD(ctx->opcode)]);
  6254 + tcg_gen_st_i32(t, cpu_env, offsetof(CPUState, vscr));
  6255 + tcg_temp_free_i32(t);
  6256 +}
  6257 +
6231 6258 /* Logical operations */
6232 6259 #define GEN_VX_LOGICAL(name, tcg_op, opc2, opc3) \
6233 6260 GEN_HANDLER(name, 0x04, opc2, opc3, 0x00000000, PPC_ALTIVEC) \
... ...