gwj / at91sam9263 · Commits

Commit 78556820a4ef3f507ec7c26a86d5ac3889d93d1f

Authored by edgar_igl
1 parent ca896ef3

CFI-0002 linux MTD compatibility. 

* Add an extended table area.
* Clear buffer write timeouts to indicate that we dont support it.
* Correct device size.


git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4387 c046a42c-6fe2-441c-8c8c-71466251a162
Inline Side-by-side
Showing 1 changed file with 25 additions and 7 deletions
hw/pflash_cfi02.c
  View file @7855682
... ... @@ -608,8 +608,8 @@ pflash_t *pflash_cfi02_register(target_phys_addr_t base, ram_addr_t off,
608 608 /* Command set (AMD/Fujitsu) */
609 609 pfl->cfi_table[0x13] = 0x02;
610 610 pfl->cfi_table[0x14] = 0x00;
611   - /* Primary extended table address (none) */
612   - pfl->cfi_table[0x15] = 0x00;
  611 + /* Primary extended table address */
  612 + pfl->cfi_table[0x15] = 0x31;
613 613 pfl->cfi_table[0x16] = 0x00;
614 614 /* Alternate command set (none) */
615 615 pfl->cfi_table[0x17] = 0x00;
... ... @@ -627,22 +627,22 @@ pflash_t *pflash_cfi02_register(target_phys_addr_t base, ram_addr_t off,
627 627 pfl->cfi_table[0x1E] = 0x00;
628 628 /* Reserved */
629 629 pfl->cfi_table[0x1F] = 0x07;
630   - /* Timeout for min size buffer write (16 µs) */
631   - pfl->cfi_table[0x20] = 0x04;
  630 + /* Timeout for min size buffer write (NA) */
  631 + pfl->cfi_table[0x20] = 0x00;
632 632 /* Typical timeout for block erase (512 ms) */
633 633 pfl->cfi_table[0x21] = 0x09;
634 634 /* Typical timeout for full chip erase (4096 ms) */
635 635 pfl->cfi_table[0x22] = 0x0C;
636 636 /* Reserved */
637 637 pfl->cfi_table[0x23] = 0x01;
638   - /* Max timeout for buffer write */
639   - pfl->cfi_table[0x24] = 0x04;
  638 + /* Max timeout for buffer write (NA) */
  639 + pfl->cfi_table[0x24] = 0x00;
640 640 /* Max timeout for block erase */
641 641 pfl->cfi_table[0x25] = 0x0A;
642 642 /* Max timeout for chip erase */
643 643 pfl->cfi_table[0x26] = 0x0D;
644 644 /* Device size */
645   - pfl->cfi_table[0x27] = ctz32(chip_len) + 1;
  645 + pfl->cfi_table[0x27] = ctz32(chip_len);
646 646 /* Flash device interface (8 & 16 bits) */
647 647 pfl->cfi_table[0x28] = 0x02;
648 648 pfl->cfi_table[0x29] = 0x00;
... ... @@ -659,5 +659,23 @@ pflash_t *pflash_cfi02_register(target_phys_addr_t base, ram_addr_t off,
659 659 pfl->cfi_table[0x2F] = sector_len >> 8;
660 660 pfl->cfi_table[0x30] = sector_len >> 16;
661 661  
  662 + /* Extended */
  663 + pfl->cfi_table[0x31] = 'P';
  664 + pfl->cfi_table[0x32] = 'R';
  665 + pfl->cfi_table[0x33] = 'I';
  666 +
  667 + pfl->cfi_table[0x34] = '1';
  668 + pfl->cfi_table[0x35] = '0';
  669 +
  670 + pfl->cfi_table[0x36] = 0x00;
  671 + pfl->cfi_table[0x37] = 0x00;
  672 + pfl->cfi_table[0x38] = 0x00;
  673 + pfl->cfi_table[0x39] = 0x00;
  674 +
  675 + pfl->cfi_table[0x3a] = 0x00;
  676 +
  677 + pfl->cfi_table[0x3b] = 0x00;
  678 + pfl->cfi_table[0x3c] = 0x00;
  679 +
662 680 return pfl;
663 681 }
... ...