gwj / at91sam9263 · Commits

Commit 76db3ba44ee8db671f804755f13b016eefd13288

Authored by aurel32
1 parent 8bba3ea1

target-ppc: memory load/store rework 

Rework the memory load/store:
- Unify load/store functions for 32-bit and 64-bit CPU
- Don't swap values twice for bit-reverse load/store functions
  in little endian mode.
- On a 64-bit CPU in 32-bit mode, do the address truncation for
  address computation instead of every load store. Truncate the
  address when incrementing the address (if needed)
- Cache writes to access_types.
- Add a few missing calls to gen_set_access_type()

Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5949 c046a42c-6fe2-441c-8c8c-71466251a162
Inline Side-by-side
Showing 2 changed files with 684 additions and 678 deletions
target-ppc/op_helper.c
  View file @76db3ba
@@ -257,47 +257,51 @@ void helper_store_601_batu (uint32_t nr, target_ulong val) @@ -257,47 +257,51 @@ void helper_store_601_batu (uint32_t nr, target_ulong val)
257 /*****************************************************************************/ 257 /*****************************************************************************/
258 /* Memory load and stores */ 258 /* Memory load and stores */
259 259
260 -static always_inline target_ulong get_addr(target_ulong addr) 260 +static always_inline target_ulong addr_add(target_ulong addr, target_long arg)
261 { 261 {
262 #if defined(TARGET_PPC64) 262 #if defined(TARGET_PPC64)
263 - if (msr_sf)  
264 - return addr; 263 + if (!msr_sf)
  264 + return (uint32_t)(addr + arg);
265 else 265 else
266 #endif 266 #endif
267 - return (uint32_t)addr; 267 + return addr + arg;
268 } 268 }
269 269
270 void helper_lmw (target_ulong addr, uint32_t reg) 270 void helper_lmw (target_ulong addr, uint32_t reg)
271 { 271 {
272 - for (; reg < 32; reg++, addr += 4) { 272 + for (; reg < 32; reg++) {
273 if (msr_le) 273 if (msr_le)
274 - env->gpr[reg] = bswap32(ldl(get_addr(addr))); 274 + env->gpr[reg] = bswap32(ldl(addr));
275 else 275 else
276 - env->gpr[reg] = ldl(get_addr(addr)); 276 + env->gpr[reg] = ldl(addr);
  277 + addr = addr_add(addr, 4);
277 } 278 }
278 } 279 }
279 280
280 void helper_stmw (target_ulong addr, uint32_t reg) 281 void helper_stmw (target_ulong addr, uint32_t reg)
281 { 282 {
282 - for (; reg < 32; reg++, addr += 4) { 283 + for (; reg < 32; reg++) {
283 if (msr_le) 284 if (msr_le)
284 - stl(get_addr(addr), bswap32((uint32_t)env->gpr[reg])); 285 + stl(addr, bswap32((uint32_t)env->gpr[reg]));
285 else 286 else
286 - stl(get_addr(addr), (uint32_t)env->gpr[reg]); 287 + stl(addr, (uint32_t)env->gpr[reg]);
  288 + addr = addr_add(addr, 4);
287 } 289 }
288 } 290 }
289 291
290 void helper_lsw(target_ulong addr, uint32_t nb, uint32_t reg) 292 void helper_lsw(target_ulong addr, uint32_t nb, uint32_t reg)
291 { 293 {
292 int sh; 294 int sh;
293 - for (; nb > 3; nb -= 4, addr += 4) {  
294 - env->gpr[reg] = ldl(get_addr(addr)); 295 + for (; nb > 3; nb -= 4) {
  296 + env->gpr[reg] = ldl(addr);
295 reg = (reg + 1) % 32; 297 reg = (reg + 1) % 32;
  298 + addr = addr_add(addr, 4);
296 } 299 }
297 if (unlikely(nb > 0)) { 300 if (unlikely(nb > 0)) {
298 env->gpr[reg] = 0; 301 env->gpr[reg] = 0;
299 - for (sh = 24; nb > 0; nb--, addr++, sh -= 8) {  
300 - env->gpr[reg] |= ldub(get_addr(addr)) << sh; 302 + for (sh = 24; nb > 0; nb--, sh -= 8) {
  303 + env->gpr[reg] |= ldub(addr) << sh;
  304 + addr = addr_add(addr, 1);
301 } 305 }
302 } 306 }
303 } 307 }
@@ -323,25 +327,26 @@ void helper_lswx(target_ulong addr, uint32_t reg, uint32_t ra, uint32_t rb) @@ -323,25 +327,26 @@ void helper_lswx(target_ulong addr, uint32_t reg, uint32_t ra, uint32_t rb)
323 void helper_stsw(target_ulong addr, uint32_t nb, uint32_t reg) 327 void helper_stsw(target_ulong addr, uint32_t nb, uint32_t reg)
324 { 328 {
325 int sh; 329 int sh;
326 - for (; nb > 3; nb -= 4, addr += 4) {  
327 - stl(get_addr(addr), env->gpr[reg]); 330 + for (; nb > 3; nb -= 4) {
  331 + stl(addr, env->gpr[reg]);
328 reg = (reg + 1) % 32; 332 reg = (reg + 1) % 32;
  333 + addr = addr_add(addr, 4);
329 } 334 }
330 if (unlikely(nb > 0)) { 335 if (unlikely(nb > 0)) {
331 - for (sh = 24; nb > 0; nb--, addr++, sh -= 8)  
332 - stb(get_addr(addr), (env->gpr[reg] >> sh) & 0xFF); 336 + for (sh = 24; nb > 0; nb--, sh -= 8)
  337 + stb(addr, (env->gpr[reg] >> sh) & 0xFF);
  338 + addr = addr_add(addr, 1);
333 } 339 }
334 } 340 }
335 341
336 static void do_dcbz(target_ulong addr, int dcache_line_size) 342 static void do_dcbz(target_ulong addr, int dcache_line_size)
337 { 343 {
338 - target_long mask = get_addr(~(dcache_line_size - 1)); 344 + addr &= ~(dcache_line_size - 1);
339 int i; 345 int i;
340 - addr &= mask;  
341 for (i = 0 ; i < dcache_line_size ; i += 4) { 346 for (i = 0 ; i < dcache_line_size ; i += 4) {
342 stl(addr + i , 0); 347 stl(addr + i , 0);
343 } 348 }
344 - if ((env->reserve & mask) == addr) 349 + if (env->reserve == addr)
345 env->reserve = (target_ulong)-1ULL; 350 env->reserve = (target_ulong)-1ULL;
346 } 351 }
347 352
@@ -362,7 +367,7 @@ void helper_icbi(target_ulong addr) @@ -362,7 +367,7 @@ void helper_icbi(target_ulong addr)
362 { 367 {
363 uint32_t tmp; 368 uint32_t tmp;
364 369
365 - addr = get_addr(addr & ~(env->dcache_line_size - 1)); 370 + addr &= ~(env->dcache_line_size - 1);
366 /* Invalidate one cache line : 371 /* Invalidate one cache line :
367 * PowerPC specification says this is to be treated like a load 372 * PowerPC specification says this is to be treated like a load
368 * (not a fetch) by the MMU. To be sure it will be so, 373 * (not a fetch) by the MMU. To be sure it will be so,
@@ -378,7 +383,8 @@ target_ulong helper_lscbx (target_ulong addr, uint32_t reg, uint32_t ra, uint32_ @@ -378,7 +383,8 @@ target_ulong helper_lscbx (target_ulong addr, uint32_t reg, uint32_t ra, uint32_
378 int i, c, d; 383 int i, c, d;
379 d = 24; 384 d = 24;
380 for (i = 0; i < xer_bc; i++) { 385 for (i = 0; i < xer_bc; i++) {
381 - c = ldub((uint32_t)addr++); 386 + c = ldub(addr);
  387 + addr = addr_add(addr, 1);
382 /* ra (if not 0) and rb are never modified */ 388 /* ra (if not 0) and rb are never modified */
383 if (likely(reg != rb && (ra == 0 || reg != ra))) { 389 if (likely(reg != rb && (ra == 0 || reg != ra))) {
384 env->gpr[reg] = (env->gpr[reg] & ~(0xFF << d)) | (c << d); 390 env->gpr[reg] = (env->gpr[reg] & ~(0xFF << d)) | (c << d);
target-ppc/translate.c
  View file @76db3ba
@@ -175,10 +175,9 @@ typedef struct DisasContext { @@ -175,10 +175,9 @@ typedef struct DisasContext {
175 uint32_t exception; 175 uint32_t exception;
176 /* Routine used to access memory */ 176 /* Routine used to access memory */
177 int mem_idx; 177 int mem_idx;
  178 + int access_type;
178 /* Translation flags */ 179 /* Translation flags */
179 -#if !defined(CONFIG_USER_ONLY)  
180 - int supervisor;  
181 -#endif 180 + int le_mode;
182 #if defined(TARGET_PPC64) 181 #if defined(TARGET_PPC64)
183 int sf_mode; 182 int sf_mode;
184 #endif 183 #endif
@@ -249,9 +248,12 @@ static always_inline void gen_optimize_fprf (void) @@ -249,9 +248,12 @@ static always_inline void gen_optimize_fprf (void)
249 #endif 248 #endif
250 } 249 }
251 250
252 -static always_inline void gen_set_access_type(int access_type) 251 +static always_inline void gen_set_access_type (DisasContext *ctx, int access_type)
253 { 252 {
254 - tcg_gen_movi_i32(cpu_access_type, access_type); 253 + if (ctx->access_type != access_type) {
  254 + tcg_gen_movi_i32(cpu_access_type, access_type);
  255 + ctx->access_type = access_type;
  256 + }
255 } 257 }
256 258
257 static always_inline void gen_update_nip (DisasContext *ctx, target_ulong nip) 259 static always_inline void gen_update_nip (DisasContext *ctx, target_ulong nip)
@@ -1515,25 +1517,25 @@ GEN_HANDLER(or, 0x1F, 0x1C, 0x0D, 0x00000000, PPC_INTEGER) @@ -1515,25 +1517,25 @@ GEN_HANDLER(or, 0x1F, 0x1C, 0x0D, 0x00000000, PPC_INTEGER)
1515 break; 1517 break;
1516 #if !defined(CONFIG_USER_ONLY) 1518 #if !defined(CONFIG_USER_ONLY)
1517 case 31: 1519 case 31:
1518 - if (ctx->supervisor > 0) { 1520 + if (ctx->mem_idx > 0) {
1519 /* Set process priority to very low */ 1521 /* Set process priority to very low */
1520 prio = 1; 1522 prio = 1;
1521 } 1523 }
1522 break; 1524 break;
1523 case 5: 1525 case 5:
1524 - if (ctx->supervisor > 0) { 1526 + if (ctx->mem_idx > 0) {
1525 /* Set process priority to medium-hight */ 1527 /* Set process priority to medium-hight */
1526 prio = 5; 1528 prio = 5;
1527 } 1529 }
1528 break; 1530 break;
1529 case 3: 1531 case 3:
1530 - if (ctx->supervisor > 0) { 1532 + if (ctx->mem_idx > 0) {
1531 /* Set process priority to high */ 1533 /* Set process priority to high */
1532 prio = 6; 1534 prio = 6;
1533 } 1535 }
1534 break; 1536 break;
1535 case 7: 1537 case 7:
1536 - if (ctx->supervisor > 1) { 1538 + if (ctx->mem_idx > 1) {
1537 /* Set process priority to very high */ 1539 /* Set process priority to very high */
1538 prio = 7; 1540 prio = 7;
1539 } 1541 }
@@ -2434,37 +2436,76 @@ GEN_HANDLER(mtfsfi, 0x3F, 0x06, 0x04, 0x006f0800, PPC_FLOAT) @@ -2434,37 +2436,76 @@ GEN_HANDLER(mtfsfi, 0x3F, 0x06, 0x04, 0x006f0800, PPC_FLOAT)
2434 2436
2435 /*** Addressing modes ***/ 2437 /*** Addressing modes ***/
2436 /* Register indirect with immediate index : EA = (rA|0) + SIMM */ 2438 /* Register indirect with immediate index : EA = (rA|0) + SIMM */
2437 -static always_inline void gen_addr_imm_index (TCGv EA,  
2438 - DisasContext *ctx,  
2439 - target_long maskl) 2439 +static always_inline void gen_addr_imm_index (DisasContext *ctx, TCGv EA, target_long maskl)
2440 { 2440 {
2441 target_long simm = SIMM(ctx->opcode); 2441 target_long simm = SIMM(ctx->opcode);
2442 2442
2443 simm &= ~maskl; 2443 simm &= ~maskl;
2444 - if (rA(ctx->opcode) == 0) 2444 + if (rA(ctx->opcode) == 0) {
  2445 +#if defined(TARGET_PPC64)
  2446 + if (!ctx->sf_mode) {
  2447 + tcg_gen_movi_tl(EA, (uint32_t)simm);
  2448 + } else
  2449 +#endif
2445 tcg_gen_movi_tl(EA, simm); 2450 tcg_gen_movi_tl(EA, simm);
2446 - else if (likely(simm != 0)) 2451 + } else if (likely(simm != 0)) {
2447 tcg_gen_addi_tl(EA, cpu_gpr[rA(ctx->opcode)], simm); 2452 tcg_gen_addi_tl(EA, cpu_gpr[rA(ctx->opcode)], simm);
2448 - else 2453 +#if defined(TARGET_PPC64)
  2454 + if (!ctx->sf_mode) {
  2455 + tcg_gen_ext32u_tl(EA, EA);
  2456 + }
  2457 +#endif
  2458 + } else {
  2459 +#if defined(TARGET_PPC64)
  2460 + if (!ctx->sf_mode) {
  2461 + tcg_gen_ext32u_tl(EA, cpu_gpr[rA(ctx->opcode)]);
  2462 + } else
  2463 +#endif
2449 tcg_gen_mov_tl(EA, cpu_gpr[rA(ctx->opcode)]); 2464 tcg_gen_mov_tl(EA, cpu_gpr[rA(ctx->opcode)]);
  2465 + }
2450 } 2466 }
2451 2467
2452 -static always_inline void gen_addr_reg_index (TCGv EA,  
2453 - DisasContext *ctx) 2468 +static always_inline void gen_addr_reg_index (DisasContext *ctx, TCGv EA)
2454 { 2469 {
2455 - if (rA(ctx->opcode) == 0) 2470 + if (rA(ctx->opcode) == 0) {
  2471 +#if defined(TARGET_PPC64)
  2472 + if (!ctx->sf_mode) {
  2473 + tcg_gen_ext32u_tl(EA, cpu_gpr[rB(ctx->opcode)]);
  2474 + } else
  2475 +#endif
2456 tcg_gen_mov_tl(EA, cpu_gpr[rB(ctx->opcode)]); 2476 tcg_gen_mov_tl(EA, cpu_gpr[rB(ctx->opcode)]);
2457 - else 2477 + } else {
2458 tcg_gen_add_tl(EA, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); 2478 tcg_gen_add_tl(EA, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
  2479 +#if defined(TARGET_PPC64)
  2480 + if (!ctx->sf_mode) {
  2481 + tcg_gen_ext32u_tl(EA, EA);
  2482 + }
  2483 +#endif
  2484 + }
2459 } 2485 }
2460 2486
2461 -static always_inline void gen_addr_register (TCGv EA,  
2462 - DisasContext *ctx) 2487 +static always_inline void gen_addr_register (DisasContext *ctx, TCGv EA)
2463 { 2488 {
2464 - if (rA(ctx->opcode) == 0) 2489 + if (rA(ctx->opcode) == 0) {
2465 tcg_gen_movi_tl(EA, 0); 2490 tcg_gen_movi_tl(EA, 0);
2466 - else  
2467 - tcg_gen_mov_tl(EA, cpu_gpr[rA(ctx->opcode)]); 2491 + } else {
  2492 +#if defined(TARGET_PPC64)
  2493 + if (!ctx->sf_mode) {
  2494 + tcg_gen_ext32u_tl(EA, cpu_gpr[rA(ctx->opcode)]);
  2495 + } else
  2496 +#endif
  2497 + tcg_gen_mov_tl(EA, cpu_gpr[rA(ctx->opcode)]);
  2498 + }
  2499 +}
  2500 +
  2501 +static always_inline void gen_addr_add (DisasContext *ctx, TCGv ret, TCGv arg1, target_long val)
  2502 +{
  2503 + tcg_gen_addi_tl(ret, arg1, val);
  2504 +#if defined(TARGET_PPC64)
  2505 + if (!ctx->sf_mode) {
  2506 + tcg_gen_ext32u_tl(ret, ret);
  2507 + }
  2508 +#endif
2468 } 2509 }
2469 2510
2470 static always_inline void gen_check_align (DisasContext *ctx, TCGv EA, int mask) 2511 static always_inline void gen_check_align (DisasContext *ctx, TCGv EA, int mask)
@@ -2486,288 +2527,170 @@ static always_inline void gen_check_align (DisasContext *ctx, TCGv EA, int mask) @@ -2486,288 +2527,170 @@ static always_inline void gen_check_align (DisasContext *ctx, TCGv EA, int mask)
2486 } 2527 }
2487 2528
2488 /*** Integer load ***/ 2529 /*** Integer load ***/
  2530 +static always_inline void gen_qemu_ld8u(DisasContext *ctx, TCGv arg1, TCGv arg2)
  2531 +{
  2532 + tcg_gen_qemu_ld8u(arg1, arg2, ctx->mem_idx);
  2533 +}
  2534 +
  2535 +static always_inline void gen_qemu_ld8s(DisasContext *ctx, TCGv arg1, TCGv arg2)
  2536 +{
  2537 + tcg_gen_qemu_ld8s(arg1, arg2, ctx->mem_idx);
  2538 +}
  2539 +
  2540 +static always_inline void gen_qemu_ld16u(DisasContext *ctx, TCGv arg1, TCGv arg2)
  2541 +{
  2542 + tcg_gen_qemu_ld16u(arg1, arg2, ctx->mem_idx);
  2543 + if (unlikely(ctx->le_mode)) {
2489 #if defined(TARGET_PPC64) 2544 #if defined(TARGET_PPC64)
2490 -#define GEN_QEMU_LD_PPC64(width) \  
2491 -static always_inline void gen_qemu_ld##width##_ppc64(TCGv t0, TCGv t1, int flags)\  
2492 -{ \  
2493 - if (likely(flags & 2)) \  
2494 - tcg_gen_qemu_ld##width(t0, t1, flags >> 2); \  
2495 - else { \  
2496 - TCGv addr = tcg_temp_new(); \  
2497 - tcg_gen_ext32u_tl(addr, t1); \  
2498 - tcg_gen_qemu_ld##width(t0, addr, flags >> 2); \  
2499 - tcg_temp_free(addr); \  
2500 - } \  
2501 -}  
2502 -GEN_QEMU_LD_PPC64(8u)  
2503 -GEN_QEMU_LD_PPC64(8s)  
2504 -GEN_QEMU_LD_PPC64(16u)  
2505 -GEN_QEMU_LD_PPC64(16s)  
2506 -GEN_QEMU_LD_PPC64(32u)  
2507 -GEN_QEMU_LD_PPC64(32s)  
2508 -GEN_QEMU_LD_PPC64(64)  
2509 -  
2510 -#define GEN_QEMU_ST_PPC64(width) \  
2511 -static always_inline void gen_qemu_st##width##_ppc64(TCGv t0, TCGv t1, int flags)\  
2512 -{ \  
2513 - if (likely(flags & 2)) \  
2514 - tcg_gen_qemu_st##width(t0, t1, flags >> 2); \  
2515 - else { \  
2516 - TCGv addr = tcg_temp_new(); \  
2517 - tcg_gen_ext32u_tl(addr, t1); \  
2518 - tcg_gen_qemu_st##width(t0, addr, flags >> 2); \  
2519 - tcg_temp_free(addr); \  
2520 - } \  
2521 -}  
2522 -GEN_QEMU_ST_PPC64(8)  
2523 -GEN_QEMU_ST_PPC64(16)  
2524 -GEN_QEMU_ST_PPC64(32)  
2525 -GEN_QEMU_ST_PPC64(64)  
2526 -  
2527 -static always_inline void gen_qemu_ld8u(TCGv arg0, TCGv arg1, int flags)  
2528 -{  
2529 - gen_qemu_ld8u_ppc64(arg0, arg1, flags);  
2530 -}  
2531 -  
2532 -static always_inline void gen_qemu_ld8s(TCGv arg0, TCGv arg1, int flags)  
2533 -{  
2534 - gen_qemu_ld8s_ppc64(arg0, arg1, flags);  
2535 -}  
2536 -  
2537 -static always_inline void gen_qemu_ld16u(TCGv arg0, TCGv arg1, int flags)  
2538 -{  
2539 - if (unlikely(flags & 1)) {  
2540 - TCGv_i32 t0;  
2541 - gen_qemu_ld16u_ppc64(arg0, arg1, flags);  
2542 - t0 = tcg_temp_new_i32();  
2543 - tcg_gen_trunc_tl_i32(t0, arg0); 2545 + TCGv_i32 t0 = tcg_temp_new_i32();
  2546 + tcg_gen_trunc_tl_i32(t0, arg1);
2544 tcg_gen_bswap16_i32(t0, t0); 2547 tcg_gen_bswap16_i32(t0, t0);
2545 - tcg_gen_extu_i32_tl(arg0, t0); 2548 + tcg_gen_extu_i32_tl(arg1, t0);
2546 tcg_temp_free_i32(t0); 2549 tcg_temp_free_i32(t0);
2547 - } else  
2548 - gen_qemu_ld16u_ppc64(arg0, arg1, flags); 2550 +#else
  2551 + tcg_gen_bswap16_i32(arg1, arg1);
  2552 +#endif
  2553 + }
2549 } 2554 }
2550 2555
2551 -static always_inline void gen_qemu_ld16s(TCGv arg0, TCGv arg1, int flags) 2556 +static always_inline void gen_qemu_ld16s(DisasContext *ctx, TCGv arg1, TCGv arg2)
2552 { 2557 {
2553 - if (unlikely(flags & 1)) { 2558 + if (unlikely(ctx->le_mode)) {
  2559 +#if defined(TARGET_PPC64)
2554 TCGv_i32 t0; 2560 TCGv_i32 t0;
2555 - gen_qemu_ld16u_ppc64(arg0, arg1, flags); 2561 + tcg_gen_qemu_ld16u(arg1, arg2, ctx->mem_idx);
2556 t0 = tcg_temp_new_i32(); 2562 t0 = tcg_temp_new_i32();
2557 - tcg_gen_trunc_tl_i32(t0, arg0); 2563 + tcg_gen_trunc_tl_i32(t0, arg1);
2558 tcg_gen_bswap16_i32(t0, t0); 2564 tcg_gen_bswap16_i32(t0, t0);
2559 - tcg_gen_extu_i32_tl(arg0, t0);  
2560 - tcg_gen_ext16s_tl(arg0, arg0); 2565 + tcg_gen_extu_i32_tl(arg1, t0);
  2566 + tcg_gen_ext16s_tl(arg1, arg1);
2561 tcg_temp_free_i32(t0); 2567 tcg_temp_free_i32(t0);
2562 - } else  
2563 - gen_qemu_ld16s_ppc64(arg0, arg1, flags); 2568 +#else
  2569 + tcg_gen_qemu_ld16u(arg1, arg2, ctx->mem_idx);
  2570 + tcg_gen_bswap16_i32(arg1, arg1);
  2571 + tcg_gen_ext16s_i32(arg1, arg1);
  2572 +#endif
  2573 + } else {
  2574 + tcg_gen_qemu_ld16s(arg1, arg2, ctx->mem_idx);
  2575 + }
2564 } 2576 }
2565 2577
2566 -static always_inline void gen_qemu_ld32u(TCGv arg0, TCGv arg1, int flags) 2578 +static always_inline void gen_qemu_ld32u(DisasContext *ctx, TCGv arg1, TCGv arg2)
2567 { 2579 {
2568 - if (unlikely(flags & 1)) {  
2569 - TCGv_i32 t0;  
2570 - gen_qemu_ld32u_ppc64(arg0, arg1, flags);  
2571 - t0 = tcg_temp_new_i32();  
2572 - tcg_gen_trunc_tl_i32(t0, arg0); 2580 + tcg_gen_qemu_ld32u(arg1, arg2, ctx->mem_idx);
  2581 + if (unlikely(ctx->le_mode)) {
  2582 +#if defined(TARGET_PPC64)
  2583 + TCGv_i32 t0 = tcg_temp_new_i32();
  2584 + tcg_gen_trunc_tl_i32(t0, arg1);
2573 tcg_gen_bswap_i32(t0, t0); 2585 tcg_gen_bswap_i32(t0, t0);
2574 - tcg_gen_extu_i32_tl(arg0, t0); 2586 + tcg_gen_extu_i32_tl(arg1, t0);
2575 tcg_temp_free_i32(t0); 2587 tcg_temp_free_i32(t0);
2576 - } else  
2577 - gen_qemu_ld32u_ppc64(arg0, arg1, flags); 2588 +#else
  2589 + tcg_gen_bswap_i32(arg1, arg1);
  2590 +#endif
  2591 + }
2578 } 2592 }
2579 2593
2580 -static always_inline void gen_qemu_ld32s(TCGv arg0, TCGv arg1, int flags) 2594 +#if defined(TARGET_PPC64)
  2595 +static always_inline void gen_qemu_ld32s(DisasContext *ctx, TCGv arg1, TCGv arg2)
2581 { 2596 {
2582 - if (unlikely(flags & 1)) { 2597 + if (unlikely(ctx->mem_idx)) {
2583 TCGv_i32 t0; 2598 TCGv_i32 t0;
2584 - gen_qemu_ld32u_ppc64(arg0, arg1, flags); 2599 + tcg_gen_qemu_ld32u(arg1, arg2, ctx->mem_idx);
2585 t0 = tcg_temp_new_i32(); 2600 t0 = tcg_temp_new_i32();
2586 - tcg_gen_trunc_tl_i32(t0, arg0); 2601 + tcg_gen_trunc_tl_i32(t0, arg1);
2587 tcg_gen_bswap_i32(t0, t0); 2602 tcg_gen_bswap_i32(t0, t0);
2588 - tcg_gen_ext_i32_tl(arg0, t0); 2603 + tcg_gen_ext_i32_tl(arg1, t0);
2589 tcg_temp_free_i32(t0); 2604 tcg_temp_free_i32(t0);
2590 } else 2605 } else
2591 - gen_qemu_ld32s_ppc64(arg0, arg1, flags); 2606 + tcg_gen_qemu_ld32s(arg1, arg2, ctx->mem_idx);
2592 } 2607 }
  2608 +#endif
2593 2609
2594 -static always_inline void gen_qemu_ld64(TCGv arg0, TCGv arg1, int flags) 2610 +static always_inline void gen_qemu_ld64(DisasContext *ctx, TCGv_i64 arg1, TCGv arg2)
2595 { 2611 {
2596 - gen_qemu_ld64_ppc64(arg0, arg1, flags);  
2597 - if (unlikely(flags & 1))  
2598 - tcg_gen_bswap_i64(arg0, arg0); 2612 + tcg_gen_qemu_ld64(arg1, arg2, ctx->mem_idx);
  2613 + if (unlikely(ctx->le_mode)) {
  2614 + tcg_gen_bswap_i64(arg1, arg1);
  2615 + }
2599 } 2616 }
2600 2617
2601 -static always_inline void gen_qemu_st8(TCGv arg0, TCGv arg1, int flags) 2618 +static always_inline void gen_qemu_st8(DisasContext *ctx, TCGv arg1, TCGv arg2)
2602 { 2619 {
2603 - gen_qemu_st8_ppc64(arg0, arg1, flags); 2620 + tcg_gen_qemu_st8(arg1, arg2, ctx->mem_idx);
2604 } 2621 }
2605 2622
2606 -static always_inline void gen_qemu_st16(TCGv arg0, TCGv arg1, int flags) 2623 +static always_inline void gen_qemu_st16(DisasContext *ctx, TCGv arg1, TCGv arg2)
2607 { 2624 {
2608 - if (unlikely(flags & 1)) { 2625 + if (unlikely(ctx->le_mode)) {
  2626 +#if defined(TARGET_PPC64)
2609 TCGv_i32 t0; 2627 TCGv_i32 t0;
2610 - TCGv_i64 t1; 2628 + TCGv t1;
2611 t0 = tcg_temp_new_i32(); 2629 t0 = tcg_temp_new_i32();
2612 - tcg_gen_trunc_tl_i32(t0, arg0); 2630 + tcg_gen_trunc_tl_i32(t0, arg1);
2613 tcg_gen_ext16u_i32(t0, t0); 2631 tcg_gen_ext16u_i32(t0, t0);
2614 tcg_gen_bswap16_i32(t0, t0); 2632 tcg_gen_bswap16_i32(t0, t0);
2615 - t1 = tcg_temp_new_i64(); 2633 + t1 = tcg_temp_new();
2616 tcg_gen_extu_i32_tl(t1, t0); 2634 tcg_gen_extu_i32_tl(t1, t0);
2617 tcg_temp_free_i32(t0); 2635 tcg_temp_free_i32(t0);
2618 - gen_qemu_st16_ppc64(t1, arg1, flags);  
2619 - tcg_temp_free_i64(t1);  
2620 - } else  
2621 - gen_qemu_st16_ppc64(arg0, arg1, flags); 2636 + tcg_gen_qemu_st16(t1, arg2, ctx->mem_idx);
  2637 + tcg_temp_free(t1);
  2638 +#else
  2639 + TCGv t0 = tcg_temp_new();
  2640 + tcg_gen_ext16u_tl(t0, arg1);
  2641 + tcg_gen_bswap16_i32(t0, t0);
  2642 + tcg_gen_qemu_st16(t0, arg2, ctx->mem_idx);
  2643 + tcg_temp_free(t0);
  2644 +#endif
  2645 + } else {
  2646 + tcg_gen_qemu_st16(arg1, arg2, ctx->mem_idx);
  2647 + }
2622 } 2648 }
2623 2649
2624 -static always_inline void gen_qemu_st32(TCGv arg0, TCGv arg1, int flags) 2650 +static always_inline void gen_qemu_st32(DisasContext *ctx, TCGv arg1, TCGv arg2)
2625 { 2651 {
2626 - if (unlikely(flags & 1)) { 2652 + if (unlikely(ctx->le_mode)) {
  2653 +#if defined(TARGET_PPC64)
2627 TCGv_i32 t0; 2654 TCGv_i32 t0;
2628 - TCGv_i64 t1; 2655 + TCGv t1;
2629 t0 = tcg_temp_new_i32(); 2656 t0 = tcg_temp_new_i32();
2630 - tcg_gen_trunc_tl_i32(t0, arg0); 2657 + tcg_gen_trunc_tl_i32(t0, arg1);
2631 tcg_gen_bswap_i32(t0, t0); 2658 tcg_gen_bswap_i32(t0, t0);
2632 - t1 = tcg_temp_new_i64(); 2659 + t1 = tcg_temp_new();
2633 tcg_gen_extu_i32_tl(t1, t0); 2660 tcg_gen_extu_i32_tl(t1, t0);
2634 tcg_temp_free_i32(t0); 2661 tcg_temp_free_i32(t0);
2635 - gen_qemu_st32_ppc64(t1, arg1, flags);  
2636 - tcg_temp_free_i64(t1);  
2637 - } else  
2638 - gen_qemu_st32_ppc64(arg0, arg1, flags); 2662 + tcg_gen_qemu_st32(t1, arg2, ctx->mem_idx);
  2663 + tcg_temp_free(t1);
  2664 +#else
  2665 + TCGv t0 = tcg_temp_new_i32();
  2666 + tcg_gen_bswap_i32(t0, arg1);
  2667 + tcg_gen_qemu_st32(t0, arg2, ctx->mem_idx);
  2668 + tcg_temp_free(t0);
  2669 +#endif
  2670 + } else {
  2671 + tcg_gen_qemu_st32(arg1, arg2, ctx->mem_idx);
  2672 + }
2639 } 2673 }
2640 2674
2641 -static always_inline void gen_qemu_st64(TCGv arg0, TCGv arg1, int flags) 2675 +static always_inline void gen_qemu_st64(DisasContext *ctx, TCGv_i64 arg1, TCGv arg2)
2642 { 2676 {
2643 - if (unlikely(flags & 1)) { 2677 + if (unlikely(ctx->le_mode)) {
2644 TCGv_i64 t0 = tcg_temp_new_i64(); 2678 TCGv_i64 t0 = tcg_temp_new_i64();
2645 - tcg_gen_bswap_i64(t0, arg0);  
2646 - gen_qemu_st64_ppc64(t0, arg1, flags); 2679 + tcg_gen_bswap_i64(t0, arg1);
  2680 + tcg_gen_qemu_st64(t0, arg2, ctx->mem_idx);
2647 tcg_temp_free_i64(t0); 2681 tcg_temp_free_i64(t0);
2648 } else 2682 } else
2649 - gen_qemu_st64_ppc64(arg0, arg1, flags);  
2650 -}  
2651 -  
2652 -  
2653 -#else /* defined(TARGET_PPC64) */  
2654 -#define GEN_QEMU_LD_PPC32(width) \  
2655 -static always_inline void gen_qemu_ld##width##_ppc32(TCGv arg0, TCGv arg1, int flags) \  
2656 -{ \  
2657 - tcg_gen_qemu_ld##width(arg0, arg1, flags >> 1); \  
2658 -}  
2659 -GEN_QEMU_LD_PPC32(8u)  
2660 -GEN_QEMU_LD_PPC32(8s)  
2661 -GEN_QEMU_LD_PPC32(16u)  
2662 -GEN_QEMU_LD_PPC32(16s)  
2663 -GEN_QEMU_LD_PPC32(32u)  
2664 -GEN_QEMU_LD_PPC32(32s)  
2665 -static always_inline void gen_qemu_ld64_ppc32(TCGv_i64 arg0, TCGv arg1, int flags)  
2666 -{  
2667 - tcg_gen_qemu_ld64(arg0, arg1, flags >> 1);  
2668 -}  
2669 -  
2670 -#define GEN_QEMU_ST_PPC32(width) \  
2671 -static always_inline void gen_qemu_st##width##_ppc32(TCGv arg0, TCGv arg1, int flags) \  
2672 -{ \  
2673 - tcg_gen_qemu_st##width(arg0, arg1, flags >> 1); \  
2674 -}  
2675 -GEN_QEMU_ST_PPC32(8)  
2676 -GEN_QEMU_ST_PPC32(16)  
2677 -GEN_QEMU_ST_PPC32(32)  
2678 -static always_inline void gen_qemu_st64_ppc32(TCGv_i64 arg0, TCGv arg1, int flags)  
2679 -{  
2680 - tcg_gen_qemu_st64(arg0, arg1, flags >> 1);  
2681 -}  
2682 -  
2683 -static always_inline void gen_qemu_ld8u(TCGv arg0, TCGv arg1, int flags)  
2684 -{  
2685 - gen_qemu_ld8u_ppc32(arg0, arg1, flags >> 1);  
2686 -}  
2687 -  
2688 -static always_inline void gen_qemu_ld8s(TCGv arg0, TCGv arg1, int flags)  
2689 -{  
2690 - gen_qemu_ld8s_ppc32(arg0, arg1, flags >> 1);  
2691 -}  
2692 -  
2693 -static always_inline void gen_qemu_ld16u(TCGv arg0, TCGv arg1, int flags)  
2694 -{  
2695 - gen_qemu_ld16u_ppc32(arg0, arg1, flags >> 1);  
2696 - if (unlikely(flags & 1))  
2697 - tcg_gen_bswap16_i32(arg0, arg0);  
2698 -}  
2699 -  
2700 -static always_inline void gen_qemu_ld16s(TCGv arg0, TCGv arg1, int flags)  
2701 -{  
2702 - if (unlikely(flags & 1)) {  
2703 - gen_qemu_ld16u_ppc32(arg0, arg1, flags);  
2704 - tcg_gen_bswap16_i32(arg0, arg0);  
2705 - tcg_gen_ext16s_i32(arg0, arg0);  
2706 - } else  
2707 - gen_qemu_ld16s_ppc32(arg0, arg1, flags);  
2708 -}  
2709 -  
2710 -static always_inline void gen_qemu_ld32u(TCGv arg0, TCGv arg1, int flags)  
2711 -{  
2712 - gen_qemu_ld32u_ppc32(arg0, arg1, flags);  
2713 - if (unlikely(flags & 1))  
2714 - tcg_gen_bswap_i32(arg0, arg0);  
2715 -}  
2716 -  
2717 -static always_inline void gen_qemu_ld64(TCGv_i64 arg0, TCGv arg1, int flags)  
2718 -{  
2719 - gen_qemu_ld64_ppc32(arg0, arg1, flags);  
2720 - if (unlikely(flags & 1))  
2721 - tcg_gen_bswap_i64(arg0, arg0);  
2722 -}  
2723 -  
2724 -static always_inline void gen_qemu_st8(TCGv arg0, TCGv arg1, int flags)  
2725 -{  
2726 - gen_qemu_st8_ppc32(arg0, arg1, flags);  
2727 -}  
2728 -  
2729 -static always_inline void gen_qemu_st16(TCGv arg0, TCGv arg1, int flags)  
2730 -{  
2731 - if (unlikely(flags & 1)) {  
2732 - TCGv_i32 temp = tcg_temp_new_i32();  
2733 - tcg_gen_ext16u_i32(temp, arg0);  
2734 - tcg_gen_bswap16_i32(temp, temp);  
2735 - gen_qemu_st16_ppc32(temp, arg1, flags);  
2736 - tcg_temp_free_i32(temp);  
2737 - } else  
2738 - gen_qemu_st16_ppc32(arg0, arg1, flags);  
2739 -}  
2740 -  
2741 -static always_inline void gen_qemu_st32(TCGv arg0, TCGv arg1, int flags)  
2742 -{  
2743 - if (unlikely(flags & 1)) {  
2744 - TCGv_i32 temp = tcg_temp_new_i32();  
2745 - tcg_gen_bswap_i32(temp, arg0);  
2746 - gen_qemu_st32_ppc32(temp, arg1, flags);  
2747 - tcg_temp_free_i32(temp);  
2748 - } else  
2749 - gen_qemu_st32_ppc32(arg0, arg1, flags); 2683 + tcg_gen_qemu_st64(arg1, arg2, ctx->mem_idx);
2750 } 2684 }
2751 2685
2752 -static always_inline void gen_qemu_st64(TCGv_i64 arg0, TCGv arg1, int flags)  
2753 -{  
2754 - if (unlikely(flags & 1)) {  
2755 - TCGv_i64 temp = tcg_temp_new_i64();  
2756 - tcg_gen_bswap_i64(temp, arg0);  
2757 - gen_qemu_st64_ppc32(temp, arg1, flags);  
2758 - tcg_temp_free_i64(temp);  
2759 - } else  
2760 - gen_qemu_st64_ppc32(arg0, arg1, flags);  
2761 -}  
2762 -#endif  
2763 -  
2764 #define GEN_LD(name, ldop, opc, type) \ 2686 #define GEN_LD(name, ldop, opc, type) \
2765 GEN_HANDLER(name, opc, 0xFF, 0xFF, 0x00000000, type) \ 2687 GEN_HANDLER(name, opc, 0xFF, 0xFF, 0x00000000, type) \
2766 { \ 2688 { \
2767 - TCGv EA = tcg_temp_new(); \  
2768 - gen_set_access_type(ACCESS_INT); \  
2769 - gen_addr_imm_index(EA, ctx, 0); \  
2770 - gen_qemu_##ldop(cpu_gpr[rD(ctx->opcode)], EA, ctx->mem_idx); \ 2689 + TCGv EA; \
  2690 + gen_set_access_type(ctx, ACCESS_INT); \
  2691 + EA = tcg_temp_new(); \
  2692 + gen_addr_imm_index(ctx, EA, 0); \
  2693 + gen_qemu_##ldop(ctx, cpu_gpr[rD(ctx->opcode)], EA); \
2771 tcg_temp_free(EA); \ 2694 tcg_temp_free(EA); \
2772 } 2695 }
2773 2696
@@ -2780,13 +2703,13 @@ GEN_HANDLER(name##u, opc, 0xFF, 0xFF, 0x00000000, type) \ @@ -2780,13 +2703,13 @@ GEN_HANDLER(name##u, opc, 0xFF, 0xFF, 0x00000000, type) \
2780 GEN_EXCP_INVAL(ctx); \ 2703 GEN_EXCP_INVAL(ctx); \
2781 return; \ 2704 return; \
2782 } \ 2705 } \
  2706 + gen_set_access_type(ctx, ACCESS_INT); \
2783 EA = tcg_temp_new(); \ 2707 EA = tcg_temp_new(); \
2784 - gen_set_access_type(ACCESS_INT); \  
2785 if (type == PPC_64B) \ 2708 if (type == PPC_64B) \
2786 - gen_addr_imm_index(EA, ctx, 0x03); \ 2709 + gen_addr_imm_index(ctx, EA, 0x03); \
2787 else \ 2710 else \
2788 - gen_addr_imm_index(EA, ctx, 0); \  
2789 - gen_qemu_##ldop(cpu_gpr[rD(ctx->opcode)], EA, ctx->mem_idx); \ 2711 + gen_addr_imm_index(ctx, EA, 0); \
  2712 + gen_qemu_##ldop(ctx, cpu_gpr[rD(ctx->opcode)], EA); \
2790 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \ 2713 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
2791 tcg_temp_free(EA); \ 2714 tcg_temp_free(EA); \
2792 } 2715 }
@@ -2800,10 +2723,10 @@ GEN_HANDLER(name##ux, 0x1F, opc2, opc3, 0x00000001, type) \ @@ -2800,10 +2723,10 @@ GEN_HANDLER(name##ux, 0x1F, opc2, opc3, 0x00000001, type) \
2800 GEN_EXCP_INVAL(ctx); \ 2723 GEN_EXCP_INVAL(ctx); \
2801 return; \ 2724 return; \
2802 } \ 2725 } \
  2726 + gen_set_access_type(ctx, ACCESS_INT); \
2803 EA = tcg_temp_new(); \ 2727 EA = tcg_temp_new(); \
2804 - gen_set_access_type(ACCESS_INT); \  
2805 - gen_addr_reg_index(EA, ctx); \  
2806 - gen_qemu_##ldop(cpu_gpr[rD(ctx->opcode)], EA, ctx->mem_idx); \ 2728 + gen_addr_reg_index(ctx, EA); \
  2729 + gen_qemu_##ldop(ctx, cpu_gpr[rD(ctx->opcode)], EA); \
2807 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \ 2730 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
2808 tcg_temp_free(EA); \ 2731 tcg_temp_free(EA); \
2809 } 2732 }
@@ -2811,10 +2734,11 @@ GEN_HANDLER(name##ux, 0x1F, opc2, opc3, 0x00000001, type) \ @@ -2811,10 +2734,11 @@ GEN_HANDLER(name##ux, 0x1F, opc2, opc3, 0x00000001, type) \
2811 #define GEN_LDX(name, ldop, opc2, opc3, type) \ 2734 #define GEN_LDX(name, ldop, opc2, opc3, type) \
2812 GEN_HANDLER(name##x, 0x1F, opc2, opc3, 0x00000001, type) \ 2735 GEN_HANDLER(name##x, 0x1F, opc2, opc3, 0x00000001, type) \
2813 { \ 2736 { \
2814 - TCGv EA = tcg_temp_new(); \  
2815 - gen_set_access_type(ACCESS_INT); \  
2816 - gen_addr_reg_index(EA, ctx); \  
2817 - gen_qemu_##ldop(cpu_gpr[rD(ctx->opcode)], EA, ctx->mem_idx); \ 2737 + TCGv EA; \
  2738 + gen_set_access_type(ctx, ACCESS_INT); \
  2739 + EA = tcg_temp_new(); \
  2740 + gen_addr_reg_index(ctx, EA); \
  2741 + gen_qemu_##ldop(ctx, cpu_gpr[rD(ctx->opcode)], EA); \
2818 tcg_temp_free(EA); \ 2742 tcg_temp_free(EA); \
2819 } 2743 }
2820 2744
@@ -2851,15 +2775,15 @@ GEN_HANDLER(ld, 0x3A, 0xFF, 0xFF, 0x00000000, PPC_64B) @@ -2851,15 +2775,15 @@ GEN_HANDLER(ld, 0x3A, 0xFF, 0xFF, 0x00000000, PPC_64B)
2851 return; 2775 return;
2852 } 2776 }
2853 } 2777 }
  2778 + gen_set_access_type(ctx, ACCESS_INT);
2854 EA = tcg_temp_new(); 2779 EA = tcg_temp_new();
2855 - gen_set_access_type(ACCESS_INT);  
2856 - gen_addr_imm_index(EA, ctx, 0x03); 2780 + gen_addr_imm_index(ctx, EA, 0x03);
2857 if (ctx->opcode & 0x02) { 2781 if (ctx->opcode & 0x02) {
2858 /* lwa (lwau is undefined) */ 2782 /* lwa (lwau is undefined) */
2859 - gen_qemu_ld32s(cpu_gpr[rD(ctx->opcode)], EA, ctx->mem_idx); 2783 + gen_qemu_ld32s(ctx, cpu_gpr[rD(ctx->opcode)], EA);
2860 } else { 2784 } else {
2861 /* ld - ldu */ 2785 /* ld - ldu */
2862 - gen_qemu_ld64(cpu_gpr[rD(ctx->opcode)], EA, ctx->mem_idx); 2786 + gen_qemu_ld64(ctx, cpu_gpr[rD(ctx->opcode)], EA);
2863 } 2787 }
2864 if (Rc(ctx->opcode)) 2788 if (Rc(ctx->opcode))
2865 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); 2789 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA);
@@ -2875,7 +2799,7 @@ GEN_HANDLER(lq, 0x38, 0xFF, 0xFF, 0x00000000, PPC_64BX) @@ -2875,7 +2799,7 @@ GEN_HANDLER(lq, 0x38, 0xFF, 0xFF, 0x00000000, PPC_64BX)
2875 TCGv EA; 2799 TCGv EA;
2876 2800
2877 /* Restore CPU state */ 2801 /* Restore CPU state */
2878 - if (unlikely(ctx->supervisor == 0)) { 2802 + if (unlikely(ctx->mem_idx == 0)) {
2879 GEN_EXCP_PRIVOPC(ctx); 2803 GEN_EXCP_PRIVOPC(ctx);
2880 return; 2804 return;
2881 } 2805 }
@@ -2885,17 +2809,17 @@ GEN_HANDLER(lq, 0x38, 0xFF, 0xFF, 0x00000000, PPC_64BX) @@ -2885,17 +2809,17 @@ GEN_HANDLER(lq, 0x38, 0xFF, 0xFF, 0x00000000, PPC_64BX)
2885 GEN_EXCP_INVAL(ctx); 2809 GEN_EXCP_INVAL(ctx);
2886 return; 2810 return;
2887 } 2811 }
2888 - if (unlikely(ctx->mem_idx & 1)) { 2812 + if (unlikely(ctx->le_mode)) {
2889 /* Little-endian mode is not handled */ 2813 /* Little-endian mode is not handled */
2890 GEN_EXCP(ctx, POWERPC_EXCP_ALIGN, POWERPC_EXCP_ALIGN_LE); 2814 GEN_EXCP(ctx, POWERPC_EXCP_ALIGN, POWERPC_EXCP_ALIGN_LE);
2891 return; 2815 return;
2892 } 2816 }
  2817 + gen_set_access_type(ctx, ACCESS_INT);
2893 EA = tcg_temp_new(); 2818 EA = tcg_temp_new();
2894 - gen_set_access_type(ACCESS_INT);  
2895 - gen_addr_imm_index(EA, ctx, 0x0F);  
2896 - gen_qemu_ld64(cpu_gpr[rd], EA, ctx->mem_idx);  
2897 - tcg_gen_addi_tl(EA, EA, 8);  
2898 - gen_qemu_ld64(cpu_gpr[rd+1], EA, ctx->mem_idx); 2819 + gen_addr_imm_index(ctx, EA, 0x0F);
  2820 + gen_qemu_ld64(ctx, cpu_gpr[rd], EA);
  2821 + gen_addr_add(ctx, EA, EA, 8);
  2822 + gen_qemu_ld64(ctx, cpu_gpr[rd+1], EA);
2899 tcg_temp_free(EA); 2823 tcg_temp_free(EA);
2900 #endif 2824 #endif
2901 } 2825 }
@@ -2905,10 +2829,11 @@ GEN_HANDLER(lq, 0x38, 0xFF, 0xFF, 0x00000000, PPC_64BX) @@ -2905,10 +2829,11 @@ GEN_HANDLER(lq, 0x38, 0xFF, 0xFF, 0x00000000, PPC_64BX)
2905 #define GEN_ST(name, stop, opc, type) \ 2829 #define GEN_ST(name, stop, opc, type) \
2906 GEN_HANDLER(name, opc, 0xFF, 0xFF, 0x00000000, type) \ 2830 GEN_HANDLER(name, opc, 0xFF, 0xFF, 0x00000000, type) \
2907 { \ 2831 { \
2908 - TCGv EA = tcg_temp_new(); \  
2909 - gen_set_access_type(ACCESS_INT); \  
2910 - gen_addr_imm_index(EA, ctx, 0); \  
2911 - gen_qemu_##stop(cpu_gpr[rS(ctx->opcode)], EA, ctx->mem_idx); \ 2832 + TCGv EA; \
  2833 + gen_set_access_type(ctx, ACCESS_INT); \
  2834 + EA = tcg_temp_new(); \
  2835 + gen_addr_imm_index(ctx, EA, 0); \
  2836 + gen_qemu_##stop(ctx, cpu_gpr[rS(ctx->opcode)], EA); \
2912 tcg_temp_free(EA); \ 2837 tcg_temp_free(EA); \
2913 } 2838 }
2914 2839
@@ -2920,13 +2845,13 @@ GEN_HANDLER(stop##u, opc, 0xFF, 0xFF, 0x00000000, type) \ @@ -2920,13 +2845,13 @@ GEN_HANDLER(stop##u, opc, 0xFF, 0xFF, 0x00000000, type) \
2920 GEN_EXCP_INVAL(ctx); \ 2845 GEN_EXCP_INVAL(ctx); \
2921 return; \ 2846 return; \
2922 } \ 2847 } \
  2848 + gen_set_access_type(ctx, ACCESS_INT); \
2923 EA = tcg_temp_new(); \ 2849 EA = tcg_temp_new(); \
2924 - gen_set_access_type(ACCESS_INT); \  
2925 if (type == PPC_64B) \ 2850 if (type == PPC_64B) \
2926 - gen_addr_imm_index(EA, ctx, 0x03); \ 2851 + gen_addr_imm_index(ctx, EA, 0x03); \
2927 else \ 2852 else \
2928 - gen_addr_imm_index(EA, ctx, 0); \  
2929 - gen_qemu_##stop(cpu_gpr[rS(ctx->opcode)], EA, ctx->mem_idx); \ 2853 + gen_addr_imm_index(ctx, EA, 0); \
  2854 + gen_qemu_##stop(ctx, cpu_gpr[rS(ctx->opcode)], EA); \
2930 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \ 2855 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
2931 tcg_temp_free(EA); \ 2856 tcg_temp_free(EA); \
2932 } 2857 }
@@ -2939,10 +2864,10 @@ GEN_HANDLER(name##ux, 0x1F, opc2, opc3, 0x00000001, type) \ @@ -2939,10 +2864,10 @@ GEN_HANDLER(name##ux, 0x1F, opc2, opc3, 0x00000001, type) \
2939 GEN_EXCP_INVAL(ctx); \ 2864 GEN_EXCP_INVAL(ctx); \
2940 return; \ 2865 return; \
2941 } \ 2866 } \
  2867 + gen_set_access_type(ctx, ACCESS_INT); \
2942 EA = tcg_temp_new(); \ 2868 EA = tcg_temp_new(); \
2943 - gen_set_access_type(ACCESS_INT); \  
2944 - gen_addr_reg_index(EA, ctx); \  
2945 - gen_qemu_##stop(cpu_gpr[rS(ctx->opcode)], EA, ctx->mem_idx); \ 2869 + gen_addr_reg_index(ctx, EA); \
  2870 + gen_qemu_##stop(ctx, cpu_gpr[rS(ctx->opcode)], EA); \
2946 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \ 2871 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
2947 tcg_temp_free(EA); \ 2872 tcg_temp_free(EA); \
2948 } 2873 }
@@ -2950,10 +2875,11 @@ GEN_HANDLER(name##ux, 0x1F, opc2, opc3, 0x00000001, type) \ @@ -2950,10 +2875,11 @@ GEN_HANDLER(name##ux, 0x1F, opc2, opc3, 0x00000001, type) \
2950 #define GEN_STX(name, stop, opc2, opc3, type) \ 2875 #define GEN_STX(name, stop, opc2, opc3, type) \
2951 GEN_HANDLER(name##x, 0x1F, opc2, opc3, 0x00000001, type) \ 2876 GEN_HANDLER(name##x, 0x1F, opc2, opc3, 0x00000001, type) \
2952 { \ 2877 { \
2953 - TCGv EA = tcg_temp_new(); \  
2954 - gen_set_access_type(ACCESS_INT); \  
2955 - gen_addr_reg_index(EA, ctx); \  
2956 - gen_qemu_##stop(cpu_gpr[rS(ctx->opcode)], EA, ctx->mem_idx); \ 2878 + TCGv EA; \
  2879 + gen_set_access_type(ctx, ACCESS_INT); \
  2880 + EA = tcg_temp_new(); \
  2881 + gen_addr_reg_index(ctx, EA); \
  2882 + gen_qemu_##stop(ctx, cpu_gpr[rS(ctx->opcode)], EA); \
2957 tcg_temp_free(EA); \ 2883 tcg_temp_free(EA); \
2958 } 2884 }
2959 2885
@@ -2983,7 +2909,7 @@ GEN_HANDLER(std, 0x3E, 0xFF, 0xFF, 0x00000000, PPC_64B) @@ -2983,7 +2909,7 @@ GEN_HANDLER(std, 0x3E, 0xFF, 0xFF, 0x00000000, PPC_64B)
2983 GEN_EXCP_PRIVOPC(ctx); 2909 GEN_EXCP_PRIVOPC(ctx);
2984 #else 2910 #else
2985 /* stq */ 2911 /* stq */
2986 - if (unlikely(ctx->supervisor == 0)) { 2912 + if (unlikely(ctx->mem_idx == 0)) {
2987 GEN_EXCP_PRIVOPC(ctx); 2913 GEN_EXCP_PRIVOPC(ctx);
2988 return; 2914 return;
2989 } 2915 }
@@ -2991,17 +2917,17 @@ GEN_HANDLER(std, 0x3E, 0xFF, 0xFF, 0x00000000, PPC_64B) @@ -2991,17 +2917,17 @@ GEN_HANDLER(std, 0x3E, 0xFF, 0xFF, 0x00000000, PPC_64B)
2991 GEN_EXCP_INVAL(ctx); 2917 GEN_EXCP_INVAL(ctx);
2992 return; 2918 return;
2993 } 2919 }
2994 - if (unlikely(ctx->mem_idx & 1)) { 2920 + if (unlikely(ctx->le_mode)) {
2995 /* Little-endian mode is not handled */ 2921 /* Little-endian mode is not handled */
2996 GEN_EXCP(ctx, POWERPC_EXCP_ALIGN, POWERPC_EXCP_ALIGN_LE); 2922 GEN_EXCP(ctx, POWERPC_EXCP_ALIGN, POWERPC_EXCP_ALIGN_LE);
2997 return; 2923 return;
2998 } 2924 }
  2925 + gen_set_access_type(ctx, ACCESS_INT);
2999 EA = tcg_temp_new(); 2926 EA = tcg_temp_new();
3000 - gen_set_access_type(ACCESS_INT);  
3001 - gen_addr_imm_index(EA, ctx, 0x03);  
3002 - gen_qemu_st64(cpu_gpr[rs], EA, ctx->mem_idx);  
3003 - tcg_gen_addi_tl(EA, EA, 8);  
3004 - gen_qemu_st64(cpu_gpr[rs+1], EA, ctx->mem_idx); 2927 + gen_addr_imm_index(ctx, EA, 0x03);
  2928 + gen_qemu_st64(ctx, cpu_gpr[rs], EA);
  2929 + gen_addr_add(ctx, EA, EA, 8);
  2930 + gen_qemu_st64(ctx, cpu_gpr[rs+1], EA);
3005 tcg_temp_free(EA); 2931 tcg_temp_free(EA);
3006 #endif 2932 #endif
3007 } else { 2933 } else {
@@ -3012,10 +2938,10 @@ GEN_HANDLER(std, 0x3E, 0xFF, 0xFF, 0x00000000, PPC_64B) @@ -3012,10 +2938,10 @@ GEN_HANDLER(std, 0x3E, 0xFF, 0xFF, 0x00000000, PPC_64B)
3012 return; 2938 return;
3013 } 2939 }
3014 } 2940 }
  2941 + gen_set_access_type(ctx, ACCESS_INT);
3015 EA = tcg_temp_new(); 2942 EA = tcg_temp_new();
3016 - gen_set_access_type(ACCESS_INT);  
3017 - gen_addr_imm_index(EA, ctx, 0x03);  
3018 - gen_qemu_st64(cpu_gpr[rs], EA, ctx->mem_idx); 2943 + gen_addr_imm_index(ctx, EA, 0x03);
  2944 + gen_qemu_st64(ctx, cpu_gpr[rs], EA);
3019 if (Rc(ctx->opcode)) 2945 if (Rc(ctx->opcode))
3020 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); 2946 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA);
3021 tcg_temp_free(EA); 2947 tcg_temp_free(EA);
@@ -3024,55 +2950,94 @@ GEN_HANDLER(std, 0x3E, 0xFF, 0xFF, 0x00000000, PPC_64B) @@ -3024,55 +2950,94 @@ GEN_HANDLER(std, 0x3E, 0xFF, 0xFF, 0x00000000, PPC_64B)
3024 #endif 2950 #endif
3025 /*** Integer load and store with byte reverse ***/ 2951 /*** Integer load and store with byte reverse ***/
3026 /* lhbrx */ 2952 /* lhbrx */
3027 -static void always_inline gen_qemu_ld16ur(TCGv t0, TCGv t1, int flags) 2953 +static void always_inline gen_qemu_ld16ur(DisasContext *ctx, TCGv arg1, TCGv arg2)
3028 { 2954 {
3029 - TCGv_i32 temp = tcg_temp_new_i32();  
3030 - gen_qemu_ld16u(t0, t1, flags);  
3031 - tcg_gen_trunc_tl_i32(temp, t0);  
3032 - tcg_gen_bswap16_i32(temp, temp);  
3033 - tcg_gen_extu_i32_tl(t0, temp);  
3034 - tcg_temp_free_i32(temp); 2955 + tcg_gen_qemu_ld16u(arg1, arg2, ctx->mem_idx);
  2956 + if (likely(!ctx->le_mode)) {
  2957 +#if defined(TARGET_PPC64)
  2958 + TCGv_i32 t0 = tcg_temp_new_i32();
  2959 + tcg_gen_trunc_tl_i32(t0, arg1);
  2960 + tcg_gen_bswap16_i32(t0, t0);
  2961 + tcg_gen_extu_i32_tl(arg1, t0);
  2962 + tcg_temp_free_i32(t0);
  2963 +#else
  2964 + tcg_gen_bswap16_i32(arg1, arg1);
  2965 +#endif
  2966 + }
3035 } 2967 }
3036 GEN_LDX(lhbr, ld16ur, 0x16, 0x18, PPC_INTEGER); 2968 GEN_LDX(lhbr, ld16ur, 0x16, 0x18, PPC_INTEGER);
3037 2969
3038 /* lwbrx */ 2970 /* lwbrx */
3039 -static void always_inline gen_qemu_ld32ur(TCGv t0, TCGv t1, int flags) 2971 +static void always_inline gen_qemu_ld32ur(DisasContext *ctx, TCGv arg1, TCGv arg2)
3040 { 2972 {
3041 - TCGv_i32 temp = tcg_temp_new_i32();  
3042 - gen_qemu_ld32u(t0, t1, flags);  
3043 - tcg_gen_trunc_tl_i32(temp, t0);  
3044 - tcg_gen_bswap_i32(temp, temp);  
3045 - tcg_gen_extu_i32_tl(t0, temp);  
3046 - tcg_temp_free_i32(temp); 2973 + tcg_gen_qemu_ld32u(arg1, arg2, ctx->mem_idx);
  2974 + if (likely(!ctx->le_mode)) {
  2975 +#if defined(TARGET_PPC64)
  2976 + TCGv_i32 t0 = tcg_temp_new_i32();
  2977 + tcg_gen_trunc_tl_i32(t0, arg1);
  2978 + tcg_gen_bswap_i32(t0, t0);
  2979 + tcg_gen_extu_i32_tl(arg1, t0);
  2980 + tcg_temp_free_i32(t0);
  2981 +#else
  2982 + tcg_gen_bswap_i32(arg1, arg1);
  2983 +#endif
  2984 + }
3047 } 2985 }
3048 GEN_LDX(lwbr, ld32ur, 0x16, 0x10, PPC_INTEGER); 2986 GEN_LDX(lwbr, ld32ur, 0x16, 0x10, PPC_INTEGER);
3049 2987
3050 /* sthbrx */ 2988 /* sthbrx */
3051 -static void always_inline gen_qemu_st16r(TCGv t0, TCGv t1, int flags) 2989 +static void always_inline gen_qemu_st16r(DisasContext *ctx, TCGv arg1, TCGv arg2)
3052 { 2990 {
3053 - TCGv_i32 temp = tcg_temp_new_i32();  
3054 - TCGv t2 = tcg_temp_new();  
3055 - tcg_gen_trunc_tl_i32(temp, t0);  
3056 - tcg_gen_ext16u_i32(temp, temp);  
3057 - tcg_gen_bswap16_i32(temp, temp);  
3058 - tcg_gen_extu_i32_tl(t2, temp);  
3059 - tcg_temp_free_i32(temp);  
3060 - gen_qemu_st16(t2, t1, flags);  
3061 - tcg_temp_free(t2); 2991 + if (likely(!ctx->le_mode)) {
  2992 +#if defined(TARGET_PPC64)
  2993 + TCGv_i32 t0;
  2994 + TCGv t1;
  2995 + t0 = tcg_temp_new_i32();
  2996 + tcg_gen_trunc_tl_i32(t0, arg1);
  2997 + tcg_gen_ext16u_i32(t0, t0);
  2998 + tcg_gen_bswap16_i32(t0, t0);
  2999 + t1 = tcg_temp_new();
  3000 + tcg_gen_extu_i32_tl(t1, t0);
  3001 + tcg_temp_free_i32(t0);
  3002 + tcg_gen_qemu_st16(t1, arg2, ctx->mem_idx);
  3003 + tcg_temp_free(t1);
  3004 +#else
  3005 + TCGv t0 = tcg_temp_new();
  3006 + tcg_gen_ext16u_tl(t0, arg1);
  3007 + tcg_gen_bswap16_i32(t0, t0);
  3008 + tcg_gen_qemu_st16(t0, arg2, ctx->mem_idx);
  3009 + tcg_temp_free(t0);
  3010 +#endif
  3011 + } else {
  3012 + tcg_gen_qemu_st16(arg1, arg2, ctx->mem_idx);
  3013 + }
3062 } 3014 }
3063 GEN_STX(sthbr, st16r, 0x16, 0x1C, PPC_INTEGER); 3015 GEN_STX(sthbr, st16r, 0x16, 0x1C, PPC_INTEGER);
3064 3016
3065 /* stwbrx */ 3017 /* stwbrx */
3066 -static void always_inline gen_qemu_st32r(TCGv t0, TCGv t1, int flags) 3018 +static void always_inline gen_qemu_st32r(DisasContext *ctx, TCGv arg1, TCGv arg2)
3067 { 3019 {
3068 - TCGv_i32 temp = tcg_temp_new_i32();  
3069 - TCGv t2 = tcg_temp_new();  
3070 - tcg_gen_trunc_tl_i32(temp, t0);  
3071 - tcg_gen_bswap_i32(temp, temp);  
3072 - tcg_gen_extu_i32_tl(t2, temp);  
3073 - tcg_temp_free_i32(temp);  
3074 - gen_qemu_st32(t2, t1, flags);  
3075 - tcg_temp_free(t2); 3020 + if (likely(!ctx->le_mode)) {
  3021 +#if defined(TARGET_PPC64)
  3022 + TCGv_i32 t0;
  3023 + TCGv t1;
  3024 + t0 = tcg_temp_new_i32();
  3025 + tcg_gen_trunc_tl_i32(t0, arg1);
  3026 + tcg_gen_bswap_i32(t0, t0);
  3027 + t1 = tcg_temp_new();
  3028 + tcg_gen_extu_i32_tl(t1, t0);
  3029 + tcg_temp_free_i32(t0);
  3030 + tcg_gen_qemu_st32(t1, arg2, ctx->mem_idx);
  3031 + tcg_temp_free(t1);
  3032 +#else
  3033 + TCGv t0 = tcg_temp_new_i32();
  3034 + tcg_gen_bswap_i32(t0, arg1);
  3035 + tcg_gen_qemu_st32(t0, arg2, ctx->mem_idx);
  3036 + tcg_temp_free(t0);
  3037 +#endif
  3038 + } else {
  3039 + tcg_gen_qemu_st32(arg1, arg2, ctx->mem_idx);
  3040 + }
3076 } 3041 }
3077 GEN_STX(stwbr, st32r, 0x16, 0x14, PPC_INTEGER); 3042 GEN_STX(stwbr, st32r, 0x16, 0x14, PPC_INTEGER);
3078 3043
@@ -3080,11 +3045,14 @@ GEN_STX(stwbr, st32r, 0x16, 0x14, PPC_INTEGER); @@ -3080,11 +3045,14 @@ GEN_STX(stwbr, st32r, 0x16, 0x14, PPC_INTEGER);
3080 /* lmw */ 3045 /* lmw */
3081 GEN_HANDLER(lmw, 0x2E, 0xFF, 0xFF, 0x00000000, PPC_INTEGER) 3046 GEN_HANDLER(lmw, 0x2E, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
3082 { 3047 {
3083 - TCGv t0 = tcg_temp_new();  
3084 - TCGv_i32 t1 = tcg_const_i32(rD(ctx->opcode)); 3048 + TCGv t0;
  3049 + TCGv_i32 t1;
  3050 + gen_set_access_type(ctx, ACCESS_INT);
3085 /* NIP cannot be restored if the memory exception comes from an helper */ 3051 /* NIP cannot be restored if the memory exception comes from an helper */
3086 gen_update_nip(ctx, ctx->nip - 4); 3052 gen_update_nip(ctx, ctx->nip - 4);
3087 - gen_addr_imm_index(t0, ctx, 0); 3053 + t0 = tcg_temp_new();
  3054 + t1 = tcg_const_i32(rD(ctx->opcode));
  3055 + gen_addr_imm_index(ctx, t0, 0);
3088 gen_helper_lmw(t0, t1); 3056 gen_helper_lmw(t0, t1);
3089 tcg_temp_free(t0); 3057 tcg_temp_free(t0);
3090 tcg_temp_free_i32(t1); 3058 tcg_temp_free_i32(t1);
@@ -3093,11 +3061,14 @@ GEN_HANDLER(lmw, 0x2E, 0xFF, 0xFF, 0x00000000, PPC_INTEGER) @@ -3093,11 +3061,14 @@ GEN_HANDLER(lmw, 0x2E, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
3093 /* stmw */ 3061 /* stmw */
3094 GEN_HANDLER(stmw, 0x2F, 0xFF, 0xFF, 0x00000000, PPC_INTEGER) 3062 GEN_HANDLER(stmw, 0x2F, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
3095 { 3063 {
3096 - TCGv t0 = tcg_temp_new();  
3097 - TCGv_i32 t1 = tcg_const_i32(rS(ctx->opcode)); 3064 + TCGv t0;
  3065 + TCGv_i32 t1;
  3066 + gen_set_access_type(ctx, ACCESS_INT);
3098 /* NIP cannot be restored if the memory exception comes from an helper */ 3067 /* NIP cannot be restored if the memory exception comes from an helper */
3099 gen_update_nip(ctx, ctx->nip - 4); 3068 gen_update_nip(ctx, ctx->nip - 4);
3100 - gen_addr_imm_index(t0, ctx, 0); 3069 + t0 = tcg_temp_new();
  3070 + t1 = tcg_const_i32(rS(ctx->opcode));
  3071 + gen_addr_imm_index(ctx, t0, 0);
3101 gen_helper_stmw(t0, t1); 3072 gen_helper_stmw(t0, t1);
3102 tcg_temp_free(t0); 3073 tcg_temp_free(t0);
3103 tcg_temp_free_i32(t1); 3074 tcg_temp_free_i32(t1);
@@ -3129,10 +3100,11 @@ GEN_HANDLER(lswi, 0x1F, 0x15, 0x12, 0x00000001, PPC_STRING) @@ -3129,10 +3100,11 @@ GEN_HANDLER(lswi, 0x1F, 0x15, 0x12, 0x00000001, PPC_STRING)
3129 POWERPC_EXCP_INVAL | POWERPC_EXCP_INVAL_LSWX); 3100 POWERPC_EXCP_INVAL | POWERPC_EXCP_INVAL_LSWX);
3130 return; 3101 return;
3131 } 3102 }
  3103 + gen_set_access_type(ctx, ACCESS_INT);
3132 /* NIP cannot be restored if the memory exception comes from an helper */ 3104 /* NIP cannot be restored if the memory exception comes from an helper */
3133 gen_update_nip(ctx, ctx->nip - 4); 3105 gen_update_nip(ctx, ctx->nip - 4);
3134 t0 = tcg_temp_new(); 3106 t0 = tcg_temp_new();
3135 - gen_addr_register(t0, ctx); 3107 + gen_addr_register(ctx, t0);
3136 t1 = tcg_const_i32(nb); 3108 t1 = tcg_const_i32(nb);
3137 t2 = tcg_const_i32(start); 3109 t2 = tcg_const_i32(start);
3138 gen_helper_lsw(t0, t1, t2); 3110 gen_helper_lsw(t0, t1, t2);
@@ -3144,13 +3116,16 @@ GEN_HANDLER(lswi, 0x1F, 0x15, 0x12, 0x00000001, PPC_STRING) @@ -3144,13 +3116,16 @@ GEN_HANDLER(lswi, 0x1F, 0x15, 0x12, 0x00000001, PPC_STRING)
3144 /* lswx */ 3116 /* lswx */
3145 GEN_HANDLER(lswx, 0x1F, 0x15, 0x10, 0x00000001, PPC_STRING) 3117 GEN_HANDLER(lswx, 0x1F, 0x15, 0x10, 0x00000001, PPC_STRING)
3146 { 3118 {
3147 - TCGv t0 = tcg_temp_new();  
3148 - TCGv_i32 t1 = tcg_const_i32(rD(ctx->opcode));  
3149 - TCGv_i32 t2 = tcg_const_i32(rA(ctx->opcode));  
3150 - TCGv_i32 t3 = tcg_const_i32(rB(ctx->opcode)); 3119 + TCGv t0;
  3120 + TCGv_i32 t1, t2, t3;
  3121 + gen_set_access_type(ctx, ACCESS_INT);
3151 /* NIP cannot be restored if the memory exception comes from an helper */ 3122 /* NIP cannot be restored if the memory exception comes from an helper */
3152 gen_update_nip(ctx, ctx->nip - 4); 3123 gen_update_nip(ctx, ctx->nip - 4);
3153 - gen_addr_reg_index(t0, ctx); 3124 + t0 = tcg_temp_new();
  3125 + gen_addr_reg_index(ctx, t0);
  3126 + t1 = tcg_const_i32(rD(ctx->opcode));
  3127 + t2 = tcg_const_i32(rA(ctx->opcode));
  3128 + t3 = tcg_const_i32(rB(ctx->opcode));
3154 gen_helper_lswx(t0, t1, t2, t3); 3129 gen_helper_lswx(t0, t1, t2, t3);
3155 tcg_temp_free(t0); 3130 tcg_temp_free(t0);
3156 tcg_temp_free_i32(t1); 3131 tcg_temp_free_i32(t1);
@@ -3161,16 +3136,18 @@ GEN_HANDLER(lswx, 0x1F, 0x15, 0x10, 0x00000001, PPC_STRING) @@ -3161,16 +3136,18 @@ GEN_HANDLER(lswx, 0x1F, 0x15, 0x10, 0x00000001, PPC_STRING)
3161 /* stswi */ 3136 /* stswi */
3162 GEN_HANDLER(stswi, 0x1F, 0x15, 0x16, 0x00000001, PPC_STRING) 3137 GEN_HANDLER(stswi, 0x1F, 0x15, 0x16, 0x00000001, PPC_STRING)
3163 { 3138 {
  3139 + TCGv t0;
  3140 + TCGv_i32 t1, t2;
3164 int nb = NB(ctx->opcode); 3141 int nb = NB(ctx->opcode);
3165 - TCGv t0 = tcg_temp_new();  
3166 - TCGv_i32 t1;  
3167 - TCGv_i32 t2 = tcg_const_i32(rS(ctx->opcode)); 3142 + gen_set_access_type(ctx, ACCESS_INT);
3168 /* NIP cannot be restored if the memory exception comes from an helper */ 3143 /* NIP cannot be restored if the memory exception comes from an helper */
3169 gen_update_nip(ctx, ctx->nip - 4); 3144 gen_update_nip(ctx, ctx->nip - 4);
3170 - gen_addr_register(t0, ctx); 3145 + t0 = tcg_temp_new();
  3146 + gen_addr_register(ctx, t0);
3171 if (nb == 0) 3147 if (nb == 0)
3172 nb = 32; 3148 nb = 32;
3173 t1 = tcg_const_i32(nb); 3149 t1 = tcg_const_i32(nb);
  3150 + t2 = tcg_const_i32(rS(ctx->opcode));
3174 gen_helper_stsw(t0, t1, t2); 3151 gen_helper_stsw(t0, t1, t2);
3175 tcg_temp_free(t0); 3152 tcg_temp_free(t0);
3176 tcg_temp_free_i32(t1); 3153 tcg_temp_free_i32(t1);
@@ -3180,14 +3157,17 @@ GEN_HANDLER(stswi, 0x1F, 0x15, 0x16, 0x00000001, PPC_STRING) @@ -3180,14 +3157,17 @@ GEN_HANDLER(stswi, 0x1F, 0x15, 0x16, 0x00000001, PPC_STRING)
3180 /* stswx */ 3157 /* stswx */
3181 GEN_HANDLER(stswx, 0x1F, 0x15, 0x14, 0x00000001, PPC_STRING) 3158 GEN_HANDLER(stswx, 0x1F, 0x15, 0x14, 0x00000001, PPC_STRING)
3182 { 3159 {
3183 - TCGv t0 = tcg_temp_new();  
3184 - TCGv_i32 t1 = tcg_temp_new_i32();  
3185 - TCGv_i32 t2 = tcg_const_i32(rS(ctx->opcode)); 3160 + TCGv t0;
  3161 + TCGv_i32 t1, t2;
  3162 + gen_set_access_type(ctx, ACCESS_INT);
3186 /* NIP cannot be restored if the memory exception comes from an helper */ 3163 /* NIP cannot be restored if the memory exception comes from an helper */
3187 gen_update_nip(ctx, ctx->nip - 4); 3164 gen_update_nip(ctx, ctx->nip - 4);
3188 - gen_addr_reg_index(t0, ctx); 3165 + t0 = tcg_temp_new();
  3166 + gen_addr_reg_index(ctx, t0);
  3167 + t1 = tcg_temp_new_i32();
3189 tcg_gen_trunc_tl_i32(t1, cpu_xer); 3168 tcg_gen_trunc_tl_i32(t1, cpu_xer);
3190 tcg_gen_andi_i32(t1, t1, 0x7F); 3169 tcg_gen_andi_i32(t1, t1, 0x7F);
  3170 + t2 = tcg_const_i32(rS(ctx->opcode));
3191 gen_helper_stsw(t0, t1, t2); 3171 gen_helper_stsw(t0, t1, t2);
3192 tcg_temp_free(t0); 3172 tcg_temp_free(t0);
3193 tcg_temp_free_i32(t1); 3173 tcg_temp_free_i32(t1);
@@ -3209,15 +3189,12 @@ GEN_HANDLER(isync, 0x13, 0x16, 0x04, 0x03FFF801, PPC_MEM) @@ -3209,15 +3189,12 @@ GEN_HANDLER(isync, 0x13, 0x16, 0x04, 0x03FFF801, PPC_MEM)
3209 /* lwarx */ 3189 /* lwarx */
3210 GEN_HANDLER(lwarx, 0x1F, 0x14, 0x00, 0x00000001, PPC_RES) 3190 GEN_HANDLER(lwarx, 0x1F, 0x14, 0x00, 0x00000001, PPC_RES)
3211 { 3191 {
3212 - TCGv t0 = tcg_temp_local_new();  
3213 - gen_set_access_type(ACCESS_RES);  
3214 - gen_addr_reg_index(t0, ctx); 3192 + TCGv t0;
  3193 + gen_set_access_type(ctx, ACCESS_RES);
  3194 + t0 = tcg_temp_local_new();
  3195 + gen_addr_reg_index(ctx, t0);
3215 gen_check_align(ctx, t0, 0x03); 3196 gen_check_align(ctx, t0, 0x03);
3216 -#if defined(TARGET_PPC64)  
3217 - if (!ctx->sf_mode)  
3218 - tcg_gen_ext32u_tl(t0, t0);  
3219 -#endif  
3220 - gen_qemu_ld32u(cpu_gpr[rD(ctx->opcode)], t0, ctx->mem_idx); 3197 + gen_qemu_ld32u(ctx, cpu_gpr[rD(ctx->opcode)], t0);
3221 tcg_gen_mov_tl(cpu_reserve, t0); 3198 tcg_gen_mov_tl(cpu_reserve, t0);
3222 tcg_temp_free(t0); 3199 tcg_temp_free(t0);
3223 } 3200 }
@@ -3225,21 +3202,19 @@ GEN_HANDLER(lwarx, 0x1F, 0x14, 0x00, 0x00000001, PPC_RES) @@ -3225,21 +3202,19 @@ GEN_HANDLER(lwarx, 0x1F, 0x14, 0x00, 0x00000001, PPC_RES)
3225 /* stwcx. */ 3202 /* stwcx. */
3226 GEN_HANDLER2(stwcx_, "stwcx.", 0x1F, 0x16, 0x04, 0x00000000, PPC_RES) 3203 GEN_HANDLER2(stwcx_, "stwcx.", 0x1F, 0x16, 0x04, 0x00000000, PPC_RES)
3227 { 3204 {
3228 - int l1 = gen_new_label();  
3229 - TCGv t0 = tcg_temp_local_new();  
3230 - gen_set_access_type(ACCESS_RES);  
3231 - gen_addr_reg_index(t0, ctx); 3205 + int l1;
  3206 + TCGv t0;
  3207 + gen_set_access_type(ctx, ACCESS_RES);
  3208 + t0 = tcg_temp_local_new();
  3209 + gen_addr_reg_index(ctx, t0);
3232 gen_check_align(ctx, t0, 0x03); 3210 gen_check_align(ctx, t0, 0x03);
3233 -#if defined(TARGET_PPC64)  
3234 - if (!ctx->sf_mode)  
3235 - tcg_gen_ext32u_tl(t0, t0);  
3236 -#endif  
3237 tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_xer); 3211 tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_xer);
3238 tcg_gen_shri_i32(cpu_crf[0], cpu_crf[0], XER_SO); 3212 tcg_gen_shri_i32(cpu_crf[0], cpu_crf[0], XER_SO);
3239 tcg_gen_andi_i32(cpu_crf[0], cpu_crf[0], 1); 3213 tcg_gen_andi_i32(cpu_crf[0], cpu_crf[0], 1);
  3214 + l1 = gen_new_label();
3240 tcg_gen_brcond_tl(TCG_COND_NE, t0, cpu_reserve, l1); 3215 tcg_gen_brcond_tl(TCG_COND_NE, t0, cpu_reserve, l1);
3241 tcg_gen_ori_i32(cpu_crf[0], cpu_crf[0], 1 << CRF_EQ); 3216 tcg_gen_ori_i32(cpu_crf[0], cpu_crf[0], 1 << CRF_EQ);
3242 - gen_qemu_st32(cpu_gpr[rS(ctx->opcode)], t0, ctx->mem_idx); 3217 + gen_qemu_st32(ctx, cpu_gpr[rS(ctx->opcode)], t0);
3243 gen_set_label(l1); 3218 gen_set_label(l1);
3244 tcg_gen_movi_tl(cpu_reserve, -1); 3219 tcg_gen_movi_tl(cpu_reserve, -1);
3245 tcg_temp_free(t0); 3220 tcg_temp_free(t0);
@@ -3249,13 +3224,12 @@ GEN_HANDLER2(stwcx_, &quot;stwcx.&quot;, 0x1F, 0x16, 0x04, 0x00000000, PPC_RES) @@ -3249,13 +3224,12 @@ GEN_HANDLER2(stwcx_, &quot;stwcx.&quot;, 0x1F, 0x16, 0x04, 0x00000000, PPC_RES)
3249 /* ldarx */ 3224 /* ldarx */
3250 GEN_HANDLER(ldarx, 0x1F, 0x14, 0x02, 0x00000001, PPC_64B) 3225 GEN_HANDLER(ldarx, 0x1F, 0x14, 0x02, 0x00000001, PPC_64B)
3251 { 3226 {
3252 - TCGv t0 = tcg_temp_local_new();  
3253 - gen_set_access_type(ACCESS_RES);  
3254 - gen_addr_reg_index(t0, ctx); 3227 + TCGv t0;
  3228 + gen_set_access_type(ctx, ACCESS_RES);
  3229 + t0 = tcg_temp_local_new();
  3230 + gen_addr_reg_index(ctx, t0);
3255 gen_check_align(ctx, t0, 0x07); 3231 gen_check_align(ctx, t0, 0x07);
3256 - if (!ctx->sf_mode)  
3257 - tcg_gen_ext32u_tl(t0, t0);  
3258 - gen_qemu_ld64(cpu_gpr[rD(ctx->opcode)], t0, ctx->mem_idx); 3232 + gen_qemu_ld64(ctx, cpu_gpr[rD(ctx->opcode)], t0);
3259 tcg_gen_mov_tl(cpu_reserve, t0); 3233 tcg_gen_mov_tl(cpu_reserve, t0);
3260 tcg_temp_free(t0); 3234 tcg_temp_free(t0);
3261 } 3235 }
@@ -3263,19 +3237,19 @@ GEN_HANDLER(ldarx, 0x1F, 0x14, 0x02, 0x00000001, PPC_64B) @@ -3263,19 +3237,19 @@ GEN_HANDLER(ldarx, 0x1F, 0x14, 0x02, 0x00000001, PPC_64B)
3263 /* stdcx. */ 3237 /* stdcx. */
3264 GEN_HANDLER2(stdcx_, "stdcx.", 0x1F, 0x16, 0x06, 0x00000000, PPC_64B) 3238 GEN_HANDLER2(stdcx_, "stdcx.", 0x1F, 0x16, 0x06, 0x00000000, PPC_64B)
3265 { 3239 {
3266 - int l1 = gen_new_label();  
3267 - TCGv t0 = tcg_temp_local_new();  
3268 - gen_set_access_type(ACCESS_RES);  
3269 - gen_addr_reg_index(t0, ctx); 3240 + int l1;
  3241 + TCGv t0;
  3242 + gen_set_access_type(ctx, ACCESS_RES);
  3243 + t0 = tcg_temp_local_new();
  3244 + gen_addr_reg_index(ctx, t0);
3270 gen_check_align(ctx, t0, 0x07); 3245 gen_check_align(ctx, t0, 0x07);
3271 - if (!ctx->sf_mode)  
3272 - tcg_gen_ext32u_tl(t0, t0);  
3273 tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_xer); 3246 tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_xer);
3274 tcg_gen_shri_i32(cpu_crf[0], cpu_crf[0], XER_SO); 3247 tcg_gen_shri_i32(cpu_crf[0], cpu_crf[0], XER_SO);
3275 tcg_gen_andi_i32(cpu_crf[0], cpu_crf[0], 1); 3248 tcg_gen_andi_i32(cpu_crf[0], cpu_crf[0], 1);
  3249 + l1 = gen_new_label();
3276 tcg_gen_brcond_tl(TCG_COND_NE, t0, cpu_reserve, l1); 3250 tcg_gen_brcond_tl(TCG_COND_NE, t0, cpu_reserve, l1);
3277 tcg_gen_ori_i32(cpu_crf[0], cpu_crf[0], 1 << CRF_EQ); 3251 tcg_gen_ori_i32(cpu_crf[0], cpu_crf[0], 1 << CRF_EQ);
3278 - gen_qemu_st64(cpu_gpr[rS(ctx->opcode)], t0, ctx->mem_idx); 3252 + gen_qemu_st64(ctx, cpu_gpr[rS(ctx->opcode)], t0);
3279 gen_set_label(l1); 3253 gen_set_label(l1);
3280 tcg_gen_movi_tl(cpu_reserve, -1); 3254 tcg_gen_movi_tl(cpu_reserve, -1);
3281 tcg_temp_free(t0); 3255 tcg_temp_free(t0);
@@ -3306,10 +3280,10 @@ GEN_HANDLER(name, opc, 0xFF, 0xFF, 0x00000000, type) \ @@ -3306,10 +3280,10 @@ GEN_HANDLER(name, opc, 0xFF, 0xFF, 0x00000000, type) \
3306 GEN_EXCP_NO_FP(ctx); \ 3280 GEN_EXCP_NO_FP(ctx); \
3307 return; \ 3281 return; \
3308 } \ 3282 } \
3309 - gen_set_access_type(ACCESS_FLOAT); \ 3283 + gen_set_access_type(ctx, ACCESS_FLOAT); \
3310 EA = tcg_temp_new(); \ 3284 EA = tcg_temp_new(); \
3311 - gen_addr_imm_index(EA, ctx, 0); \  
3312 - gen_qemu_##ldop(cpu_fpr[rD(ctx->opcode)], EA, ctx->mem_idx); \ 3285 + gen_addr_imm_index(ctx, EA, 0); \
  3286 + gen_qemu_##ldop(ctx, cpu_fpr[rD(ctx->opcode)], EA); \
3313 tcg_temp_free(EA); \ 3287 tcg_temp_free(EA); \
3314 } 3288 }
3315 3289
@@ -3325,10 +3299,10 @@ GEN_HANDLER(name##u, opc, 0xFF, 0xFF, 0x00000000, type) \ @@ -3325,10 +3299,10 @@ GEN_HANDLER(name##u, opc, 0xFF, 0xFF, 0x00000000, type) \
3325 GEN_EXCP_INVAL(ctx); \ 3299 GEN_EXCP_INVAL(ctx); \
3326 return; \ 3300 return; \
3327 } \ 3301 } \
3328 - gen_set_access_type(ACCESS_FLOAT); \ 3302 + gen_set_access_type(ctx, ACCESS_FLOAT); \
3329 EA = tcg_temp_new(); \ 3303 EA = tcg_temp_new(); \
3330 - gen_addr_imm_index(EA, ctx, 0); \  
3331 - gen_qemu_##ldop(cpu_fpr[rD(ctx->opcode)], EA, ctx->mem_idx); \ 3304 + gen_addr_imm_index(ctx, EA, 0); \
  3305 + gen_qemu_##ldop(ctx, cpu_fpr[rD(ctx->opcode)], EA); \
3332 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \ 3306 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
3333 tcg_temp_free(EA); \ 3307 tcg_temp_free(EA); \
3334 } 3308 }
@@ -3345,10 +3319,10 @@ GEN_HANDLER(name##ux, 0x1F, 0x17, opc, 0x00000001, type) \ @@ -3345,10 +3319,10 @@ GEN_HANDLER(name##ux, 0x1F, 0x17, opc, 0x00000001, type) \
3345 GEN_EXCP_INVAL(ctx); \ 3319 GEN_EXCP_INVAL(ctx); \
3346 return; \ 3320 return; \
3347 } \ 3321 } \
3348 - gen_set_access_type(ACCESS_FLOAT); \ 3322 + gen_set_access_type(ctx, ACCESS_FLOAT); \
3349 EA = tcg_temp_new(); \ 3323 EA = tcg_temp_new(); \
3350 - gen_addr_reg_index(EA, ctx); \  
3351 - gen_qemu_##ldop(cpu_fpr[rD(ctx->opcode)], EA, ctx->mem_idx); \ 3324 + gen_addr_reg_index(ctx, EA); \
  3325 + gen_qemu_##ldop(ctx, cpu_fpr[rD(ctx->opcode)], EA); \
3352 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \ 3326 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
3353 tcg_temp_free(EA); \ 3327 tcg_temp_free(EA); \
3354 } 3328 }
@@ -3361,10 +3335,10 @@ GEN_HANDLER(name##x, 0x1F, opc2, opc3, 0x00000001, type) \ @@ -3361,10 +3335,10 @@ GEN_HANDLER(name##x, 0x1F, opc2, opc3, 0x00000001, type) \
3361 GEN_EXCP_NO_FP(ctx); \ 3335 GEN_EXCP_NO_FP(ctx); \
3362 return; \ 3336 return; \
3363 } \ 3337 } \
3364 - gen_set_access_type(ACCESS_FLOAT); \ 3338 + gen_set_access_type(ctx, ACCESS_FLOAT); \
3365 EA = tcg_temp_new(); \ 3339 EA = tcg_temp_new(); \
3366 - gen_addr_reg_index(EA, ctx); \  
3367 - gen_qemu_##ldop(cpu_fpr[rD(ctx->opcode)], EA, ctx->mem_idx); \ 3340 + gen_addr_reg_index(ctx, EA); \
  3341 + gen_qemu_##ldop(ctx, cpu_fpr[rD(ctx->opcode)], EA); \
3368 tcg_temp_free(EA); \ 3342 tcg_temp_free(EA); \
3369 } 3343 }
3370 3344
@@ -3374,11 +3348,11 @@ GEN_LDUF(name, ldop, op | 0x21, type); \ @@ -3374,11 +3348,11 @@ GEN_LDUF(name, ldop, op | 0x21, type); \
3374 GEN_LDUXF(name, ldop, op | 0x01, type); \ 3348 GEN_LDUXF(name, ldop, op | 0x01, type); \
3375 GEN_LDXF(name, ldop, 0x17, op | 0x00, type) 3349 GEN_LDXF(name, ldop, 0x17, op | 0x00, type)
3376 3350
3377 -static always_inline void gen_qemu_ld32fs(TCGv_i64 arg1, TCGv arg2, int flags) 3351 +static always_inline void gen_qemu_ld32fs(DisasContext *ctx, TCGv_i64 arg1, TCGv arg2)
3378 { 3352 {
3379 TCGv t0 = tcg_temp_new(); 3353 TCGv t0 = tcg_temp_new();
3380 TCGv_i32 t1 = tcg_temp_new_i32(); 3354 TCGv_i32 t1 = tcg_temp_new_i32();
3381 - gen_qemu_ld32u(t0, arg2, flags); 3355 + gen_qemu_ld32u(ctx, t0, arg2);
3382 tcg_gen_trunc_tl_i32(t1, t0); 3356 tcg_gen_trunc_tl_i32(t1, t0);
3383 tcg_temp_free(t0); 3357 tcg_temp_free(t0);
3384 gen_helper_float32_to_float64(arg1, t1); 3358 gen_helper_float32_to_float64(arg1, t1);
@@ -3399,10 +3373,10 @@ GEN_HANDLER(name, opc, 0xFF, 0xFF, 0x00000000, type) \ @@ -3399,10 +3373,10 @@ GEN_HANDLER(name, opc, 0xFF, 0xFF, 0x00000000, type) \
3399 GEN_EXCP_NO_FP(ctx); \ 3373 GEN_EXCP_NO_FP(ctx); \
3400 return; \ 3374 return; \
3401 } \ 3375 } \
3402 - gen_set_access_type(ACCESS_FLOAT); \ 3376 + gen_set_access_type(ctx, ACCESS_FLOAT); \
3403 EA = tcg_temp_new(); \ 3377 EA = tcg_temp_new(); \
3404 - gen_addr_imm_index(EA, ctx, 0); \  
3405 - gen_qemu_##stop(cpu_fpr[rS(ctx->opcode)], EA, ctx->mem_idx); \ 3378 + gen_addr_imm_index(ctx, EA, 0); \
  3379 + gen_qemu_##stop(ctx, cpu_fpr[rS(ctx->opcode)], EA); \
3406 tcg_temp_free(EA); \ 3380 tcg_temp_free(EA); \
3407 } 3381 }
3408 3382
@@ -3418,10 +3392,10 @@ GEN_HANDLER(name##u, opc, 0xFF, 0xFF, 0x00000000, type) \ @@ -3418,10 +3392,10 @@ GEN_HANDLER(name##u, opc, 0xFF, 0xFF, 0x00000000, type) \
3418 GEN_EXCP_INVAL(ctx); \ 3392 GEN_EXCP_INVAL(ctx); \
3419 return; \ 3393 return; \
3420 } \ 3394 } \
3421 - gen_set_access_type(ACCESS_FLOAT); \ 3395 + gen_set_access_type(ctx, ACCESS_FLOAT); \
3422 EA = tcg_temp_new(); \ 3396 EA = tcg_temp_new(); \
3423 - gen_addr_imm_index(EA, ctx, 0); \  
3424 - gen_qemu_##stop(cpu_fpr[rS(ctx->opcode)], EA, ctx->mem_idx); \ 3397 + gen_addr_imm_index(ctx, EA, 0); \
  3398 + gen_qemu_##stop(ctx, cpu_fpr[rS(ctx->opcode)], EA); \
3425 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \ 3399 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
3426 tcg_temp_free(EA); \ 3400 tcg_temp_free(EA); \
3427 } 3401 }
@@ -3438,10 +3412,10 @@ GEN_HANDLER(name##ux, 0x1F, 0x17, opc, 0x00000001, type) \ @@ -3438,10 +3412,10 @@ GEN_HANDLER(name##ux, 0x1F, 0x17, opc, 0x00000001, type) \
3438 GEN_EXCP_INVAL(ctx); \ 3412 GEN_EXCP_INVAL(ctx); \
3439 return; \ 3413 return; \
3440 } \ 3414 } \
3441 - gen_set_access_type(ACCESS_FLOAT); \ 3415 + gen_set_access_type(ctx, ACCESS_FLOAT); \
3442 EA = tcg_temp_new(); \ 3416 EA = tcg_temp_new(); \
3443 - gen_addr_reg_index(EA, ctx); \  
3444 - gen_qemu_##stop(cpu_fpr[rS(ctx->opcode)], EA, ctx->mem_idx); \ 3417 + gen_addr_reg_index(ctx, EA); \
  3418 + gen_qemu_##stop(ctx, cpu_fpr[rS(ctx->opcode)], EA); \
3445 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \ 3419 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
3446 tcg_temp_free(EA); \ 3420 tcg_temp_free(EA); \
3447 } 3421 }
@@ -3454,10 +3428,10 @@ GEN_HANDLER(name##x, 0x1F, opc2, opc3, 0x00000001, type) \ @@ -3454,10 +3428,10 @@ GEN_HANDLER(name##x, 0x1F, opc2, opc3, 0x00000001, type) \
3454 GEN_EXCP_NO_FP(ctx); \ 3428 GEN_EXCP_NO_FP(ctx); \
3455 return; \ 3429 return; \
3456 } \ 3430 } \
3457 - gen_set_access_type(ACCESS_FLOAT); \ 3431 + gen_set_access_type(ctx, ACCESS_FLOAT); \
3458 EA = tcg_temp_new(); \ 3432 EA = tcg_temp_new(); \
3459 - gen_addr_reg_index(EA, ctx); \  
3460 - gen_qemu_##stop(cpu_fpr[rS(ctx->opcode)], EA, ctx->mem_idx); \ 3433 + gen_addr_reg_index(ctx, EA); \
  3434 + gen_qemu_##stop(ctx, cpu_fpr[rS(ctx->opcode)], EA); \
3461 tcg_temp_free(EA); \ 3435 tcg_temp_free(EA); \
3462 } 3436 }
3463 3437
@@ -3467,14 +3441,14 @@ GEN_STUF(name, stop, op | 0x21, type); \ @@ -3467,14 +3441,14 @@ GEN_STUF(name, stop, op | 0x21, type); \
3467 GEN_STUXF(name, stop, op | 0x01, type); \ 3441 GEN_STUXF(name, stop, op | 0x01, type); \
3468 GEN_STXF(name, stop, 0x17, op | 0x00, type) 3442 GEN_STXF(name, stop, 0x17, op | 0x00, type)
3469 3443
3470 -static always_inline void gen_qemu_st32fs(TCGv_i64 arg1, TCGv arg2, int flags) 3444 +static always_inline void gen_qemu_st32fs(DisasContext *ctx, TCGv_i64 arg1, TCGv arg2)
3471 { 3445 {
3472 TCGv_i32 t0 = tcg_temp_new_i32(); 3446 TCGv_i32 t0 = tcg_temp_new_i32();
3473 TCGv t1 = tcg_temp_new(); 3447 TCGv t1 = tcg_temp_new();
3474 gen_helper_float64_to_float32(t0, arg1); 3448 gen_helper_float64_to_float32(t0, arg1);
3475 tcg_gen_extu_i32_tl(t1, t0); 3449 tcg_gen_extu_i32_tl(t1, t0);
3476 tcg_temp_free_i32(t0); 3450 tcg_temp_free_i32(t0);
3477 - gen_qemu_st32(t1, arg2, flags); 3451 + gen_qemu_st32(ctx, t1, arg2);
3478 tcg_temp_free(t1); 3452 tcg_temp_free(t1);
3479 } 3453 }
3480 3454
@@ -3484,11 +3458,11 @@ GEN_STFS(stfd, st64, 0x16, PPC_FLOAT); @@ -3484,11 +3458,11 @@ GEN_STFS(stfd, st64, 0x16, PPC_FLOAT);
3484 GEN_STFS(stfs, st32fs, 0x14, PPC_FLOAT); 3458 GEN_STFS(stfs, st32fs, 0x14, PPC_FLOAT);
3485 3459
3486 /* Optional: */ 3460 /* Optional: */
3487 -static always_inline void gen_qemu_st32fiw(TCGv_i64 arg1, TCGv arg2, int flags) 3461 +static always_inline void gen_qemu_st32fiw(DisasContext *ctx, TCGv_i64 arg1, TCGv arg2)
3488 { 3462 {
3489 TCGv t0 = tcg_temp_new(); 3463 TCGv t0 = tcg_temp_new();
3490 tcg_gen_trunc_i64_tl(t0, arg1), 3464 tcg_gen_trunc_i64_tl(t0, arg1),
3491 - gen_qemu_st32(t0, arg2, flags); 3465 + gen_qemu_st32(ctx, t0, arg2);
3492 tcg_temp_free(t0); 3466 tcg_temp_free(t0);
3493 } 3467 }
3494 /* stfiwx */ 3468 /* stfiwx */
@@ -3716,14 +3690,14 @@ GEN_HANDLER(mcrf, 0x13, 0x00, 0xFF, 0x00000001, PPC_INTEGER) @@ -3716,14 +3690,14 @@ GEN_HANDLER(mcrf, 0x13, 0x00, 0xFF, 0x00000001, PPC_INTEGER)
3716 } 3690 }
3717 3691
3718 /*** System linkage ***/ 3692 /*** System linkage ***/
3719 -/* rfi (supervisor only) */ 3693 +/* rfi (mem_idx only) */
3720 GEN_HANDLER(rfi, 0x13, 0x12, 0x01, 0x03FF8001, PPC_FLOW) 3694 GEN_HANDLER(rfi, 0x13, 0x12, 0x01, 0x03FF8001, PPC_FLOW)
3721 { 3695 {
3722 #if defined(CONFIG_USER_ONLY) 3696 #if defined(CONFIG_USER_ONLY)
3723 GEN_EXCP_PRIVOPC(ctx); 3697 GEN_EXCP_PRIVOPC(ctx);
3724 #else 3698 #else
3725 /* Restore CPU state */ 3699 /* Restore CPU state */
3726 - if (unlikely(!ctx->supervisor)) { 3700 + if (unlikely(!ctx->mem_idx)) {
3727 GEN_EXCP_PRIVOPC(ctx); 3701 GEN_EXCP_PRIVOPC(ctx);
3728 return; 3702 return;
3729 } 3703 }
@@ -3739,7 +3713,7 @@ GEN_HANDLER(rfid, 0x13, 0x12, 0x00, 0x03FF8001, PPC_64B) @@ -3739,7 +3713,7 @@ GEN_HANDLER(rfid, 0x13, 0x12, 0x00, 0x03FF8001, PPC_64B)
3739 GEN_EXCP_PRIVOPC(ctx); 3713 GEN_EXCP_PRIVOPC(ctx);
3740 #else 3714 #else
3741 /* Restore CPU state */ 3715 /* Restore CPU state */
3742 - if (unlikely(!ctx->supervisor)) { 3716 + if (unlikely(!ctx->mem_idx)) {
3743 GEN_EXCP_PRIVOPC(ctx); 3717 GEN_EXCP_PRIVOPC(ctx);
3744 return; 3718 return;
3745 } 3719 }
@@ -3754,7 +3728,7 @@ GEN_HANDLER(hrfid, 0x13, 0x12, 0x08, 0x03FF8001, PPC_64H) @@ -3754,7 +3728,7 @@ GEN_HANDLER(hrfid, 0x13, 0x12, 0x08, 0x03FF8001, PPC_64H)
3754 GEN_EXCP_PRIVOPC(ctx); 3728 GEN_EXCP_PRIVOPC(ctx);
3755 #else 3729 #else
3756 /* Restore CPU state */ 3730 /* Restore CPU state */
3757 - if (unlikely(ctx->supervisor <= 1)) { 3731 + if (unlikely(ctx->mem_idx <= 1)) {
3758 GEN_EXCP_PRIVOPC(ctx); 3732 GEN_EXCP_PRIVOPC(ctx);
3759 return; 3733 return;
3760 } 3734 }
@@ -3856,7 +3830,7 @@ GEN_HANDLER(mfmsr, 0x1F, 0x13, 0x02, 0x001FF801, PPC_MISC) @@ -3856,7 +3830,7 @@ GEN_HANDLER(mfmsr, 0x1F, 0x13, 0x02, 0x001FF801, PPC_MISC)
3856 #if defined(CONFIG_USER_ONLY) 3830 #if defined(CONFIG_USER_ONLY)
3857 GEN_EXCP_PRIVREG(ctx); 3831 GEN_EXCP_PRIVREG(ctx);
3858 #else 3832 #else
3859 - if (unlikely(!ctx->supervisor)) { 3833 + if (unlikely(!ctx->mem_idx)) {
3860 GEN_EXCP_PRIVREG(ctx); 3834 GEN_EXCP_PRIVREG(ctx);
3861 return; 3835 return;
3862 } 3836 }
@@ -3882,9 +3856,9 @@ static always_inline void gen_op_mfspr (DisasContext *ctx) @@ -3882,9 +3856,9 @@ static always_inline void gen_op_mfspr (DisasContext *ctx)
3882 uint32_t sprn = SPR(ctx->opcode); 3856 uint32_t sprn = SPR(ctx->opcode);
3883 3857
3884 #if !defined(CONFIG_USER_ONLY) 3858 #if !defined(CONFIG_USER_ONLY)
3885 - if (ctx->supervisor == 2) 3859 + if (ctx->mem_idx == 2)
3886 read_cb = ctx->spr_cb[sprn].hea_read; 3860 read_cb = ctx->spr_cb[sprn].hea_read;
3887 - else if (ctx->supervisor) 3861 + else if (ctx->mem_idx)
3888 read_cb = ctx->spr_cb[sprn].oea_read; 3862 read_cb = ctx->spr_cb[sprn].oea_read;
3889 else 3863 else
3890 #endif 3864 #endif
@@ -3959,7 +3933,7 @@ GEN_HANDLER(mtmsrd, 0x1F, 0x12, 0x05, 0x001EF801, PPC_64B) @@ -3959,7 +3933,7 @@ GEN_HANDLER(mtmsrd, 0x1F, 0x12, 0x05, 0x001EF801, PPC_64B)
3959 #if defined(CONFIG_USER_ONLY) 3933 #if defined(CONFIG_USER_ONLY)
3960 GEN_EXCP_PRIVREG(ctx); 3934 GEN_EXCP_PRIVREG(ctx);
3961 #else 3935 #else
3962 - if (unlikely(!ctx->supervisor)) { 3936 + if (unlikely(!ctx->mem_idx)) {
3963 GEN_EXCP_PRIVREG(ctx); 3937 GEN_EXCP_PRIVREG(ctx);
3964 return; 3938 return;
3965 } 3939 }
@@ -3990,7 +3964,7 @@ GEN_HANDLER(mtmsr, 0x1F, 0x12, 0x04, 0x001FF801, PPC_MISC) @@ -3990,7 +3964,7 @@ GEN_HANDLER(mtmsr, 0x1F, 0x12, 0x04, 0x001FF801, PPC_MISC)
3990 #if defined(CONFIG_USER_ONLY) 3964 #if defined(CONFIG_USER_ONLY)
3991 GEN_EXCP_PRIVREG(ctx); 3965 GEN_EXCP_PRIVREG(ctx);
3992 #else 3966 #else
3993 - if (unlikely(!ctx->supervisor)) { 3967 + if (unlikely(!ctx->mem_idx)) {
3994 GEN_EXCP_PRIVREG(ctx); 3968 GEN_EXCP_PRIVREG(ctx);
3995 return; 3969 return;
3996 } 3970 }
@@ -4034,9 +4008,9 @@ GEN_HANDLER(mtspr, 0x1F, 0x13, 0x0E, 0x00000001, PPC_MISC) @@ -4034,9 +4008,9 @@ GEN_HANDLER(mtspr, 0x1F, 0x13, 0x0E, 0x00000001, PPC_MISC)
4034 uint32_t sprn = SPR(ctx->opcode); 4008 uint32_t sprn = SPR(ctx->opcode);
4035 4009
4036 #if !defined(CONFIG_USER_ONLY) 4010 #if !defined(CONFIG_USER_ONLY)
4037 - if (ctx->supervisor == 2) 4011 + if (ctx->mem_idx == 2)
4038 write_cb = ctx->spr_cb[sprn].hea_write; 4012 write_cb = ctx->spr_cb[sprn].hea_write;
4039 - else if (ctx->supervisor) 4013 + else if (ctx->mem_idx)
4040 write_cb = ctx->spr_cb[sprn].oea_write; 4014 write_cb = ctx->spr_cb[sprn].oea_write;
4041 else 4015 else
4042 #endif 4016 #endif
@@ -4072,10 +4046,11 @@ GEN_HANDLER(mtspr, 0x1F, 0x13, 0x0E, 0x00000001, PPC_MISC) @@ -4072,10 +4046,11 @@ GEN_HANDLER(mtspr, 0x1F, 0x13, 0x0E, 0x00000001, PPC_MISC)
4072 GEN_HANDLER(dcbf, 0x1F, 0x16, 0x02, 0x03C00001, PPC_CACHE) 4046 GEN_HANDLER(dcbf, 0x1F, 0x16, 0x02, 0x03C00001, PPC_CACHE)
4073 { 4047 {
4074 /* XXX: specification says this is treated as a load by the MMU */ 4048 /* XXX: specification says this is treated as a load by the MMU */
4075 - TCGv t0 = tcg_temp_new();  
4076 - gen_set_access_type(ACCESS_CACHE);  
4077 - gen_addr_reg_index(t0, ctx);  
4078 - gen_qemu_ld8u(t0, t0, ctx->mem_idx); 4049 + TCGv t0;
  4050 + gen_set_access_type(ctx, ACCESS_CACHE);
  4051 + t0 = tcg_temp_new();
  4052 + gen_addr_reg_index(ctx, t0);
  4053 + gen_qemu_ld8u(ctx, t0, t0);
4079 tcg_temp_free(t0); 4054 tcg_temp_free(t0);
4080 } 4055 }
4081 4056
@@ -4086,17 +4061,17 @@ GEN_HANDLER(dcbi, 0x1F, 0x16, 0x0E, 0x03E00001, PPC_CACHE) @@ -4086,17 +4061,17 @@ GEN_HANDLER(dcbi, 0x1F, 0x16, 0x0E, 0x03E00001, PPC_CACHE)
4086 GEN_EXCP_PRIVOPC(ctx); 4061 GEN_EXCP_PRIVOPC(ctx);
4087 #else 4062 #else
4088 TCGv EA, val; 4063 TCGv EA, val;
4089 - if (unlikely(!ctx->supervisor)) { 4064 + if (unlikely(!ctx->mem_idx)) {
4090 GEN_EXCP_PRIVOPC(ctx); 4065 GEN_EXCP_PRIVOPC(ctx);
4091 return; 4066 return;
4092 } 4067 }
4093 EA = tcg_temp_new(); 4068 EA = tcg_temp_new();
4094 - gen_set_access_type(ACCESS_CACHE);  
4095 - gen_addr_reg_index(EA, ctx); 4069 + gen_set_access_type(ctx, ACCESS_CACHE);
  4070 + gen_addr_reg_index(ctx, EA);
4096 val = tcg_temp_new(); 4071 val = tcg_temp_new();
4097 /* XXX: specification says this should be treated as a store by the MMU */ 4072 /* XXX: specification says this should be treated as a store by the MMU */
4098 - gen_qemu_ld8u(val, EA, ctx->mem_idx);  
4099 - gen_qemu_st8(val, EA, ctx->mem_idx); 4073 + gen_qemu_ld8u(ctx, val, EA);
  4074 + gen_qemu_st8(ctx, val, EA);
4100 tcg_temp_free(val); 4075 tcg_temp_free(val);
4101 tcg_temp_free(EA); 4076 tcg_temp_free(EA);
4102 #endif 4077 #endif
@@ -4106,10 +4081,11 @@ GEN_HANDLER(dcbi, 0x1F, 0x16, 0x0E, 0x03E00001, PPC_CACHE) @@ -4106,10 +4081,11 @@ GEN_HANDLER(dcbi, 0x1F, 0x16, 0x0E, 0x03E00001, PPC_CACHE)
4106 GEN_HANDLER(dcbst, 0x1F, 0x16, 0x01, 0x03E00001, PPC_CACHE) 4081 GEN_HANDLER(dcbst, 0x1F, 0x16, 0x01, 0x03E00001, PPC_CACHE)
4107 { 4082 {
4108 /* XXX: specification say this is treated as a load by the MMU */ 4083 /* XXX: specification say this is treated as a load by the MMU */
4109 - TCGv t0 = tcg_temp_new();  
4110 - gen_set_access_type(ACCESS_CACHE);  
4111 - gen_addr_reg_index(t0, ctx);  
4112 - gen_qemu_ld8u(t0, t0, ctx->mem_idx); 4084 + TCGv t0;
  4085 + gen_set_access_type(ctx, ACCESS_CACHE);
  4086 + t0 = tcg_temp_new();
  4087 + gen_addr_reg_index(ctx, t0);
  4088 + gen_qemu_ld8u(ctx, t0, t0);
4113 tcg_temp_free(t0); 4089 tcg_temp_free(t0);
4114 } 4090 }
4115 4091
@@ -4134,20 +4110,24 @@ GEN_HANDLER(dcbtst, 0x1F, 0x16, 0x07, 0x02000001, PPC_CACHE) @@ -4134,20 +4110,24 @@ GEN_HANDLER(dcbtst, 0x1F, 0x16, 0x07, 0x02000001, PPC_CACHE)
4134 /* dcbz */ 4110 /* dcbz */
4135 GEN_HANDLER(dcbz, 0x1F, 0x16, 0x1F, 0x03E00001, PPC_CACHE_DCBZ) 4111 GEN_HANDLER(dcbz, 0x1F, 0x16, 0x1F, 0x03E00001, PPC_CACHE_DCBZ)
4136 { 4112 {
4137 - TCGv t0 = tcg_temp_new();  
4138 - gen_addr_reg_index(t0, ctx); 4113 + TCGv t0;
  4114 + gen_set_access_type(ctx, ACCESS_CACHE);
4139 /* NIP cannot be restored if the memory exception comes from an helper */ 4115 /* NIP cannot be restored if the memory exception comes from an helper */
4140 gen_update_nip(ctx, ctx->nip - 4); 4116 gen_update_nip(ctx, ctx->nip - 4);
  4117 + t0 = tcg_temp_new();
  4118 + gen_addr_reg_index(ctx, t0);
4141 gen_helper_dcbz(t0); 4119 gen_helper_dcbz(t0);
4142 tcg_temp_free(t0); 4120 tcg_temp_free(t0);
4143 } 4121 }
4144 4122
4145 GEN_HANDLER2(dcbz_970, "dcbz", 0x1F, 0x16, 0x1F, 0x03C00001, PPC_CACHE_DCBZT) 4123 GEN_HANDLER2(dcbz_970, "dcbz", 0x1F, 0x16, 0x1F, 0x03C00001, PPC_CACHE_DCBZT)
4146 { 4124 {
4147 - TCGv t0 = tcg_temp_new();  
4148 - gen_addr_reg_index(t0, ctx); 4125 + TCGv t0;
  4126 + gen_set_access_type(ctx, ACCESS_CACHE);
4149 /* NIP cannot be restored if the memory exception comes from an helper */ 4127 /* NIP cannot be restored if the memory exception comes from an helper */
4150 gen_update_nip(ctx, ctx->nip - 4); 4128 gen_update_nip(ctx, ctx->nip - 4);
  4129 + t0 = tcg_temp_new();
  4130 + gen_addr_reg_index(ctx, t0);
4151 if (ctx->opcode & 0x00200000) 4131 if (ctx->opcode & 0x00200000)
4152 gen_helper_dcbz(t0); 4132 gen_helper_dcbz(t0);
4153 else 4133 else
@@ -4158,10 +4138,12 @@ GEN_HANDLER2(dcbz_970, &quot;dcbz&quot;, 0x1F, 0x16, 0x1F, 0x03C00001, PPC_CACHE_DCBZT) @@ -4158,10 +4138,12 @@ GEN_HANDLER2(dcbz_970, &quot;dcbz&quot;, 0x1F, 0x16, 0x1F, 0x03C00001, PPC_CACHE_DCBZT)
4158 /* icbi */ 4138 /* icbi */
4159 GEN_HANDLER(icbi, 0x1F, 0x16, 0x1E, 0x03E00001, PPC_CACHE_ICBI) 4139 GEN_HANDLER(icbi, 0x1F, 0x16, 0x1E, 0x03E00001, PPC_CACHE_ICBI)
4160 { 4140 {
4161 - TCGv t0 = tcg_temp_new(); 4141 + TCGv t0;
  4142 + gen_set_access_type(ctx, ACCESS_CACHE);
4162 /* NIP cannot be restored if the memory exception comes from an helper */ 4143 /* NIP cannot be restored if the memory exception comes from an helper */
4163 gen_update_nip(ctx, ctx->nip - 4); 4144 gen_update_nip(ctx, ctx->nip - 4);
4164 - gen_addr_reg_index(t0, ctx); 4145 + t0 = tcg_temp_new();
  4146 + gen_addr_reg_index(ctx, t0);
4165 gen_helper_icbi(t0); 4147 gen_helper_icbi(t0);
4166 tcg_temp_free(t0); 4148 tcg_temp_free(t0);
4167 } 4149 }
@@ -4185,7 +4167,7 @@ GEN_HANDLER(mfsr, 0x1F, 0x13, 0x12, 0x0010F801, PPC_SEGMENT) @@ -4185,7 +4167,7 @@ GEN_HANDLER(mfsr, 0x1F, 0x13, 0x12, 0x0010F801, PPC_SEGMENT)
4185 GEN_EXCP_PRIVREG(ctx); 4167 GEN_EXCP_PRIVREG(ctx);
4186 #else 4168 #else
4187 TCGv t0; 4169 TCGv t0;
4188 - if (unlikely(!ctx->supervisor)) { 4170 + if (unlikely(!ctx->mem_idx)) {
4189 GEN_EXCP_PRIVREG(ctx); 4171 GEN_EXCP_PRIVREG(ctx);
4190 return; 4172 return;
4191 } 4173 }
@@ -4202,7 +4184,7 @@ GEN_HANDLER(mfsrin, 0x1F, 0x13, 0x14, 0x001F0001, PPC_SEGMENT) @@ -4202,7 +4184,7 @@ GEN_HANDLER(mfsrin, 0x1F, 0x13, 0x14, 0x001F0001, PPC_SEGMENT)
4202 GEN_EXCP_PRIVREG(ctx); 4184 GEN_EXCP_PRIVREG(ctx);
4203 #else 4185 #else
4204 TCGv t0; 4186 TCGv t0;
4205 - if (unlikely(!ctx->supervisor)) { 4187 + if (unlikely(!ctx->mem_idx)) {
4206 GEN_EXCP_PRIVREG(ctx); 4188 GEN_EXCP_PRIVREG(ctx);
4207 return; 4189 return;
4208 } 4190 }
@@ -4221,7 +4203,7 @@ GEN_HANDLER(mtsr, 0x1F, 0x12, 0x06, 0x0010F801, PPC_SEGMENT) @@ -4221,7 +4203,7 @@ GEN_HANDLER(mtsr, 0x1F, 0x12, 0x06, 0x0010F801, PPC_SEGMENT)
4221 GEN_EXCP_PRIVREG(ctx); 4203 GEN_EXCP_PRIVREG(ctx);
4222 #else 4204 #else
4223 TCGv t0; 4205 TCGv t0;
4224 - if (unlikely(!ctx->supervisor)) { 4206 + if (unlikely(!ctx->mem_idx)) {
4225 GEN_EXCP_PRIVREG(ctx); 4207 GEN_EXCP_PRIVREG(ctx);
4226 return; 4208 return;
4227 } 4209 }
@@ -4238,7 +4220,7 @@ GEN_HANDLER(mtsrin, 0x1F, 0x12, 0x07, 0x001F0001, PPC_SEGMENT) @@ -4238,7 +4220,7 @@ GEN_HANDLER(mtsrin, 0x1F, 0x12, 0x07, 0x001F0001, PPC_SEGMENT)
4238 GEN_EXCP_PRIVREG(ctx); 4220 GEN_EXCP_PRIVREG(ctx);
4239 #else 4221 #else
4240 TCGv t0; 4222 TCGv t0;
4241 - if (unlikely(!ctx->supervisor)) { 4223 + if (unlikely(!ctx->mem_idx)) {
4242 GEN_EXCP_PRIVREG(ctx); 4224 GEN_EXCP_PRIVREG(ctx);
4243 return; 4225 return;
4244 } 4226 }
@@ -4259,7 +4241,7 @@ GEN_HANDLER2(mfsr_64b, &quot;mfsr&quot;, 0x1F, 0x13, 0x12, 0x0010F801, PPC_SEGMENT_64B) @@ -4259,7 +4241,7 @@ GEN_HANDLER2(mfsr_64b, &quot;mfsr&quot;, 0x1F, 0x13, 0x12, 0x0010F801, PPC_SEGMENT_64B)
4259 GEN_EXCP_PRIVREG(ctx); 4241 GEN_EXCP_PRIVREG(ctx);
4260 #else 4242 #else
4261 TCGv t0; 4243 TCGv t0;
4262 - if (unlikely(!ctx->supervisor)) { 4244 + if (unlikely(!ctx->mem_idx)) {
4263 GEN_EXCP_PRIVREG(ctx); 4245 GEN_EXCP_PRIVREG(ctx);
4264 return; 4246 return;
4265 } 4247 }
@@ -4277,7 +4259,7 @@ GEN_HANDLER2(mfsrin_64b, &quot;mfsrin&quot;, 0x1F, 0x13, 0x14, 0x001F0001, @@ -4277,7 +4259,7 @@ GEN_HANDLER2(mfsrin_64b, &quot;mfsrin&quot;, 0x1F, 0x13, 0x14, 0x001F0001,
4277 GEN_EXCP_PRIVREG(ctx); 4259 GEN_EXCP_PRIVREG(ctx);
4278 #else 4260 #else
4279 TCGv t0; 4261 TCGv t0;
4280 - if (unlikely(!ctx->supervisor)) { 4262 + if (unlikely(!ctx->mem_idx)) {
4281 GEN_EXCP_PRIVREG(ctx); 4263 GEN_EXCP_PRIVREG(ctx);
4282 return; 4264 return;
4283 } 4265 }
@@ -4296,7 +4278,7 @@ GEN_HANDLER2(mtsr_64b, &quot;mtsr&quot;, 0x1F, 0x12, 0x06, 0x0010F801, PPC_SEGMENT_64B) @@ -4296,7 +4278,7 @@ GEN_HANDLER2(mtsr_64b, &quot;mtsr&quot;, 0x1F, 0x12, 0x06, 0x0010F801, PPC_SEGMENT_64B)
4296 GEN_EXCP_PRIVREG(ctx); 4278 GEN_EXCP_PRIVREG(ctx);
4297 #else 4279 #else
4298 TCGv t0; 4280 TCGv t0;
4299 - if (unlikely(!ctx->supervisor)) { 4281 + if (unlikely(!ctx->mem_idx)) {
4300 GEN_EXCP_PRIVREG(ctx); 4282 GEN_EXCP_PRIVREG(ctx);
4301 return; 4283 return;
4302 } 4284 }
@@ -4314,7 +4296,7 @@ GEN_HANDLER2(mtsrin_64b, &quot;mtsrin&quot;, 0x1F, 0x12, 0x07, 0x001F0001, @@ -4314,7 +4296,7 @@ GEN_HANDLER2(mtsrin_64b, &quot;mtsrin&quot;, 0x1F, 0x12, 0x07, 0x001F0001,
4314 GEN_EXCP_PRIVREG(ctx); 4296 GEN_EXCP_PRIVREG(ctx);
4315 #else 4297 #else
4316 TCGv t0; 4298 TCGv t0;
4317 - if (unlikely(!ctx->supervisor)) { 4299 + if (unlikely(!ctx->mem_idx)) {
4318 GEN_EXCP_PRIVREG(ctx); 4300 GEN_EXCP_PRIVREG(ctx);
4319 return; 4301 return;
4320 } 4302 }
@@ -4328,14 +4310,14 @@ GEN_HANDLER2(mtsrin_64b, &quot;mtsrin&quot;, 0x1F, 0x12, 0x07, 0x001F0001, @@ -4328,14 +4310,14 @@ GEN_HANDLER2(mtsrin_64b, &quot;mtsrin&quot;, 0x1F, 0x12, 0x07, 0x001F0001,
4328 #endif /* defined(TARGET_PPC64) */ 4310 #endif /* defined(TARGET_PPC64) */
4329 4311
4330 /*** Lookaside buffer management ***/ 4312 /*** Lookaside buffer management ***/
4331 -/* Optional & supervisor only: */ 4313 +/* Optional & mem_idx only: */
4332 /* tlbia */ 4314 /* tlbia */
4333 GEN_HANDLER(tlbia, 0x1F, 0x12, 0x0B, 0x03FFFC01, PPC_MEM_TLBIA) 4315 GEN_HANDLER(tlbia, 0x1F, 0x12, 0x0B, 0x03FFFC01, PPC_MEM_TLBIA)
4334 { 4316 {
4335 #if defined(CONFIG_USER_ONLY) 4317 #if defined(CONFIG_USER_ONLY)
4336 GEN_EXCP_PRIVOPC(ctx); 4318 GEN_EXCP_PRIVOPC(ctx);
4337 #else 4319 #else
4338 - if (unlikely(!ctx->supervisor)) { 4320 + if (unlikely(!ctx->mem_idx)) {
4339 GEN_EXCP_PRIVOPC(ctx); 4321 GEN_EXCP_PRIVOPC(ctx);
4340 return; 4322 return;
4341 } 4323 }
@@ -4349,7 +4331,7 @@ GEN_HANDLER(tlbie, 0x1F, 0x12, 0x09, 0x03FF0001, PPC_MEM_TLBIE) @@ -4349,7 +4331,7 @@ GEN_HANDLER(tlbie, 0x1F, 0x12, 0x09, 0x03FF0001, PPC_MEM_TLBIE)
4349 #if defined(CONFIG_USER_ONLY) 4331 #if defined(CONFIG_USER_ONLY)
4350 GEN_EXCP_PRIVOPC(ctx); 4332 GEN_EXCP_PRIVOPC(ctx);
4351 #else 4333 #else
4352 - if (unlikely(!ctx->supervisor)) { 4334 + if (unlikely(!ctx->mem_idx)) {
4353 GEN_EXCP_PRIVOPC(ctx); 4335 GEN_EXCP_PRIVOPC(ctx);
4354 return; 4336 return;
4355 } 4337 }
@@ -4371,7 +4353,7 @@ GEN_HANDLER(tlbsync, 0x1F, 0x16, 0x11, 0x03FFF801, PPC_MEM_TLBSYNC) @@ -4371,7 +4353,7 @@ GEN_HANDLER(tlbsync, 0x1F, 0x16, 0x11, 0x03FFF801, PPC_MEM_TLBSYNC)
4371 #if defined(CONFIG_USER_ONLY) 4353 #if defined(CONFIG_USER_ONLY)
4372 GEN_EXCP_PRIVOPC(ctx); 4354 GEN_EXCP_PRIVOPC(ctx);
4373 #else 4355 #else
4374 - if (unlikely(!ctx->supervisor)) { 4356 + if (unlikely(!ctx->mem_idx)) {
4375 GEN_EXCP_PRIVOPC(ctx); 4357 GEN_EXCP_PRIVOPC(ctx);
4376 return; 4358 return;
4377 } 4359 }
@@ -4389,7 +4371,7 @@ GEN_HANDLER(slbia, 0x1F, 0x12, 0x0F, 0x03FFFC01, PPC_SLBI) @@ -4389,7 +4371,7 @@ GEN_HANDLER(slbia, 0x1F, 0x12, 0x0F, 0x03FFFC01, PPC_SLBI)
4389 #if defined(CONFIG_USER_ONLY) 4371 #if defined(CONFIG_USER_ONLY)
4390 GEN_EXCP_PRIVOPC(ctx); 4372 GEN_EXCP_PRIVOPC(ctx);
4391 #else 4373 #else
4392 - if (unlikely(!ctx->supervisor)) { 4374 + if (unlikely(!ctx->mem_idx)) {
4393 GEN_EXCP_PRIVOPC(ctx); 4375 GEN_EXCP_PRIVOPC(ctx);
4394 return; 4376 return;
4395 } 4377 }
@@ -4403,7 +4385,7 @@ GEN_HANDLER(slbie, 0x1F, 0x12, 0x0D, 0x03FF0001, PPC_SLBI) @@ -4403,7 +4385,7 @@ GEN_HANDLER(slbie, 0x1F, 0x12, 0x0D, 0x03FF0001, PPC_SLBI)
4403 #if defined(CONFIG_USER_ONLY) 4385 #if defined(CONFIG_USER_ONLY)
4404 GEN_EXCP_PRIVOPC(ctx); 4386 GEN_EXCP_PRIVOPC(ctx);
4405 #else 4387 #else
4406 - if (unlikely(!ctx->supervisor)) { 4388 + if (unlikely(!ctx->mem_idx)) {
4407 GEN_EXCP_PRIVOPC(ctx); 4389 GEN_EXCP_PRIVOPC(ctx);
4408 return; 4390 return;
4409 } 4391 }
@@ -4417,24 +4399,26 @@ GEN_HANDLER(slbie, 0x1F, 0x12, 0x0D, 0x03FF0001, PPC_SLBI) @@ -4417,24 +4399,26 @@ GEN_HANDLER(slbie, 0x1F, 0x12, 0x0D, 0x03FF0001, PPC_SLBI)
4417 /* eciwx */ 4399 /* eciwx */
4418 GEN_HANDLER(eciwx, 0x1F, 0x16, 0x0D, 0x00000001, PPC_EXTERN) 4400 GEN_HANDLER(eciwx, 0x1F, 0x16, 0x0D, 0x00000001, PPC_EXTERN)
4419 { 4401 {
  4402 + TCGv t0;
4420 /* Should check EAR[E] ! */ 4403 /* Should check EAR[E] ! */
4421 - TCGv t0 = tcg_temp_new();  
4422 - gen_set_access_type(ACCESS_RES);  
4423 - gen_addr_reg_index(t0, ctx); 4404 + gen_set_access_type(ctx, ACCESS_EXT);
  4405 + t0 = tcg_temp_new();
  4406 + gen_addr_reg_index(ctx, t0);
4424 gen_check_align(ctx, t0, 0x03); 4407 gen_check_align(ctx, t0, 0x03);
4425 - gen_qemu_ld32u(cpu_gpr[rD(ctx->opcode)], t0, ctx->mem_idx); 4408 + gen_qemu_ld32u(ctx, cpu_gpr[rD(ctx->opcode)], t0);
4426 tcg_temp_free(t0); 4409 tcg_temp_free(t0);
4427 } 4410 }
4428 4411
4429 /* ecowx */ 4412 /* ecowx */
4430 GEN_HANDLER(ecowx, 0x1F, 0x16, 0x09, 0x00000001, PPC_EXTERN) 4413 GEN_HANDLER(ecowx, 0x1F, 0x16, 0x09, 0x00000001, PPC_EXTERN)
4431 { 4414 {
  4415 + TCGv t0;
4432 /* Should check EAR[E] ! */ 4416 /* Should check EAR[E] ! */
4433 - TCGv t0 = tcg_temp_new();  
4434 - gen_set_access_type(ACCESS_RES);  
4435 - gen_addr_reg_index(t0, ctx); 4417 + gen_set_access_type(ctx, ACCESS_EXT);
  4418 + t0 = tcg_temp_new();
  4419 + gen_addr_reg_index(ctx, t0);
4436 gen_check_align(ctx, t0, 0x03); 4420 gen_check_align(ctx, t0, 0x03);
4437 - gen_qemu_st32(cpu_gpr[rD(ctx->opcode)], t0, ctx->mem_idx); 4421 + gen_qemu_st32(ctx, cpu_gpr[rD(ctx->opcode)], t0);
4438 tcg_temp_free(t0); 4422 tcg_temp_free(t0);
4439 } 4423 }
4440 4424
@@ -4585,7 +4569,7 @@ GEN_HANDLER(lscbx, 0x1F, 0x15, 0x08, 0x00000000, PPC_POWER_BR) @@ -4585,7 +4569,7 @@ GEN_HANDLER(lscbx, 0x1F, 0x15, 0x08, 0x00000000, PPC_POWER_BR)
4585 TCGv_i32 t2 = tcg_const_i32(rA(ctx->opcode)); 4569 TCGv_i32 t2 = tcg_const_i32(rA(ctx->opcode));
4586 TCGv_i32 t3 = tcg_const_i32(rB(ctx->opcode)); 4570 TCGv_i32 t3 = tcg_const_i32(rB(ctx->opcode));
4587 4571
4588 - gen_addr_reg_index(t0, ctx); 4572 + gen_addr_reg_index(ctx, t0);
4589 /* NIP cannot be restored if the memory exception comes from an helper */ 4573 /* NIP cannot be restored if the memory exception comes from an helper */
4590 gen_update_nip(ctx, ctx->nip - 4); 4574 gen_update_nip(ctx, ctx->nip - 4);
4591 gen_helper_lscbx(t0, t0, t1, t2, t3); 4575 gen_helper_lscbx(t0, t0, t1, t2, t3);
@@ -5099,7 +5083,7 @@ GEN_HANDLER(mfrom, 0x1F, 0x09, 0x08, 0x03E0F801, PPC_602_SPEC) @@ -5099,7 +5083,7 @@ GEN_HANDLER(mfrom, 0x1F, 0x09, 0x08, 0x03E0F801, PPC_602_SPEC)
5099 #if defined(CONFIG_USER_ONLY) 5083 #if defined(CONFIG_USER_ONLY)
5100 GEN_EXCP_PRIVOPC(ctx); 5084 GEN_EXCP_PRIVOPC(ctx);
5101 #else 5085 #else
5102 - if (unlikely(!ctx->supervisor)) { 5086 + if (unlikely(!ctx->mem_idx)) {
5103 GEN_EXCP_PRIVOPC(ctx); 5087 GEN_EXCP_PRIVOPC(ctx);
5104 return; 5088 return;
5105 } 5089 }
@@ -5114,7 +5098,7 @@ GEN_HANDLER2(tlbld_6xx, &quot;tlbld&quot;, 0x1F, 0x12, 0x1E, 0x03FF0001, PPC_6xx_TLB) @@ -5114,7 +5098,7 @@ GEN_HANDLER2(tlbld_6xx, &quot;tlbld&quot;, 0x1F, 0x12, 0x1E, 0x03FF0001, PPC_6xx_TLB)
5114 #if defined(CONFIG_USER_ONLY) 5098 #if defined(CONFIG_USER_ONLY)
5115 GEN_EXCP_PRIVOPC(ctx); 5099 GEN_EXCP_PRIVOPC(ctx);
5116 #else 5100 #else
5117 - if (unlikely(!ctx->supervisor)) { 5101 + if (unlikely(!ctx->mem_idx)) {
5118 GEN_EXCP_PRIVOPC(ctx); 5102 GEN_EXCP_PRIVOPC(ctx);
5119 return; 5103 return;
5120 } 5104 }
@@ -5128,7 +5112,7 @@ GEN_HANDLER2(tlbli_6xx, &quot;tlbli&quot;, 0x1F, 0x12, 0x1F, 0x03FF0001, PPC_6xx_TLB) @@ -5128,7 +5112,7 @@ GEN_HANDLER2(tlbli_6xx, &quot;tlbli&quot;, 0x1F, 0x12, 0x1F, 0x03FF0001, PPC_6xx_TLB)
5128 #if defined(CONFIG_USER_ONLY) 5112 #if defined(CONFIG_USER_ONLY)
5129 GEN_EXCP_PRIVOPC(ctx); 5113 GEN_EXCP_PRIVOPC(ctx);
5130 #else 5114 #else
5131 - if (unlikely(!ctx->supervisor)) { 5115 + if (unlikely(!ctx->mem_idx)) {
5132 GEN_EXCP_PRIVOPC(ctx); 5116 GEN_EXCP_PRIVOPC(ctx);
5133 return; 5117 return;
5134 } 5118 }
@@ -5143,7 +5127,7 @@ GEN_HANDLER2(tlbld_74xx, &quot;tlbld&quot;, 0x1F, 0x12, 0x1E, 0x03FF0001, PPC_74xx_TLB) @@ -5143,7 +5127,7 @@ GEN_HANDLER2(tlbld_74xx, &quot;tlbld&quot;, 0x1F, 0x12, 0x1E, 0x03FF0001, PPC_74xx_TLB)
5143 #if defined(CONFIG_USER_ONLY) 5127 #if defined(CONFIG_USER_ONLY)
5144 GEN_EXCP_PRIVOPC(ctx); 5128 GEN_EXCP_PRIVOPC(ctx);
5145 #else 5129 #else
5146 - if (unlikely(!ctx->supervisor)) { 5130 + if (unlikely(!ctx->mem_idx)) {
5147 GEN_EXCP_PRIVOPC(ctx); 5131 GEN_EXCP_PRIVOPC(ctx);
5148 return; 5132 return;
5149 } 5133 }
@@ -5157,7 +5141,7 @@ GEN_HANDLER2(tlbli_74xx, &quot;tlbli&quot;, 0x1F, 0x12, 0x1F, 0x03FF0001, PPC_74xx_TLB) @@ -5157,7 +5141,7 @@ GEN_HANDLER2(tlbli_74xx, &quot;tlbli&quot;, 0x1F, 0x12, 0x1F, 0x03FF0001, PPC_74xx_TLB)
5157 #if defined(CONFIG_USER_ONLY) 5141 #if defined(CONFIG_USER_ONLY)
5158 GEN_EXCP_PRIVOPC(ctx); 5142 GEN_EXCP_PRIVOPC(ctx);
5159 #else 5143 #else
5160 - if (unlikely(!ctx->supervisor)) { 5144 + if (unlikely(!ctx->mem_idx)) {
5161 GEN_EXCP_PRIVOPC(ctx); 5145 GEN_EXCP_PRIVOPC(ctx);
5162 return; 5146 return;
5163 } 5147 }
@@ -5179,7 +5163,7 @@ GEN_HANDLER(cli, 0x1F, 0x16, 0x0F, 0x03E00000, PPC_POWER) @@ -5179,7 +5163,7 @@ GEN_HANDLER(cli, 0x1F, 0x16, 0x0F, 0x03E00000, PPC_POWER)
5179 #if defined(CONFIG_USER_ONLY) 5163 #if defined(CONFIG_USER_ONLY)
5180 GEN_EXCP_PRIVOPC(ctx); 5164 GEN_EXCP_PRIVOPC(ctx);
5181 #else 5165 #else
5182 - if (unlikely(!ctx->supervisor)) { 5166 + if (unlikely(!ctx->mem_idx)) {
5183 GEN_EXCP_PRIVOPC(ctx); 5167 GEN_EXCP_PRIVOPC(ctx);
5184 return; 5168 return;
5185 } 5169 }
@@ -5200,12 +5184,12 @@ GEN_HANDLER(mfsri, 0x1F, 0x13, 0x13, 0x00000001, PPC_POWER) @@ -5200,12 +5184,12 @@ GEN_HANDLER(mfsri, 0x1F, 0x13, 0x13, 0x00000001, PPC_POWER)
5200 int ra = rA(ctx->opcode); 5184 int ra = rA(ctx->opcode);
5201 int rd = rD(ctx->opcode); 5185 int rd = rD(ctx->opcode);
5202 TCGv t0; 5186 TCGv t0;
5203 - if (unlikely(!ctx->supervisor)) { 5187 + if (unlikely(!ctx->mem_idx)) {
5204 GEN_EXCP_PRIVOPC(ctx); 5188 GEN_EXCP_PRIVOPC(ctx);
5205 return; 5189 return;
5206 } 5190 }
5207 t0 = tcg_temp_new(); 5191 t0 = tcg_temp_new();
5208 - gen_addr_reg_index(t0, ctx); 5192 + gen_addr_reg_index(ctx, t0);
5209 tcg_gen_shri_tl(t0, t0, 28); 5193 tcg_gen_shri_tl(t0, t0, 28);
5210 tcg_gen_andi_tl(t0, t0, 0xF); 5194 tcg_gen_andi_tl(t0, t0, 0xF);
5211 gen_helper_load_sr(cpu_gpr[rd], t0); 5195 gen_helper_load_sr(cpu_gpr[rd], t0);
@@ -5221,12 +5205,12 @@ GEN_HANDLER(rac, 0x1F, 0x12, 0x19, 0x00000001, PPC_POWER) @@ -5221,12 +5205,12 @@ GEN_HANDLER(rac, 0x1F, 0x12, 0x19, 0x00000001, PPC_POWER)
5221 GEN_EXCP_PRIVOPC(ctx); 5205 GEN_EXCP_PRIVOPC(ctx);
5222 #else 5206 #else
5223 TCGv t0; 5207 TCGv t0;
5224 - if (unlikely(!ctx->supervisor)) { 5208 + if (unlikely(!ctx->mem_idx)) {
5225 GEN_EXCP_PRIVOPC(ctx); 5209 GEN_EXCP_PRIVOPC(ctx);
5226 return; 5210 return;
5227 } 5211 }
5228 t0 = tcg_temp_new(); 5212 t0 = tcg_temp_new();
5229 - gen_addr_reg_index(t0, ctx); 5213 + gen_addr_reg_index(ctx, t0);
5230 gen_helper_rac(cpu_gpr[rD(ctx->opcode)], t0); 5214 gen_helper_rac(cpu_gpr[rD(ctx->opcode)], t0);
5231 tcg_temp_free(t0); 5215 tcg_temp_free(t0);
5232 #endif 5216 #endif
@@ -5237,7 +5221,7 @@ GEN_HANDLER(rfsvc, 0x13, 0x12, 0x02, 0x03FFF0001, PPC_POWER) @@ -5237,7 +5221,7 @@ GEN_HANDLER(rfsvc, 0x13, 0x12, 0x02, 0x03FFF0001, PPC_POWER)
5237 #if defined(CONFIG_USER_ONLY) 5221 #if defined(CONFIG_USER_ONLY)
5238 GEN_EXCP_PRIVOPC(ctx); 5222 GEN_EXCP_PRIVOPC(ctx);
5239 #else 5223 #else
5240 - if (unlikely(!ctx->supervisor)) { 5224 + if (unlikely(!ctx->mem_idx)) {
5241 GEN_EXCP_PRIVOPC(ctx); 5225 GEN_EXCP_PRIVOPC(ctx);
5242 return; 5226 return;
5243 } 5227 }
@@ -5255,11 +5239,13 @@ GEN_HANDLER(rfsvc, 0x13, 0x12, 0x02, 0x03FFF0001, PPC_POWER) @@ -5255,11 +5239,13 @@ GEN_HANDLER(rfsvc, 0x13, 0x12, 0x02, 0x03FFF0001, PPC_POWER)
5255 GEN_HANDLER(lfq, 0x38, 0xFF, 0xFF, 0x00000003, PPC_POWER2) 5239 GEN_HANDLER(lfq, 0x38, 0xFF, 0xFF, 0x00000003, PPC_POWER2)
5256 { 5240 {
5257 int rd = rD(ctx->opcode); 5241 int rd = rD(ctx->opcode);
5258 - TCGv t0 = tcg_temp_new();  
5259 - gen_addr_imm_index(t0, ctx, 0);  
5260 - gen_qemu_ld64(cpu_fpr[rd], t0, ctx->mem_idx);  
5261 - tcg_gen_addi_tl(t0, t0, 8);  
5262 - gen_qemu_ld64(cpu_fpr[(rd + 1) % 32], t0, ctx->mem_idx); 5242 + TCGv t0;
  5243 + gen_set_access_type(ctx, ACCESS_FLOAT);
  5244 + t0 = tcg_temp_new();
  5245 + gen_addr_imm_index(ctx, t0, 0);
  5246 + gen_qemu_ld64(ctx, cpu_fpr[rd], t0);
  5247 + gen_addr_add(ctx, t0, t0, 8);
  5248 + gen_qemu_ld64(ctx, cpu_fpr[(rd + 1) % 32], t0);
5263 tcg_temp_free(t0); 5249 tcg_temp_free(t0);
5264 } 5250 }
5265 5251
@@ -5268,12 +5254,14 @@ GEN_HANDLER(lfqu, 0x39, 0xFF, 0xFF, 0x00000003, PPC_POWER2) @@ -5268,12 +5254,14 @@ GEN_HANDLER(lfqu, 0x39, 0xFF, 0xFF, 0x00000003, PPC_POWER2)
5268 { 5254 {
5269 int ra = rA(ctx->opcode); 5255 int ra = rA(ctx->opcode);
5270 int rd = rD(ctx->opcode); 5256 int rd = rD(ctx->opcode);
5271 - TCGv t0 = tcg_temp_new();  
5272 - TCGv t1 = tcg_temp_new();  
5273 - gen_addr_imm_index(t0, ctx, 0);  
5274 - gen_qemu_ld64(cpu_fpr[rd], t0, ctx->mem_idx);  
5275 - tcg_gen_addi_tl(t1, t0, 8);  
5276 - gen_qemu_ld64(cpu_fpr[(rd + 1) % 32], t1, ctx->mem_idx); 5257 + TCGv t0, t1;
  5258 + gen_set_access_type(ctx, ACCESS_FLOAT);
  5259 + t0 = tcg_temp_new();
  5260 + t1 = tcg_temp_new();
  5261 + gen_addr_imm_index(ctx, t0, 0);
  5262 + gen_qemu_ld64(ctx, cpu_fpr[rd], t0);
  5263 + gen_addr_add(ctx, t1, t0, 8);
  5264 + gen_qemu_ld64(ctx, cpu_fpr[(rd + 1) % 32], t1);
5277 if (ra != 0) 5265 if (ra != 0)
5278 tcg_gen_mov_tl(cpu_gpr[ra], t0); 5266 tcg_gen_mov_tl(cpu_gpr[ra], t0);
5279 tcg_temp_free(t0); 5267 tcg_temp_free(t0);
@@ -5285,27 +5273,31 @@ GEN_HANDLER(lfqux, 0x1F, 0x17, 0x19, 0x00000001, PPC_POWER2) @@ -5285,27 +5273,31 @@ GEN_HANDLER(lfqux, 0x1F, 0x17, 0x19, 0x00000001, PPC_POWER2)
5285 { 5273 {
5286 int ra = rA(ctx->opcode); 5274 int ra = rA(ctx->opcode);
5287 int rd = rD(ctx->opcode); 5275 int rd = rD(ctx->opcode);
5288 - TCGv t0 = tcg_temp_new();  
5289 - TCGv t1 = tcg_temp_new();  
5290 - gen_addr_reg_index(t0, ctx);  
5291 - gen_qemu_ld64(cpu_fpr[rd], t0, ctx->mem_idx);  
5292 - tcg_gen_addi_tl(t1, t0, 8);  
5293 - gen_qemu_ld64(cpu_fpr[(rd + 1) % 32], t1, ctx->mem_idx); 5276 + gen_set_access_type(ctx, ACCESS_FLOAT);
  5277 + TCGv t0, t1;
  5278 + t0 = tcg_temp_new();
  5279 + gen_addr_reg_index(ctx, t0);
  5280 + gen_qemu_ld64(ctx, cpu_fpr[rd], t0);
  5281 + t1 = tcg_temp_new();
  5282 + gen_addr_add(ctx, t1, t0, 8);
  5283 + gen_qemu_ld64(ctx, cpu_fpr[(rd + 1) % 32], t1);
  5284 + tcg_temp_free(t1);
5294 if (ra != 0) 5285 if (ra != 0)
5295 tcg_gen_mov_tl(cpu_gpr[ra], t0); 5286 tcg_gen_mov_tl(cpu_gpr[ra], t0);
5296 tcg_temp_free(t0); 5287 tcg_temp_free(t0);
5297 - tcg_temp_free(t1);  
5298 } 5288 }
5299 5289
5300 /* lfqx */ 5290 /* lfqx */
5301 GEN_HANDLER(lfqx, 0x1F, 0x17, 0x18, 0x00000001, PPC_POWER2) 5291 GEN_HANDLER(lfqx, 0x1F, 0x17, 0x18, 0x00000001, PPC_POWER2)
5302 { 5292 {
5303 int rd = rD(ctx->opcode); 5293 int rd = rD(ctx->opcode);
5304 - TCGv t0 = tcg_temp_new();  
5305 - gen_addr_reg_index(t0, ctx);  
5306 - gen_qemu_ld64(cpu_fpr[rd], t0, ctx->mem_idx);  
5307 - tcg_gen_addi_tl(t0, t0, 8);  
5308 - gen_qemu_ld64(cpu_fpr[(rd + 1) % 32], t0, ctx->mem_idx); 5294 + TCGv t0;
  5295 + gen_set_access_type(ctx, ACCESS_FLOAT);
  5296 + t0 = tcg_temp_new();
  5297 + gen_addr_reg_index(ctx, t0);
  5298 + gen_qemu_ld64(ctx, cpu_fpr[rd], t0);
  5299 + gen_addr_add(ctx, t0, t0, 8);
  5300 + gen_qemu_ld64(ctx, cpu_fpr[(rd + 1) % 32], t0);
5309 tcg_temp_free(t0); 5301 tcg_temp_free(t0);
5310 } 5302 }
5311 5303
@@ -5313,11 +5305,13 @@ GEN_HANDLER(lfqx, 0x1F, 0x17, 0x18, 0x00000001, PPC_POWER2) @@ -5313,11 +5305,13 @@ GEN_HANDLER(lfqx, 0x1F, 0x17, 0x18, 0x00000001, PPC_POWER2)
5313 GEN_HANDLER(stfq, 0x3C, 0xFF, 0xFF, 0x00000003, PPC_POWER2) 5305 GEN_HANDLER(stfq, 0x3C, 0xFF, 0xFF, 0x00000003, PPC_POWER2)
5314 { 5306 {
5315 int rd = rD(ctx->opcode); 5307 int rd = rD(ctx->opcode);
5316 - TCGv t0 = tcg_temp_new();  
5317 - gen_addr_imm_index(t0, ctx, 0);  
5318 - gen_qemu_st64(cpu_fpr[rd], t0, ctx->mem_idx);  
5319 - tcg_gen_addi_tl(t0, t0, 8);  
5320 - gen_qemu_st64(cpu_fpr[(rd + 1) % 32], t0, ctx->mem_idx); 5308 + TCGv t0;
  5309 + gen_set_access_type(ctx, ACCESS_FLOAT);
  5310 + t0 = tcg_temp_new();
  5311 + gen_addr_imm_index(ctx, t0, 0);
  5312 + gen_qemu_st64(ctx, cpu_fpr[rd], t0);
  5313 + gen_addr_add(ctx, t0, t0, 8);
  5314 + gen_qemu_st64(ctx, cpu_fpr[(rd + 1) % 32], t0);
5321 tcg_temp_free(t0); 5315 tcg_temp_free(t0);
5322 } 5316 }
5323 5317
@@ -5326,16 +5320,18 @@ GEN_HANDLER(stfqu, 0x3D, 0xFF, 0xFF, 0x00000003, PPC_POWER2) @@ -5326,16 +5320,18 @@ GEN_HANDLER(stfqu, 0x3D, 0xFF, 0xFF, 0x00000003, PPC_POWER2)
5326 { 5320 {
5327 int ra = rA(ctx->opcode); 5321 int ra = rA(ctx->opcode);
5328 int rd = rD(ctx->opcode); 5322 int rd = rD(ctx->opcode);
5329 - TCGv t0 = tcg_temp_new();  
5330 - TCGv t1 = tcg_temp_new();  
5331 - gen_addr_imm_index(t0, ctx, 0);  
5332 - gen_qemu_st64(cpu_fpr[rd], t0, ctx->mem_idx);  
5333 - tcg_gen_addi_tl(t1, t0, 8);  
5334 - gen_qemu_st64(cpu_fpr[(rd + 1) % 32], t1, ctx->mem_idx); 5323 + TCGv t0, t1;
  5324 + gen_set_access_type(ctx, ACCESS_FLOAT);
  5325 + t0 = tcg_temp_new();
  5326 + gen_addr_imm_index(ctx, t0, 0);
  5327 + gen_qemu_st64(ctx, cpu_fpr[rd], t0);
  5328 + t1 = tcg_temp_new();
  5329 + gen_addr_add(ctx, t1, t0, 8);
  5330 + gen_qemu_st64(ctx, cpu_fpr[(rd + 1) % 32], t1);
  5331 + tcg_temp_free(t1);
5335 if (ra != 0) 5332 if (ra != 0)
5336 tcg_gen_mov_tl(cpu_gpr[ra], t0); 5333 tcg_gen_mov_tl(cpu_gpr[ra], t0);
5337 tcg_temp_free(t0); 5334 tcg_temp_free(t0);
5338 - tcg_temp_free(t1);  
5339 } 5335 }
5340 5336
5341 /* stfqux */ 5337 /* stfqux */
@@ -5343,27 +5339,31 @@ GEN_HANDLER(stfqux, 0x1F, 0x17, 0x1D, 0x00000001, PPC_POWER2) @@ -5343,27 +5339,31 @@ GEN_HANDLER(stfqux, 0x1F, 0x17, 0x1D, 0x00000001, PPC_POWER2)
5343 { 5339 {
5344 int ra = rA(ctx->opcode); 5340 int ra = rA(ctx->opcode);
5345 int rd = rD(ctx->opcode); 5341 int rd = rD(ctx->opcode);
5346 - TCGv t0 = tcg_temp_new();  
5347 - TCGv t1 = tcg_temp_new();  
5348 - gen_addr_reg_index(t0, ctx);  
5349 - gen_qemu_st64(cpu_fpr[rd], t0, ctx->mem_idx);  
5350 - tcg_gen_addi_tl(t1, t0, 8);  
5351 - gen_qemu_st64(cpu_fpr[(rd + 1) % 32], t1, ctx->mem_idx); 5342 + TCGv t0, t1;
  5343 + gen_set_access_type(ctx, ACCESS_FLOAT);
  5344 + t0 = tcg_temp_new();
  5345 + gen_addr_reg_index(ctx, t0);
  5346 + gen_qemu_st64(ctx, cpu_fpr[rd], t0);
  5347 + t1 = tcg_temp_new();
  5348 + gen_addr_add(ctx, t1, t0, 8);
  5349 + gen_qemu_st64(ctx, cpu_fpr[(rd + 1) % 32], t1);
  5350 + tcg_temp_free(t1);
5352 if (ra != 0) 5351 if (ra != 0)
5353 tcg_gen_mov_tl(cpu_gpr[ra], t0); 5352 tcg_gen_mov_tl(cpu_gpr[ra], t0);
5354 tcg_temp_free(t0); 5353 tcg_temp_free(t0);
5355 - tcg_temp_free(t1);  
5356 } 5354 }
5357 5355
5358 /* stfqx */ 5356 /* stfqx */
5359 GEN_HANDLER(stfqx, 0x1F, 0x17, 0x1C, 0x00000001, PPC_POWER2) 5357 GEN_HANDLER(stfqx, 0x1F, 0x17, 0x1C, 0x00000001, PPC_POWER2)
5360 { 5358 {
5361 int rd = rD(ctx->opcode); 5359 int rd = rD(ctx->opcode);
5362 - TCGv t0 = tcg_temp_new();  
5363 - gen_addr_reg_index(t0, ctx);  
5364 - gen_qemu_st64(cpu_fpr[rd], t0, ctx->mem_idx);  
5365 - tcg_gen_addi_tl(t0, t0, 8);  
5366 - gen_qemu_st64(cpu_fpr[(rd + 1) % 32], t0, ctx->mem_idx); 5360 + TCGv t0;
  5361 + gen_set_access_type(ctx, ACCESS_FLOAT);
  5362 + t0 = tcg_temp_new();
  5363 + gen_addr_reg_index(ctx, t0);
  5364 + gen_qemu_st64(ctx, cpu_fpr[rd], t0);
  5365 + gen_addr_add(ctx, t0, t0, 8);
  5366 + gen_qemu_st64(ctx, cpu_fpr[(rd + 1) % 32], t0);
5367 tcg_temp_free(t0); 5367 tcg_temp_free(t0);
5368 } 5368 }
5369 5369
@@ -5382,16 +5382,12 @@ GEN_HANDLER(tlbiva, 0x1F, 0x12, 0x18, 0x03FFF801, PPC_TLBIVA) @@ -5382,16 +5382,12 @@ GEN_HANDLER(tlbiva, 0x1F, 0x12, 0x18, 0x03FFF801, PPC_TLBIVA)
5382 GEN_EXCP_PRIVOPC(ctx); 5382 GEN_EXCP_PRIVOPC(ctx);
5383 #else 5383 #else
5384 TCGv t0; 5384 TCGv t0;
5385 - if (unlikely(!ctx->supervisor)) { 5385 + if (unlikely(!ctx->mem_idx)) {
5386 GEN_EXCP_PRIVOPC(ctx); 5386 GEN_EXCP_PRIVOPC(ctx);
5387 return; 5387 return;
5388 } 5388 }
5389 t0 = tcg_temp_new(); 5389 t0 = tcg_temp_new();
5390 - gen_addr_reg_index(t0, ctx);  
5391 -#if defined(TARGET_PPC64)  
5392 - if (!ctx->sf_mode)  
5393 - tcg_gen_ext32u_tl(t0, t0);  
5394 -#endif 5390 + gen_addr_reg_index(ctx, t0);
5395 gen_helper_tlbie(cpu_gpr[rB(ctx->opcode)]); 5391 gen_helper_tlbie(cpu_gpr[rB(ctx->opcode)]);
5396 tcg_temp_free(t0); 5392 tcg_temp_free(t0);
5397 #endif 5393 #endif
@@ -5619,7 +5615,7 @@ GEN_HANDLER(mfdcr, 0x1F, 0x03, 0x0A, 0x00000001, PPC_DCR) @@ -5619,7 +5615,7 @@ GEN_HANDLER(mfdcr, 0x1F, 0x03, 0x0A, 0x00000001, PPC_DCR)
5619 GEN_EXCP_PRIVREG(ctx); 5615 GEN_EXCP_PRIVREG(ctx);
5620 #else 5616 #else
5621 TCGv dcrn; 5617 TCGv dcrn;
5622 - if (unlikely(!ctx->supervisor)) { 5618 + if (unlikely(!ctx->mem_idx)) {
5623 GEN_EXCP_PRIVREG(ctx); 5619 GEN_EXCP_PRIVREG(ctx);
5624 return; 5620 return;
5625 } 5621 }
@@ -5638,7 +5634,7 @@ GEN_HANDLER(mtdcr, 0x1F, 0x03, 0x0E, 0x00000001, PPC_DCR) @@ -5638,7 +5634,7 @@ GEN_HANDLER(mtdcr, 0x1F, 0x03, 0x0E, 0x00000001, PPC_DCR)
5638 GEN_EXCP_PRIVREG(ctx); 5634 GEN_EXCP_PRIVREG(ctx);
5639 #else 5635 #else
5640 TCGv dcrn; 5636 TCGv dcrn;
5641 - if (unlikely(!ctx->supervisor)) { 5637 + if (unlikely(!ctx->mem_idx)) {
5642 GEN_EXCP_PRIVREG(ctx); 5638 GEN_EXCP_PRIVREG(ctx);
5643 return; 5639 return;
5644 } 5640 }
@@ -5657,7 +5653,7 @@ GEN_HANDLER(mfdcrx, 0x1F, 0x03, 0x08, 0x00000000, PPC_DCRX) @@ -5657,7 +5653,7 @@ GEN_HANDLER(mfdcrx, 0x1F, 0x03, 0x08, 0x00000000, PPC_DCRX)
5657 #if defined(CONFIG_USER_ONLY) 5653 #if defined(CONFIG_USER_ONLY)
5658 GEN_EXCP_PRIVREG(ctx); 5654 GEN_EXCP_PRIVREG(ctx);
5659 #else 5655 #else
5660 - if (unlikely(!ctx->supervisor)) { 5656 + if (unlikely(!ctx->mem_idx)) {
5661 GEN_EXCP_PRIVREG(ctx); 5657 GEN_EXCP_PRIVREG(ctx);
5662 return; 5658 return;
5663 } 5659 }
@@ -5675,7 +5671,7 @@ GEN_HANDLER(mtdcrx, 0x1F, 0x03, 0x0C, 0x00000000, PPC_DCRX) @@ -5675,7 +5671,7 @@ GEN_HANDLER(mtdcrx, 0x1F, 0x03, 0x0C, 0x00000000, PPC_DCRX)
5675 #if defined(CONFIG_USER_ONLY) 5671 #if defined(CONFIG_USER_ONLY)
5676 GEN_EXCP_PRIVREG(ctx); 5672 GEN_EXCP_PRIVREG(ctx);
5677 #else 5673 #else
5678 - if (unlikely(!ctx->supervisor)) { 5674 + if (unlikely(!ctx->mem_idx)) {
5679 GEN_EXCP_PRIVREG(ctx); 5675 GEN_EXCP_PRIVREG(ctx);
5680 return; 5676 return;
5681 } 5677 }
@@ -5710,7 +5706,7 @@ GEN_HANDLER(dccci, 0x1F, 0x06, 0x0E, 0x03E00001, PPC_4xx_COMMON) @@ -5710,7 +5706,7 @@ GEN_HANDLER(dccci, 0x1F, 0x06, 0x0E, 0x03E00001, PPC_4xx_COMMON)
5710 #if defined(CONFIG_USER_ONLY) 5706 #if defined(CONFIG_USER_ONLY)
5711 GEN_EXCP_PRIVOPC(ctx); 5707 GEN_EXCP_PRIVOPC(ctx);
5712 #else 5708 #else
5713 - if (unlikely(!ctx->supervisor)) { 5709 + if (unlikely(!ctx->mem_idx)) {
5714 GEN_EXCP_PRIVOPC(ctx); 5710 GEN_EXCP_PRIVOPC(ctx);
5715 return; 5711 return;
5716 } 5712 }
@@ -5725,15 +5721,15 @@ GEN_HANDLER(dcread, 0x1F, 0x06, 0x0F, 0x00000001, PPC_4xx_COMMON) @@ -5725,15 +5721,15 @@ GEN_HANDLER(dcread, 0x1F, 0x06, 0x0F, 0x00000001, PPC_4xx_COMMON)
5725 GEN_EXCP_PRIVOPC(ctx); 5721 GEN_EXCP_PRIVOPC(ctx);
5726 #else 5722 #else
5727 TCGv EA, val; 5723 TCGv EA, val;
5728 - if (unlikely(!ctx->supervisor)) { 5724 + if (unlikely(!ctx->mem_idx)) {
5729 GEN_EXCP_PRIVOPC(ctx); 5725 GEN_EXCP_PRIVOPC(ctx);
5730 return; 5726 return;
5731 } 5727 }
  5728 + gen_set_access_type(ctx, ACCESS_CACHE);
5732 EA = tcg_temp_new(); 5729 EA = tcg_temp_new();
5733 - gen_set_access_type(ACCESS_CACHE);  
5734 - gen_addr_reg_index(EA, ctx); 5730 + gen_addr_reg_index(ctx, EA);
5735 val = tcg_temp_new(); 5731 val = tcg_temp_new();
5736 - gen_qemu_ld32u(val, EA, ctx->mem_idx); 5732 + gen_qemu_ld32u(ctx, val, EA);
5737 tcg_temp_free(val); 5733 tcg_temp_free(val);
5738 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], EA); 5734 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], EA);
5739 tcg_temp_free(EA); 5735 tcg_temp_free(EA);
@@ -5755,7 +5751,7 @@ GEN_HANDLER(iccci, 0x1F, 0x06, 0x1E, 0x00000001, PPC_4xx_COMMON) @@ -5755,7 +5751,7 @@ GEN_HANDLER(iccci, 0x1F, 0x06, 0x1E, 0x00000001, PPC_4xx_COMMON)
5755 #if defined(CONFIG_USER_ONLY) 5751 #if defined(CONFIG_USER_ONLY)
5756 GEN_EXCP_PRIVOPC(ctx); 5752 GEN_EXCP_PRIVOPC(ctx);
5757 #else 5753 #else
5758 - if (unlikely(!ctx->supervisor)) { 5754 + if (unlikely(!ctx->mem_idx)) {
5759 GEN_EXCP_PRIVOPC(ctx); 5755 GEN_EXCP_PRIVOPC(ctx);
5760 return; 5756 return;
5761 } 5757 }
@@ -5769,7 +5765,7 @@ GEN_HANDLER(icread, 0x1F, 0x06, 0x1F, 0x03E00001, PPC_4xx_COMMON) @@ -5769,7 +5765,7 @@ GEN_HANDLER(icread, 0x1F, 0x06, 0x1F, 0x03E00001, PPC_4xx_COMMON)
5769 #if defined(CONFIG_USER_ONLY) 5765 #if defined(CONFIG_USER_ONLY)
5770 GEN_EXCP_PRIVOPC(ctx); 5766 GEN_EXCP_PRIVOPC(ctx);
5771 #else 5767 #else
5772 - if (unlikely(!ctx->supervisor)) { 5768 + if (unlikely(!ctx->mem_idx)) {
5773 GEN_EXCP_PRIVOPC(ctx); 5769 GEN_EXCP_PRIVOPC(ctx);
5774 return; 5770 return;
5775 } 5771 }
@@ -5777,13 +5773,13 @@ GEN_HANDLER(icread, 0x1F, 0x06, 0x1F, 0x03E00001, PPC_4xx_COMMON) @@ -5777,13 +5773,13 @@ GEN_HANDLER(icread, 0x1F, 0x06, 0x1F, 0x03E00001, PPC_4xx_COMMON)
5777 #endif 5773 #endif
5778 } 5774 }
5779 5775
5780 -/* rfci (supervisor only) */ 5776 +/* rfci (mem_idx only) */
5781 GEN_HANDLER2(rfci_40x, "rfci", 0x13, 0x13, 0x01, 0x03FF8001, PPC_40x_EXCP) 5777 GEN_HANDLER2(rfci_40x, "rfci", 0x13, 0x13, 0x01, 0x03FF8001, PPC_40x_EXCP)
5782 { 5778 {
5783 #if defined(CONFIG_USER_ONLY) 5779 #if defined(CONFIG_USER_ONLY)
5784 GEN_EXCP_PRIVOPC(ctx); 5780 GEN_EXCP_PRIVOPC(ctx);
5785 #else 5781 #else
5786 - if (unlikely(!ctx->supervisor)) { 5782 + if (unlikely(!ctx->mem_idx)) {
5787 GEN_EXCP_PRIVOPC(ctx); 5783 GEN_EXCP_PRIVOPC(ctx);
5788 return; 5784 return;
5789 } 5785 }
@@ -5798,7 +5794,7 @@ GEN_HANDLER(rfci, 0x13, 0x13, 0x01, 0x03FF8001, PPC_BOOKE) @@ -5798,7 +5794,7 @@ GEN_HANDLER(rfci, 0x13, 0x13, 0x01, 0x03FF8001, PPC_BOOKE)
5798 #if defined(CONFIG_USER_ONLY) 5794 #if defined(CONFIG_USER_ONLY)
5799 GEN_EXCP_PRIVOPC(ctx); 5795 GEN_EXCP_PRIVOPC(ctx);
5800 #else 5796 #else
5801 - if (unlikely(!ctx->supervisor)) { 5797 + if (unlikely(!ctx->mem_idx)) {
5802 GEN_EXCP_PRIVOPC(ctx); 5798 GEN_EXCP_PRIVOPC(ctx);
5803 return; 5799 return;
5804 } 5800 }
@@ -5815,7 +5811,7 @@ GEN_HANDLER(rfdi, 0x13, 0x07, 0x01, 0x03FF8001, PPC_RFDI) @@ -5815,7 +5811,7 @@ GEN_HANDLER(rfdi, 0x13, 0x07, 0x01, 0x03FF8001, PPC_RFDI)
5815 #if defined(CONFIG_USER_ONLY) 5811 #if defined(CONFIG_USER_ONLY)
5816 GEN_EXCP_PRIVOPC(ctx); 5812 GEN_EXCP_PRIVOPC(ctx);
5817 #else 5813 #else
5818 - if (unlikely(!ctx->supervisor)) { 5814 + if (unlikely(!ctx->mem_idx)) {
5819 GEN_EXCP_PRIVOPC(ctx); 5815 GEN_EXCP_PRIVOPC(ctx);
5820 return; 5816 return;
5821 } 5817 }
@@ -5831,7 +5827,7 @@ GEN_HANDLER(rfmci, 0x13, 0x06, 0x01, 0x03FF8001, PPC_RFMCI) @@ -5831,7 +5827,7 @@ GEN_HANDLER(rfmci, 0x13, 0x06, 0x01, 0x03FF8001, PPC_RFMCI)
5831 #if defined(CONFIG_USER_ONLY) 5827 #if defined(CONFIG_USER_ONLY)
5832 GEN_EXCP_PRIVOPC(ctx); 5828 GEN_EXCP_PRIVOPC(ctx);
5833 #else 5829 #else
5834 - if (unlikely(!ctx->supervisor)) { 5830 + if (unlikely(!ctx->mem_idx)) {
5835 GEN_EXCP_PRIVOPC(ctx); 5831 GEN_EXCP_PRIVOPC(ctx);
5836 return; 5832 return;
5837 } 5833 }
@@ -5848,7 +5844,7 @@ GEN_HANDLER2(tlbre_40x, &quot;tlbre&quot;, 0x1F, 0x12, 0x1D, 0x00000001, PPC_40x_TLB) @@ -5848,7 +5844,7 @@ GEN_HANDLER2(tlbre_40x, &quot;tlbre&quot;, 0x1F, 0x12, 0x1D, 0x00000001, PPC_40x_TLB)
5848 #if defined(CONFIG_USER_ONLY) 5844 #if defined(CONFIG_USER_ONLY)
5849 GEN_EXCP_PRIVOPC(ctx); 5845 GEN_EXCP_PRIVOPC(ctx);
5850 #else 5846 #else
5851 - if (unlikely(!ctx->supervisor)) { 5847 + if (unlikely(!ctx->mem_idx)) {
5852 GEN_EXCP_PRIVOPC(ctx); 5848 GEN_EXCP_PRIVOPC(ctx);
5853 return; 5849 return;
5854 } 5850 }
@@ -5873,12 +5869,12 @@ GEN_HANDLER2(tlbsx_40x, &quot;tlbsx&quot;, 0x1F, 0x12, 0x1C, 0x00000000, PPC_40x_TLB) @@ -5873,12 +5869,12 @@ GEN_HANDLER2(tlbsx_40x, &quot;tlbsx&quot;, 0x1F, 0x12, 0x1C, 0x00000000, PPC_40x_TLB)
5873 GEN_EXCP_PRIVOPC(ctx); 5869 GEN_EXCP_PRIVOPC(ctx);
5874 #else 5870 #else
5875 TCGv t0; 5871 TCGv t0;
5876 - if (unlikely(!ctx->supervisor)) { 5872 + if (unlikely(!ctx->mem_idx)) {
5877 GEN_EXCP_PRIVOPC(ctx); 5873 GEN_EXCP_PRIVOPC(ctx);
5878 return; 5874 return;
5879 } 5875 }
5880 t0 = tcg_temp_new(); 5876 t0 = tcg_temp_new();
5881 - gen_addr_reg_index(t0, ctx); 5877 + gen_addr_reg_index(ctx, t0);
5882 gen_helper_4xx_tlbsx(cpu_gpr[rD(ctx->opcode)], t0); 5878 gen_helper_4xx_tlbsx(cpu_gpr[rD(ctx->opcode)], t0);
5883 tcg_temp_free(t0); 5879 tcg_temp_free(t0);
5884 if (Rc(ctx->opcode)) { 5880 if (Rc(ctx->opcode)) {
@@ -5899,7 +5895,7 @@ GEN_HANDLER2(tlbwe_40x, &quot;tlbwe&quot;, 0x1F, 0x12, 0x1E, 0x00000001, PPC_40x_TLB) @@ -5899,7 +5895,7 @@ GEN_HANDLER2(tlbwe_40x, &quot;tlbwe&quot;, 0x1F, 0x12, 0x1E, 0x00000001, PPC_40x_TLB)
5899 #if defined(CONFIG_USER_ONLY) 5895 #if defined(CONFIG_USER_ONLY)
5900 GEN_EXCP_PRIVOPC(ctx); 5896 GEN_EXCP_PRIVOPC(ctx);
5901 #else 5897 #else
5902 - if (unlikely(!ctx->supervisor)) { 5898 + if (unlikely(!ctx->mem_idx)) {
5903 GEN_EXCP_PRIVOPC(ctx); 5899 GEN_EXCP_PRIVOPC(ctx);
5904 return; 5900 return;
5905 } 5901 }
@@ -5924,7 +5920,7 @@ GEN_HANDLER2(tlbre_440, &quot;tlbre&quot;, 0x1F, 0x12, 0x1D, 0x00000001, PPC_BOOKE) @@ -5924,7 +5920,7 @@ GEN_HANDLER2(tlbre_440, &quot;tlbre&quot;, 0x1F, 0x12, 0x1D, 0x00000001, PPC_BOOKE)
5924 #if defined(CONFIG_USER_ONLY) 5920 #if defined(CONFIG_USER_ONLY)
5925 GEN_EXCP_PRIVOPC(ctx); 5921 GEN_EXCP_PRIVOPC(ctx);
5926 #else 5922 #else
5927 - if (unlikely(!ctx->supervisor)) { 5923 + if (unlikely(!ctx->mem_idx)) {
5928 GEN_EXCP_PRIVOPC(ctx); 5924 GEN_EXCP_PRIVOPC(ctx);
5929 return; 5925 return;
5930 } 5926 }
@@ -5952,12 +5948,12 @@ GEN_HANDLER2(tlbsx_440, &quot;tlbsx&quot;, 0x1F, 0x12, 0x1C, 0x00000000, PPC_BOOKE) @@ -5952,12 +5948,12 @@ GEN_HANDLER2(tlbsx_440, &quot;tlbsx&quot;, 0x1F, 0x12, 0x1C, 0x00000000, PPC_BOOKE)
5952 GEN_EXCP_PRIVOPC(ctx); 5948 GEN_EXCP_PRIVOPC(ctx);
5953 #else 5949 #else
5954 TCGv t0; 5950 TCGv t0;
5955 - if (unlikely(!ctx->supervisor)) { 5951 + if (unlikely(!ctx->mem_idx)) {
5956 GEN_EXCP_PRIVOPC(ctx); 5952 GEN_EXCP_PRIVOPC(ctx);
5957 return; 5953 return;
5958 } 5954 }
5959 t0 = tcg_temp_new(); 5955 t0 = tcg_temp_new();
5960 - gen_addr_reg_index(t0, ctx); 5956 + gen_addr_reg_index(ctx, t0);
5961 gen_helper_440_tlbsx(cpu_gpr[rD(ctx->opcode)], t0); 5957 gen_helper_440_tlbsx(cpu_gpr[rD(ctx->opcode)], t0);
5962 tcg_temp_free(t0); 5958 tcg_temp_free(t0);
5963 if (Rc(ctx->opcode)) { 5959 if (Rc(ctx->opcode)) {
@@ -5978,7 +5974,7 @@ GEN_HANDLER2(tlbwe_440, &quot;tlbwe&quot;, 0x1F, 0x12, 0x1E, 0x00000001, PPC_BOOKE) @@ -5978,7 +5974,7 @@ GEN_HANDLER2(tlbwe_440, &quot;tlbwe&quot;, 0x1F, 0x12, 0x1E, 0x00000001, PPC_BOOKE)
5978 #if defined(CONFIG_USER_ONLY) 5974 #if defined(CONFIG_USER_ONLY)
5979 GEN_EXCP_PRIVOPC(ctx); 5975 GEN_EXCP_PRIVOPC(ctx);
5980 #else 5976 #else
5981 - if (unlikely(!ctx->supervisor)) { 5977 + if (unlikely(!ctx->mem_idx)) {
5982 GEN_EXCP_PRIVOPC(ctx); 5978 GEN_EXCP_PRIVOPC(ctx);
5983 return; 5979 return;
5984 } 5980 }
@@ -6006,7 +6002,7 @@ GEN_HANDLER(wrtee, 0x1F, 0x03, 0x04, 0x000FFC01, PPC_WRTEE) @@ -6006,7 +6002,7 @@ GEN_HANDLER(wrtee, 0x1F, 0x03, 0x04, 0x000FFC01, PPC_WRTEE)
6006 GEN_EXCP_PRIVOPC(ctx); 6002 GEN_EXCP_PRIVOPC(ctx);
6007 #else 6003 #else
6008 TCGv t0; 6004 TCGv t0;
6009 - if (unlikely(!ctx->supervisor)) { 6005 + if (unlikely(!ctx->mem_idx)) {
6010 GEN_EXCP_PRIVOPC(ctx); 6006 GEN_EXCP_PRIVOPC(ctx);
6011 return; 6007 return;
6012 } 6008 }
@@ -6028,7 +6024,7 @@ GEN_HANDLER(wrteei, 0x1F, 0x03, 0x05, 0x000EFC01, PPC_WRTEE) @@ -6028,7 +6024,7 @@ GEN_HANDLER(wrteei, 0x1F, 0x03, 0x05, 0x000EFC01, PPC_WRTEE)
6028 #if defined(CONFIG_USER_ONLY) 6024 #if defined(CONFIG_USER_ONLY)
6029 GEN_EXCP_PRIVOPC(ctx); 6025 GEN_EXCP_PRIVOPC(ctx);
6030 #else 6026 #else
6031 - if (unlikely(!ctx->supervisor)) { 6027 + if (unlikely(!ctx->mem_idx)) {
6032 GEN_EXCP_PRIVOPC(ctx); 6028 GEN_EXCP_PRIVOPC(ctx);
6033 return; 6029 return;
6034 } 6030 }
@@ -6084,17 +6080,18 @@ GEN_HANDLER(name, 0x1F, opc2, opc3, 0x00000001, PPC_ALTIVEC) \ @@ -6084,17 +6080,18 @@ GEN_HANDLER(name, 0x1F, opc2, opc3, 0x00000001, PPC_ALTIVEC) \
6084 GEN_EXCP_NO_VR(ctx); \ 6080 GEN_EXCP_NO_VR(ctx); \
6085 return; \ 6081 return; \
6086 } \ 6082 } \
  6083 + gen_set_access_type(ctx, ACCESS_INT); \
6087 EA = tcg_temp_new(); \ 6084 EA = tcg_temp_new(); \
6088 - gen_addr_reg_index(EA, ctx); \ 6085 + gen_addr_reg_index(ctx, EA); \
6089 tcg_gen_andi_tl(EA, EA, ~0xf); \ 6086 tcg_gen_andi_tl(EA, EA, ~0xf); \
6090 - if (ctx->mem_idx & 1) { \  
6091 - gen_qemu_ld64(cpu_avrl[rD(ctx->opcode)], EA, ctx->mem_idx); \ 6087 + if (ctx->le_mode) { \
  6088 + gen_qemu_ld64(ctx, cpu_avrl[rD(ctx->opcode)], EA); \
6092 tcg_gen_addi_tl(EA, EA, 8); \ 6089 tcg_gen_addi_tl(EA, EA, 8); \
6093 - gen_qemu_ld64(cpu_avrh[rD(ctx->opcode)], EA, ctx->mem_idx); \ 6090 + gen_qemu_ld64(ctx, cpu_avrh[rD(ctx->opcode)], EA); \
6094 } else { \ 6091 } else { \
6095 - gen_qemu_ld64(cpu_avrh[rD(ctx->opcode)], EA, ctx->mem_idx); \ 6092 + gen_qemu_ld64(ctx, cpu_avrh[rD(ctx->opcode)], EA); \
6096 tcg_gen_addi_tl(EA, EA, 8); \ 6093 tcg_gen_addi_tl(EA, EA, 8); \
6097 - gen_qemu_ld64(cpu_avrl[rD(ctx->opcode)], EA, ctx->mem_idx); \ 6094 + gen_qemu_ld64(ctx, cpu_avrl[rD(ctx->opcode)], EA); \
6098 } \ 6095 } \
6099 tcg_temp_free(EA); \ 6096 tcg_temp_free(EA); \
6100 } 6097 }
@@ -6107,17 +6104,18 @@ GEN_HANDLER(st##name, 0x1F, opc2, opc3, 0x00000001, PPC_ALTIVEC) \ @@ -6107,17 +6104,18 @@ GEN_HANDLER(st##name, 0x1F, opc2, opc3, 0x00000001, PPC_ALTIVEC) \
6107 GEN_EXCP_NO_VR(ctx); \ 6104 GEN_EXCP_NO_VR(ctx); \
6108 return; \ 6105 return; \
6109 } \ 6106 } \
  6107 + gen_set_access_type(ctx, ACCESS_INT); \
6110 EA = tcg_temp_new(); \ 6108 EA = tcg_temp_new(); \
6111 - gen_addr_reg_index(EA, ctx); \ 6109 + gen_addr_reg_index(ctx, EA); \
6112 tcg_gen_andi_tl(EA, EA, ~0xf); \ 6110 tcg_gen_andi_tl(EA, EA, ~0xf); \
6113 - if (ctx->mem_idx & 1) { \  
6114 - gen_qemu_st64(cpu_avrl[rD(ctx->opcode)], EA, ctx->mem_idx); \ 6111 + if (ctx->le_mode) { \
  6112 + gen_qemu_st64(ctx, cpu_avrl[rD(ctx->opcode)], EA); \
6115 tcg_gen_addi_tl(EA, EA, 8); \ 6113 tcg_gen_addi_tl(EA, EA, 8); \
6116 - gen_qemu_st64(cpu_avrh[rD(ctx->opcode)], EA, ctx->mem_idx); \ 6114 + gen_qemu_st64(ctx, cpu_avrh[rD(ctx->opcode)], EA); \
6117 } else { \ 6115 } else { \
6118 - gen_qemu_st64(cpu_avrh[rD(ctx->opcode)], EA, ctx->mem_idx); \ 6116 + gen_qemu_st64(ctx, cpu_avrh[rD(ctx->opcode)], EA); \
6119 tcg_gen_addi_tl(EA, EA, 8); \ 6117 tcg_gen_addi_tl(EA, EA, 8); \
6120 - gen_qemu_st64(cpu_avrl[rD(ctx->opcode)], EA, ctx->mem_idx); \ 6118 + gen_qemu_st64(ctx, cpu_avrl[rD(ctx->opcode)], EA); \
6121 } \ 6119 } \
6122 tcg_temp_free(EA); \ 6120 tcg_temp_free(EA); \
6123 } 6121 }
@@ -6734,23 +6732,29 @@ GEN_SPE(evcmpltu, evcmplts, 0x19, 0x08, 0x00600000, PPC_SPE); //// @@ -6734,23 +6732,29 @@ GEN_SPE(evcmpltu, evcmplts, 0x19, 0x08, 0x00600000, PPC_SPE); ////
6734 GEN_SPE(evcmpeq, speundef, 0x1A, 0x08, 0x00600000, PPC_SPE); //// 6732 GEN_SPE(evcmpeq, speundef, 0x1A, 0x08, 0x00600000, PPC_SPE); ////
6735 6733
6736 /* SPE load and stores */ 6734 /* SPE load and stores */
6737 -static always_inline void gen_addr_spe_imm_index (TCGv EA, DisasContext *ctx, int sh) 6735 +static always_inline void gen_addr_spe_imm_index (DisasContext *ctx, TCGv EA, int sh)
6738 { 6736 {
6739 target_ulong uimm = rB(ctx->opcode); 6737 target_ulong uimm = rB(ctx->opcode);
6740 6738
6741 - if (rA(ctx->opcode) == 0) 6739 + if (rA(ctx->opcode) == 0) {
6742 tcg_gen_movi_tl(EA, uimm << sh); 6740 tcg_gen_movi_tl(EA, uimm << sh);
6743 - else 6741 + } else {
6744 tcg_gen_addi_tl(EA, cpu_gpr[rA(ctx->opcode)], uimm << sh); 6742 tcg_gen_addi_tl(EA, cpu_gpr[rA(ctx->opcode)], uimm << sh);
  6743 +#if defined(TARGET_PPC64)
  6744 + if (!ctx->sf_mode) {
  6745 + tcg_gen_ext32u_tl(EA, EA);
  6746 + }
  6747 +#endif
  6748 + }
6745 } 6749 }
6746 6750
6747 static always_inline void gen_op_evldd(DisasContext *ctx, TCGv addr) 6751 static always_inline void gen_op_evldd(DisasContext *ctx, TCGv addr)
6748 { 6752 {
6749 #if defined(TARGET_PPC64) 6753 #if defined(TARGET_PPC64)
6750 - gen_qemu_ld64(cpu_gpr[rD(ctx->opcode)], addr, ctx->mem_idx); 6754 + gen_qemu_ld64(ctx, cpu_gpr[rD(ctx->opcode)], addr);
6751 #else 6755 #else
6752 TCGv_i64 t0 = tcg_temp_new_i64(); 6756 TCGv_i64 t0 = tcg_temp_new_i64();
6753 - gen_qemu_ld64(t0, addr, ctx->mem_idx); 6757 + gen_qemu_ld64(ctx, t0, addr);
6754 tcg_gen_trunc_i64_i32(cpu_gpr[rD(ctx->opcode)], t0); 6758 tcg_gen_trunc_i64_i32(cpu_gpr[rD(ctx->opcode)], t0);
6755 tcg_gen_shri_i64(t0, t0, 32); 6759 tcg_gen_shri_i64(t0, t0, 32);
6756 tcg_gen_trunc_i64_i32(cpu_gprh[rD(ctx->opcode)], t0); 6760 tcg_gen_trunc_i64_i32(cpu_gprh[rD(ctx->opcode)], t0);
@@ -6762,16 +6766,16 @@ static always_inline void gen_op_evldw(DisasContext *ctx, TCGv addr) @@ -6762,16 +6766,16 @@ static always_inline void gen_op_evldw(DisasContext *ctx, TCGv addr)
6762 { 6766 {
6763 #if defined(TARGET_PPC64) 6767 #if defined(TARGET_PPC64)
6764 TCGv t0 = tcg_temp_new(); 6768 TCGv t0 = tcg_temp_new();
6765 - gen_qemu_ld32u(t0, addr, ctx->mem_idx); 6769 + gen_qemu_ld32u(ctx, t0, addr);
6766 tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], t0, 32); 6770 tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], t0, 32);
6767 - tcg_gen_addi_tl(addr, addr, 4);  
6768 - gen_qemu_ld32u(t0, addr, ctx->mem_idx); 6771 + gen_addr_add(ctx, addr, addr, 4);
  6772 + gen_qemu_ld32u(ctx, t0, addr);
6769 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0); 6773 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
6770 tcg_temp_free(t0); 6774 tcg_temp_free(t0);
6771 #else 6775 #else
6772 - gen_qemu_ld32u(cpu_gprh[rD(ctx->opcode)], addr, ctx->mem_idx);  
6773 - tcg_gen_addi_tl(addr, addr, 4);  
6774 - gen_qemu_ld32u(cpu_gpr[rD(ctx->opcode)], addr, ctx->mem_idx); 6776 + gen_qemu_ld32u(ctx, cpu_gprh[rD(ctx->opcode)], addr);
  6777 + gen_addr_add(ctx, addr, addr, 4);
  6778 + gen_qemu_ld32u(ctx, cpu_gpr[rD(ctx->opcode)], addr);
6775 #endif 6779 #endif
6776 } 6780 }
6777 6781
@@ -6779,30 +6783,30 @@ static always_inline void gen_op_evldh(DisasContext *ctx, TCGv addr) @@ -6779,30 +6783,30 @@ static always_inline void gen_op_evldh(DisasContext *ctx, TCGv addr)
6779 { 6783 {
6780 TCGv t0 = tcg_temp_new(); 6784 TCGv t0 = tcg_temp_new();
6781 #if defined(TARGET_PPC64) 6785 #if defined(TARGET_PPC64)
6782 - gen_qemu_ld16u(t0, addr, ctx->mem_idx); 6786 + gen_qemu_ld16u(ctx, t0, addr);
6783 tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], t0, 48); 6787 tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], t0, 48);
6784 - tcg_gen_addi_tl(addr, addr, 2);  
6785 - gen_qemu_ld16u(t0, addr, ctx->mem_idx); 6788 + gen_addr_add(ctx, addr, addr, 2);
  6789 + gen_qemu_ld16u(ctx, t0, addr);
6786 tcg_gen_shli_tl(t0, t0, 32); 6790 tcg_gen_shli_tl(t0, t0, 32);
6787 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0); 6791 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
6788 - tcg_gen_addi_tl(addr, addr, 2);  
6789 - gen_qemu_ld16u(t0, addr, ctx->mem_idx); 6792 + gen_addr_add(ctx, addr, addr, 2);
  6793 + gen_qemu_ld16u(ctx, t0, addr);
6790 tcg_gen_shli_tl(t0, t0, 16); 6794 tcg_gen_shli_tl(t0, t0, 16);
6791 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0); 6795 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
6792 - tcg_gen_addi_tl(addr, addr, 2);  
6793 - gen_qemu_ld16u(t0, addr, ctx->mem_idx); 6796 + gen_addr_add(ctx, addr, addr, 2);
  6797 + gen_qemu_ld16u(ctx, t0, addr);
6794 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0); 6798 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
6795 #else 6799 #else
6796 - gen_qemu_ld16u(t0, addr, ctx->mem_idx); 6800 + gen_qemu_ld16u(ctx, t0, addr);
6797 tcg_gen_shli_tl(cpu_gprh[rD(ctx->opcode)], t0, 16); 6801 tcg_gen_shli_tl(cpu_gprh[rD(ctx->opcode)], t0, 16);
6798 - tcg_gen_addi_tl(addr, addr, 2);  
6799 - gen_qemu_ld16u(t0, addr, ctx->mem_idx); 6802 + gen_addr_add(ctx, addr, addr, 2);
  6803 + gen_qemu_ld16u(ctx, t0, addr);
6800 tcg_gen_or_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rD(ctx->opcode)], t0); 6804 tcg_gen_or_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rD(ctx->opcode)], t0);
6801 - tcg_gen_addi_tl(addr, addr, 2);  
6802 - gen_qemu_ld16u(t0, addr, ctx->mem_idx); 6805 + gen_addr_add(ctx, addr, addr, 2);
  6806 + gen_qemu_ld16u(ctx, t0, addr);
6803 tcg_gen_shli_tl(cpu_gprh[rD(ctx->opcode)], t0, 16); 6807 tcg_gen_shli_tl(cpu_gprh[rD(ctx->opcode)], t0, 16);
6804 - tcg_gen_addi_tl(addr, addr, 2);  
6805 - gen_qemu_ld16u(t0, addr, ctx->mem_idx); 6808 + gen_addr_add(ctx, addr, addr, 2);
  6809 + gen_qemu_ld16u(ctx, t0, addr);
6806 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0); 6810 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
6807 #endif 6811 #endif
6808 tcg_temp_free(t0); 6812 tcg_temp_free(t0);
@@ -6811,7 +6815,7 @@ static always_inline void gen_op_evldh(DisasContext *ctx, TCGv addr) @@ -6811,7 +6815,7 @@ static always_inline void gen_op_evldh(DisasContext *ctx, TCGv addr)
6811 static always_inline void gen_op_evlhhesplat(DisasContext *ctx, TCGv addr) 6815 static always_inline void gen_op_evlhhesplat(DisasContext *ctx, TCGv addr)
6812 { 6816 {
6813 TCGv t0 = tcg_temp_new(); 6817 TCGv t0 = tcg_temp_new();
6814 - gen_qemu_ld16u(t0, addr, ctx->mem_idx); 6818 + gen_qemu_ld16u(ctx, t0, addr);
6815 #if defined(TARGET_PPC64) 6819 #if defined(TARGET_PPC64)
6816 tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], t0, 48); 6820 tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], t0, 48);
6817 tcg_gen_shli_tl(t0, t0, 16); 6821 tcg_gen_shli_tl(t0, t0, 16);
@@ -6827,7 +6831,7 @@ static always_inline void gen_op_evlhhesplat(DisasContext *ctx, TCGv addr) @@ -6827,7 +6831,7 @@ static always_inline void gen_op_evlhhesplat(DisasContext *ctx, TCGv addr)
6827 static always_inline void gen_op_evlhhousplat(DisasContext *ctx, TCGv addr) 6831 static always_inline void gen_op_evlhhousplat(DisasContext *ctx, TCGv addr)
6828 { 6832 {
6829 TCGv t0 = tcg_temp_new(); 6833 TCGv t0 = tcg_temp_new();
6830 - gen_qemu_ld16u(t0, addr, ctx->mem_idx); 6834 + gen_qemu_ld16u(ctx, t0, addr);
6831 #if defined(TARGET_PPC64) 6835 #if defined(TARGET_PPC64)
6832 tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], t0, 32); 6836 tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], t0, 32);
6833 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0); 6837 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
@@ -6841,7 +6845,7 @@ static always_inline void gen_op_evlhhousplat(DisasContext *ctx, TCGv addr) @@ -6841,7 +6845,7 @@ static always_inline void gen_op_evlhhousplat(DisasContext *ctx, TCGv addr)
6841 static always_inline void gen_op_evlhhossplat(DisasContext *ctx, TCGv addr) 6845 static always_inline void gen_op_evlhhossplat(DisasContext *ctx, TCGv addr)
6842 { 6846 {
6843 TCGv t0 = tcg_temp_new(); 6847 TCGv t0 = tcg_temp_new();
6844 - gen_qemu_ld16s(t0, addr, ctx->mem_idx); 6848 + gen_qemu_ld16s(ctx, t0, addr);
6845 #if defined(TARGET_PPC64) 6849 #if defined(TARGET_PPC64)
6846 tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], t0, 32); 6850 tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], t0, 32);
6847 tcg_gen_ext32u_tl(t0, t0); 6851 tcg_gen_ext32u_tl(t0, t0);
@@ -6857,16 +6861,17 @@ static always_inline void gen_op_evlwhe(DisasContext *ctx, TCGv addr) @@ -6857,16 +6861,17 @@ static always_inline void gen_op_evlwhe(DisasContext *ctx, TCGv addr)
6857 { 6861 {
6858 TCGv t0 = tcg_temp_new(); 6862 TCGv t0 = tcg_temp_new();
6859 #if defined(TARGET_PPC64) 6863 #if defined(TARGET_PPC64)
6860 - gen_qemu_ld16u(t0, addr, ctx->mem_idx); 6864 + gen_qemu_ld16u(ctx, t0, addr);
6861 tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], t0, 48); 6865 tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], t0, 48);
6862 - gen_qemu_ld16u(t0, addr, ctx->mem_idx); 6866 + gen_addr_add(ctx, addr, addr, 2);
  6867 + gen_qemu_ld16u(ctx, t0, addr);
6863 tcg_gen_shli_tl(t0, t0, 16); 6868 tcg_gen_shli_tl(t0, t0, 16);
6864 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0); 6869 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
6865 #else 6870 #else
6866 - gen_qemu_ld16u(t0, addr, ctx->mem_idx); 6871 + gen_qemu_ld16u(ctx, t0, addr);
6867 tcg_gen_shli_tl(cpu_gprh[rD(ctx->opcode)], t0, 16); 6872 tcg_gen_shli_tl(cpu_gprh[rD(ctx->opcode)], t0, 16);
6868 - tcg_gen_addi_tl(addr, addr, 2);  
6869 - gen_qemu_ld16u(t0, addr, ctx->mem_idx); 6873 + gen_addr_add(ctx, addr, addr, 2);
  6874 + gen_qemu_ld16u(ctx, t0, addr);
6870 tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], t0, 16); 6875 tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], t0, 16);
6871 #endif 6876 #endif
6872 tcg_temp_free(t0); 6877 tcg_temp_free(t0);
@@ -6876,16 +6881,16 @@ static always_inline void gen_op_evlwhou(DisasContext *ctx, TCGv addr) @@ -6876,16 +6881,16 @@ static always_inline void gen_op_evlwhou(DisasContext *ctx, TCGv addr)
6876 { 6881 {
6877 #if defined(TARGET_PPC64) 6882 #if defined(TARGET_PPC64)
6878 TCGv t0 = tcg_temp_new(); 6883 TCGv t0 = tcg_temp_new();
6879 - gen_qemu_ld16u(cpu_gpr[rD(ctx->opcode)], addr, ctx->mem_idx);  
6880 - tcg_gen_addi_tl(addr, addr, 2);  
6881 - gen_qemu_ld16u(t0, addr, ctx->mem_idx); 6884 + gen_qemu_ld16u(ctx, cpu_gpr[rD(ctx->opcode)], addr);
  6885 + gen_addr_add(ctx, addr, addr, 2);
  6886 + gen_qemu_ld16u(ctx, t0, addr);
6882 tcg_gen_shli_tl(t0, t0, 32); 6887 tcg_gen_shli_tl(t0, t0, 32);
6883 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0); 6888 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
6884 tcg_temp_free(t0); 6889 tcg_temp_free(t0);
6885 #else 6890 #else
6886 - gen_qemu_ld16u(cpu_gprh[rD(ctx->opcode)], addr, ctx->mem_idx);  
6887 - tcg_gen_addi_tl(addr, addr, 2);  
6888 - gen_qemu_ld16u(cpu_gpr[rD(ctx->opcode)], addr, ctx->mem_idx); 6891 + gen_qemu_ld16u(ctx, cpu_gprh[rD(ctx->opcode)], addr);
  6892 + gen_addr_add(ctx, addr, addr, 2);
  6893 + gen_qemu_ld16u(ctx, cpu_gpr[rD(ctx->opcode)], addr);
6889 #endif 6894 #endif
6890 } 6895 }
6891 6896
@@ -6893,24 +6898,24 @@ static always_inline void gen_op_evlwhos(DisasContext *ctx, TCGv addr) @@ -6893,24 +6898,24 @@ static always_inline void gen_op_evlwhos(DisasContext *ctx, TCGv addr)
6893 { 6898 {
6894 #if defined(TARGET_PPC64) 6899 #if defined(TARGET_PPC64)
6895 TCGv t0 = tcg_temp_new(); 6900 TCGv t0 = tcg_temp_new();
6896 - gen_qemu_ld16s(t0, addr, ctx->mem_idx); 6901 + gen_qemu_ld16s(ctx, t0, addr);
6897 tcg_gen_ext32u_tl(cpu_gpr[rD(ctx->opcode)], t0); 6902 tcg_gen_ext32u_tl(cpu_gpr[rD(ctx->opcode)], t0);
6898 - tcg_gen_addi_tl(addr, addr, 2);  
6899 - gen_qemu_ld16s(t0, addr, ctx->mem_idx); 6903 + gen_addr_add(ctx, addr, addr, 2);
  6904 + gen_qemu_ld16s(ctx, t0, addr);
6900 tcg_gen_shli_tl(t0, t0, 32); 6905 tcg_gen_shli_tl(t0, t0, 32);
6901 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0); 6906 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
6902 tcg_temp_free(t0); 6907 tcg_temp_free(t0);
6903 #else 6908 #else
6904 - gen_qemu_ld16s(cpu_gprh[rD(ctx->opcode)], addr, ctx->mem_idx);  
6905 - tcg_gen_addi_tl(addr, addr, 2);  
6906 - gen_qemu_ld16s(cpu_gpr[rD(ctx->opcode)], addr, ctx->mem_idx); 6909 + gen_qemu_ld16s(ctx, cpu_gprh[rD(ctx->opcode)], addr);
  6910 + gen_addr_add(ctx, addr, addr, 2);
  6911 + gen_qemu_ld16s(ctx, cpu_gpr[rD(ctx->opcode)], addr);
6907 #endif 6912 #endif
6908 } 6913 }
6909 6914
6910 static always_inline void gen_op_evlwwsplat(DisasContext *ctx, TCGv addr) 6915 static always_inline void gen_op_evlwwsplat(DisasContext *ctx, TCGv addr)
6911 { 6916 {
6912 TCGv t0 = tcg_temp_new(); 6917 TCGv t0 = tcg_temp_new();
6913 - gen_qemu_ld32u(t0, addr, ctx->mem_idx); 6918 + gen_qemu_ld32u(ctx, t0, addr);
6914 #if defined(TARGET_PPC64) 6919 #if defined(TARGET_PPC64)
6915 tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], t0, 32); 6920 tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], t0, 32);
6916 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0); 6921 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
@@ -6925,21 +6930,21 @@ static always_inline void gen_op_evlwhsplat(DisasContext *ctx, TCGv addr) @@ -6925,21 +6930,21 @@ static always_inline void gen_op_evlwhsplat(DisasContext *ctx, TCGv addr)
6925 { 6930 {
6926 TCGv t0 = tcg_temp_new(); 6931 TCGv t0 = tcg_temp_new();
6927 #if defined(TARGET_PPC64) 6932 #if defined(TARGET_PPC64)
6928 - gen_qemu_ld16u(t0, addr, ctx->mem_idx); 6933 + gen_qemu_ld16u(ctx, t0, addr);
6929 tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], t0, 48); 6934 tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], t0, 48);
6930 tcg_gen_shli_tl(t0, t0, 32); 6935 tcg_gen_shli_tl(t0, t0, 32);
6931 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0); 6936 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
6932 - tcg_gen_addi_tl(addr, addr, 2);  
6933 - gen_qemu_ld16u(t0, addr, ctx->mem_idx); 6937 + gen_addr_add(ctx, addr, addr, 2);
  6938 + gen_qemu_ld16u(ctx, t0, addr);
6934 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0); 6939 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
6935 tcg_gen_shli_tl(t0, t0, 16); 6940 tcg_gen_shli_tl(t0, t0, 16);
6936 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0); 6941 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
6937 #else 6942 #else
6938 - gen_qemu_ld16u(t0, addr, ctx->mem_idx); 6943 + gen_qemu_ld16u(ctx, t0, addr);
6939 tcg_gen_shli_tl(cpu_gprh[rD(ctx->opcode)], t0, 16); 6944 tcg_gen_shli_tl(cpu_gprh[rD(ctx->opcode)], t0, 16);
6940 tcg_gen_or_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rD(ctx->opcode)], t0); 6945 tcg_gen_or_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rD(ctx->opcode)], t0);
6941 - tcg_gen_addi_tl(addr, addr, 2);  
6942 - gen_qemu_ld16u(t0, addr, ctx->mem_idx); 6946 + gen_addr_add(ctx, addr, addr, 2);
  6947 + gen_qemu_ld16u(ctx, t0, addr);
6943 tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], t0, 16); 6948 tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], t0, 16);
6944 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gprh[rD(ctx->opcode)], t0); 6949 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gprh[rD(ctx->opcode)], t0);
6945 #endif 6950 #endif
@@ -6949,11 +6954,11 @@ static always_inline void gen_op_evlwhsplat(DisasContext *ctx, TCGv addr) @@ -6949,11 +6954,11 @@ static always_inline void gen_op_evlwhsplat(DisasContext *ctx, TCGv addr)
6949 static always_inline void gen_op_evstdd(DisasContext *ctx, TCGv addr) 6954 static always_inline void gen_op_evstdd(DisasContext *ctx, TCGv addr)
6950 { 6955 {
6951 #if defined(TARGET_PPC64) 6956 #if defined(TARGET_PPC64)
6952 - gen_qemu_st64(cpu_gpr[rS(ctx->opcode)], addr, ctx->mem_idx); 6957 + gen_qemu_st64(ctx, cpu_gpr[rS(ctx->opcode)], addr);
6953 #else 6958 #else
6954 TCGv_i64 t0 = tcg_temp_new_i64(); 6959 TCGv_i64 t0 = tcg_temp_new_i64();
6955 tcg_gen_concat_i32_i64(t0, cpu_gpr[rS(ctx->opcode)], cpu_gprh[rS(ctx->opcode)]); 6960 tcg_gen_concat_i32_i64(t0, cpu_gpr[rS(ctx->opcode)], cpu_gprh[rS(ctx->opcode)]);
6956 - gen_qemu_st64(t0, addr, ctx->mem_idx); 6961 + gen_qemu_st64(ctx, t0, addr);
6957 tcg_temp_free_i64(t0); 6962 tcg_temp_free_i64(t0);
6958 #endif 6963 #endif
6959 } 6964 }
@@ -6963,13 +6968,13 @@ static always_inline void gen_op_evstdw(DisasContext *ctx, TCGv addr) @@ -6963,13 +6968,13 @@ static always_inline void gen_op_evstdw(DisasContext *ctx, TCGv addr)
6963 #if defined(TARGET_PPC64) 6968 #if defined(TARGET_PPC64)
6964 TCGv t0 = tcg_temp_new(); 6969 TCGv t0 = tcg_temp_new();
6965 tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], 32); 6970 tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], 32);
6966 - gen_qemu_st32(t0, addr, ctx->mem_idx); 6971 + gen_qemu_st32(ctx, t0, addr);
6967 tcg_temp_free(t0); 6972 tcg_temp_free(t0);
6968 #else 6973 #else
6969 - gen_qemu_st32(cpu_gprh[rS(ctx->opcode)], addr, ctx->mem_idx); 6974 + gen_qemu_st32(ctx, cpu_gprh[rS(ctx->opcode)], addr);
6970 #endif 6975 #endif
6971 - tcg_gen_addi_tl(addr, addr, 4);  
6972 - gen_qemu_st32(cpu_gpr[rS(ctx->opcode)], addr, ctx->mem_idx); 6976 + gen_addr_add(ctx, addr, addr, 4);
  6977 + gen_qemu_st32(ctx, cpu_gpr[rS(ctx->opcode)], addr);
6973 } 6978 }
6974 6979
6975 static always_inline void gen_op_evstdh(DisasContext *ctx, TCGv addr) 6980 static always_inline void gen_op_evstdh(DisasContext *ctx, TCGv addr)
@@ -6980,20 +6985,20 @@ static always_inline void gen_op_evstdh(DisasContext *ctx, TCGv addr) @@ -6980,20 +6985,20 @@ static always_inline void gen_op_evstdh(DisasContext *ctx, TCGv addr)
6980 #else 6985 #else
6981 tcg_gen_shri_tl(t0, cpu_gprh[rS(ctx->opcode)], 16); 6986 tcg_gen_shri_tl(t0, cpu_gprh[rS(ctx->opcode)], 16);
6982 #endif 6987 #endif
6983 - gen_qemu_st16(t0, addr, ctx->mem_idx);  
6984 - tcg_gen_addi_tl(addr, addr, 2); 6988 + gen_qemu_st16(ctx, t0, addr);
  6989 + gen_addr_add(ctx, addr, addr, 2);
6985 #if defined(TARGET_PPC64) 6990 #if defined(TARGET_PPC64)
6986 tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], 32); 6991 tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], 32);
6987 - gen_qemu_st16(t0, addr, ctx->mem_idx); 6992 + gen_qemu_st16(ctx, t0, addr);
6988 #else 6993 #else
6989 - gen_qemu_st16(cpu_gprh[rS(ctx->opcode)], addr, ctx->mem_idx); 6994 + gen_qemu_st16(ctx, cpu_gprh[rS(ctx->opcode)], addr);
6990 #endif 6995 #endif
6991 - tcg_gen_addi_tl(addr, addr, 2); 6996 + gen_addr_add(ctx, addr, addr, 2);
6992 tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], 16); 6997 tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], 16);
6993 - gen_qemu_st16(t0, addr, ctx->mem_idx); 6998 + gen_qemu_st16(ctx, t0, addr);
6994 tcg_temp_free(t0); 6999 tcg_temp_free(t0);
6995 - tcg_gen_addi_tl(addr, addr, 2);  
6996 - gen_qemu_st16(cpu_gpr[rS(ctx->opcode)], addr, ctx->mem_idx); 7000 + gen_addr_add(ctx, addr, addr, 2);
  7001 + gen_qemu_st16(ctx, cpu_gpr[rS(ctx->opcode)], addr);
6997 } 7002 }
6998 7003
6999 static always_inline void gen_op_evstwhe(DisasContext *ctx, TCGv addr) 7004 static always_inline void gen_op_evstwhe(DisasContext *ctx, TCGv addr)
@@ -7004,10 +7009,10 @@ static always_inline void gen_op_evstwhe(DisasContext *ctx, TCGv addr) @@ -7004,10 +7009,10 @@ static always_inline void gen_op_evstwhe(DisasContext *ctx, TCGv addr)
7004 #else 7009 #else
7005 tcg_gen_shri_tl(t0, cpu_gprh[rS(ctx->opcode)], 16); 7010 tcg_gen_shri_tl(t0, cpu_gprh[rS(ctx->opcode)], 16);
7006 #endif 7011 #endif
7007 - gen_qemu_st16(t0, addr, ctx->mem_idx);  
7008 - tcg_gen_addi_tl(addr, addr, 2); 7012 + gen_qemu_st16(ctx, t0, addr);
  7013 + gen_addr_add(ctx, addr, addr, 2);
7009 tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], 16); 7014 tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], 16);
7010 - gen_qemu_st16(t0, addr, ctx->mem_idx); 7015 + gen_qemu_st16(ctx, t0, addr);
7011 tcg_temp_free(t0); 7016 tcg_temp_free(t0);
7012 } 7017 }
7013 7018
@@ -7016,13 +7021,13 @@ static always_inline void gen_op_evstwho(DisasContext *ctx, TCGv addr) @@ -7016,13 +7021,13 @@ static always_inline void gen_op_evstwho(DisasContext *ctx, TCGv addr)
7016 #if defined(TARGET_PPC64) 7021 #if defined(TARGET_PPC64)
7017 TCGv t0 = tcg_temp_new(); 7022 TCGv t0 = tcg_temp_new();
7018 tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], 32); 7023 tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], 32);
7019 - gen_qemu_st16(t0, addr, ctx->mem_idx); 7024 + gen_qemu_st16(ctx, t0, addr);
7020 tcg_temp_free(t0); 7025 tcg_temp_free(t0);
7021 #else 7026 #else
7022 - gen_qemu_st16(cpu_gprh[rS(ctx->opcode)], addr, ctx->mem_idx); 7027 + gen_qemu_st16(ctx, cpu_gprh[rS(ctx->opcode)], addr);
7023 #endif 7028 #endif
7024 - tcg_gen_addi_tl(addr, addr, 2);  
7025 - gen_qemu_st16(cpu_gpr[rS(ctx->opcode)], addr, ctx->mem_idx); 7029 + gen_addr_add(ctx, addr, addr, 2);
  7030 + gen_qemu_st16(ctx, cpu_gpr[rS(ctx->opcode)], addr);
7026 } 7031 }
7027 7032
7028 static always_inline void gen_op_evstwwe(DisasContext *ctx, TCGv addr) 7033 static always_inline void gen_op_evstwwe(DisasContext *ctx, TCGv addr)
@@ -7030,31 +7035,32 @@ static always_inline void gen_op_evstwwe(DisasContext *ctx, TCGv addr) @@ -7030,31 +7035,32 @@ static always_inline void gen_op_evstwwe(DisasContext *ctx, TCGv addr)
7030 #if defined(TARGET_PPC64) 7035 #if defined(TARGET_PPC64)
7031 TCGv t0 = tcg_temp_new(); 7036 TCGv t0 = tcg_temp_new();
7032 tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], 32); 7037 tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], 32);
7033 - gen_qemu_st32(t0, addr, ctx->mem_idx); 7038 + gen_qemu_st32(ctx, t0, addr);
7034 tcg_temp_free(t0); 7039 tcg_temp_free(t0);
7035 #else 7040 #else
7036 - gen_qemu_st32(cpu_gprh[rS(ctx->opcode)], addr, ctx->mem_idx); 7041 + gen_qemu_st32(ctx, cpu_gprh[rS(ctx->opcode)], addr);
7037 #endif 7042 #endif
7038 } 7043 }
7039 7044
7040 static always_inline void gen_op_evstwwo(DisasContext *ctx, TCGv addr) 7045 static always_inline void gen_op_evstwwo(DisasContext *ctx, TCGv addr)
7041 { 7046 {
7042 - gen_qemu_st32(cpu_gpr[rS(ctx->opcode)], addr, ctx->mem_idx); 7047 + gen_qemu_st32(ctx, cpu_gpr[rS(ctx->opcode)], addr);
7043 } 7048 }
7044 7049
7045 #define GEN_SPEOP_LDST(name, opc2, sh) \ 7050 #define GEN_SPEOP_LDST(name, opc2, sh) \
7046 -GEN_HANDLER(gen_##name, 0x04, opc2, 0x0C, 0x00000000, PPC_SPE) \ 7051 +GEN_HANDLER(name, 0x04, opc2, 0x0C, 0x00000000, PPC_SPE) \
7047 { \ 7052 { \
7048 TCGv t0; \ 7053 TCGv t0; \
7049 if (unlikely(!ctx->spe_enabled)) { \ 7054 if (unlikely(!ctx->spe_enabled)) { \
7050 GEN_EXCP_NO_AP(ctx); \ 7055 GEN_EXCP_NO_AP(ctx); \
7051 return; \ 7056 return; \
7052 } \ 7057 } \
  7058 + gen_set_access_type(ctx, ACCESS_INT); \
7053 t0 = tcg_temp_new(); \ 7059 t0 = tcg_temp_new(); \
7054 if (Rc(ctx->opcode)) { \ 7060 if (Rc(ctx->opcode)) { \
7055 - gen_addr_spe_imm_index(t0, ctx, sh); \ 7061 + gen_addr_spe_imm_index(ctx, t0, sh); \
7056 } else { \ 7062 } else { \
7057 - gen_addr_reg_index(t0, ctx); \ 7063 + gen_addr_reg_index(ctx, t0); \
7058 } \ 7064 } \
7059 gen_op_##name(ctx, t0); \ 7065 gen_op_##name(ctx, t0); \
7060 tcg_temp_free(t0); \ 7066 tcg_temp_free(t0); \
@@ -7710,7 +7716,6 @@ static always_inline void gen_intermediate_code_internal (CPUState *env, @@ -7710,7 +7716,6 @@ static always_inline void gen_intermediate_code_internal (CPUState *env,
7710 opc_handler_t **table, *handler; 7716 opc_handler_t **table, *handler;
7711 target_ulong pc_start; 7717 target_ulong pc_start;
7712 uint16_t *gen_opc_end; 7718 uint16_t *gen_opc_end;
7713 - int supervisor, little_endian;  
7714 CPUBreakpoint *bp; 7719 CPUBreakpoint *bp;
7715 int j, lj = -1; 7720 int j, lj = -1;
7716 int num_insns; 7721 int num_insns;
@@ -7725,16 +7730,11 @@ static always_inline void gen_intermediate_code_internal (CPUState *env, @@ -7725,16 +7730,11 @@ static always_inline void gen_intermediate_code_internal (CPUState *env,
7725 ctx.tb = tb; 7730 ctx.tb = tb;
7726 ctx.exception = POWERPC_EXCP_NONE; 7731 ctx.exception = POWERPC_EXCP_NONE;
7727 ctx.spr_cb = env->spr_cb; 7732 ctx.spr_cb = env->spr_cb;
7728 - supervisor = env->mmu_idx;  
7729 -#if !defined(CONFIG_USER_ONLY)  
7730 - ctx.supervisor = supervisor;  
7731 -#endif  
7732 - little_endian = env->hflags & (1 << MSR_LE) ? 1 : 0; 7733 + ctx.mem_idx = env->mmu_idx;
  7734 + ctx.access_type = -1;
  7735 + ctx.le_mode = env->hflags & (1 << MSR_LE) ? 1 : 0;
7733 #if defined(TARGET_PPC64) 7736 #if defined(TARGET_PPC64)
7734 ctx.sf_mode = msr_sf; 7737 ctx.sf_mode = msr_sf;
7735 - ctx.mem_idx = (supervisor << 2) | (msr_sf << 1) | little_endian;  
7736 -#else  
7737 - ctx.mem_idx = (supervisor << 1) | little_endian;  
7738 #endif 7738 #endif
7739 ctx.fpu_enabled = msr_fp; 7739 ctx.fpu_enabled = msr_fp;
7740 if ((env->flags & POWERPC_FLAG_SPE) && msr_spe) 7740 if ((env->flags & POWERPC_FLAG_SPE) && msr_spe)
@@ -7789,12 +7789,12 @@ static always_inline void gen_intermediate_code_internal (CPUState *env, @@ -7789,12 +7789,12 @@ static always_inline void gen_intermediate_code_internal (CPUState *env,
7789 if (loglevel & CPU_LOG_TB_IN_ASM) { 7789 if (loglevel & CPU_LOG_TB_IN_ASM) {
7790 fprintf(logfile, "----------------\n"); 7790 fprintf(logfile, "----------------\n");
7791 fprintf(logfile, "nip=" ADDRX " super=%d ir=%d\n", 7791 fprintf(logfile, "nip=" ADDRX " super=%d ir=%d\n",
7792 - ctx.nip, supervisor, (int)msr_ir); 7792 + ctx.nip, ctx.mem_idx, (int)msr_ir);
7793 } 7793 }
7794 #endif 7794 #endif
7795 if (num_insns + 1 == max_insns && (tb->cflags & CF_LAST_IO)) 7795 if (num_insns + 1 == max_insns && (tb->cflags & CF_LAST_IO))
7796 gen_io_start(); 7796 gen_io_start();
7797 - if (unlikely(little_endian)) { 7797 + if (unlikely(ctx.le_mode)) {
7798 ctx.opcode = bswap32(ldl_code(ctx.nip)); 7798 ctx.opcode = bswap32(ldl_code(ctx.nip));
7799 } else { 7799 } else {
7800 ctx.opcode = ldl_code(ctx.nip); 7800 ctx.opcode = ldl_code(ctx.nip);
@@ -7904,7 +7904,7 @@ static always_inline void gen_intermediate_code_internal (CPUState *env, @@ -7904,7 +7904,7 @@ static always_inline void gen_intermediate_code_internal (CPUState *env,
7904 if (loglevel & CPU_LOG_TB_IN_ASM) { 7904 if (loglevel & CPU_LOG_TB_IN_ASM) {
7905 int flags; 7905 int flags;
7906 flags = env->bfd_mach; 7906 flags = env->bfd_mach;
7907 - flags |= little_endian << 16; 7907 + flags |= ctx.le_mode << 16;
7908 fprintf(logfile, "IN: %s\n", lookup_symbol(pc_start)); 7908 fprintf(logfile, "IN: %s\n", lookup_symbol(pc_start));
7909 target_disas(logfile, pc_start, ctx.nip - pc_start, flags); 7909 target_disas(logfile, pc_start, ctx.nip - pc_start, flags);
7910 fprintf(logfile, "\n"); 7910 fprintf(logfile, "\n");