gwj / at91sam9263 · Commits

Commit 764dfc3fa03f08457bb584720650c8899df82d57

Authored by ths
1 parent ae45d369

Move FP TNs to cpu env. 


git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4728 c046a42c-6fe2-441c-8c8c-71466251a162
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Showing 3 changed files with 27 additions and 26 deletions
target-mips/cpu.h
  View file @764dfc3
@@ -70,11 +70,6 @@ typedef struct CPUMIPSFPUContext CPUMIPSFPUContext; @@ -70,11 +70,6 @@ typedef struct CPUMIPSFPUContext CPUMIPSFPUContext;
70 struct CPUMIPSFPUContext { 70 struct CPUMIPSFPUContext {
71 /* Floating point registers */ 71 /* Floating point registers */
72 fpr_t fpr[32]; 72 fpr_t fpr[32];
73 -#ifndef USE_HOST_FLOAT_REGS  
74 - fpr_t ft0;  
75 - fpr_t ft1;  
76 - fpr_t ft2;  
77 -#endif  
78 float_status fp_status; 73 float_status fp_status;
79 /* fpu implementation/revision register (fir) */ 74 /* fpu implementation/revision register (fir) */
80 uint32_t fcr0; 75 uint32_t fcr0;
@@ -149,6 +144,12 @@ struct CPUMIPSState { @@ -149,6 +144,12 @@ struct CPUMIPSState {
149 target_ulong t0; 144 target_ulong t0;
150 target_ulong t1; 145 target_ulong t1;
151 #endif 146 #endif
  147 + /* temporary hack for FP globals */
  148 +#ifndef USE_HOST_FLOAT_REGS
  149 + fpr_t ft0;
  150 + fpr_t ft1;
  151 + fpr_t ft2;
  152 +#endif
152 target_ulong HI[MIPS_TC_MAX][MIPS_DSP_ACC]; 153 target_ulong HI[MIPS_TC_MAX][MIPS_DSP_ACC];
153 target_ulong LO[MIPS_TC_MAX][MIPS_DSP_ACC]; 154 target_ulong LO[MIPS_TC_MAX][MIPS_DSP_ACC];
154 target_ulong ACX[MIPS_TC_MAX][MIPS_DSP_ACC]; 155 target_ulong ACX[MIPS_TC_MAX][MIPS_DSP_ACC];
target-mips/exec.h
  View file @764dfc3
@@ -21,24 +21,24 @@ register target_ulong T1 asm(AREG2); @@ -21,24 +21,24 @@ register target_ulong T1 asm(AREG2);
21 #if defined (USE_HOST_FLOAT_REGS) 21 #if defined (USE_HOST_FLOAT_REGS)
22 #error "implement me." 22 #error "implement me."
23 #else 23 #else
24 -#define FDT0 (env->fpu->ft0.fd)  
25 -#define FDT1 (env->fpu->ft1.fd)  
26 -#define FDT2 (env->fpu->ft2.fd)  
27 -#define FST0 (env->fpu->ft0.fs[FP_ENDIAN_IDX])  
28 -#define FST1 (env->fpu->ft1.fs[FP_ENDIAN_IDX])  
29 -#define FST2 (env->fpu->ft2.fs[FP_ENDIAN_IDX])  
30 -#define FSTH0 (env->fpu->ft0.fs[!FP_ENDIAN_IDX])  
31 -#define FSTH1 (env->fpu->ft1.fs[!FP_ENDIAN_IDX])  
32 -#define FSTH2 (env->fpu->ft2.fs[!FP_ENDIAN_IDX])  
33 -#define DT0 (env->fpu->ft0.d)  
34 -#define DT1 (env->fpu->ft1.d)  
35 -#define DT2 (env->fpu->ft2.d)  
36 -#define WT0 (env->fpu->ft0.w[FP_ENDIAN_IDX])  
37 -#define WT1 (env->fpu->ft1.w[FP_ENDIAN_IDX])  
38 -#define WT2 (env->fpu->ft2.w[FP_ENDIAN_IDX])  
39 -#define WTH0 (env->fpu->ft0.w[!FP_ENDIAN_IDX])  
40 -#define WTH1 (env->fpu->ft1.w[!FP_ENDIAN_IDX])  
41 -#define WTH2 (env->fpu->ft2.w[!FP_ENDIAN_IDX]) 24 +#define FDT0 (env->ft0.fd)
  25 +#define FDT1 (env->ft1.fd)
  26 +#define FDT2 (env->ft2.fd)
  27 +#define FST0 (env->ft0.fs[FP_ENDIAN_IDX])
  28 +#define FST1 (env->ft1.fs[FP_ENDIAN_IDX])
  29 +#define FST2 (env->ft2.fs[FP_ENDIAN_IDX])
  30 +#define FSTH0 (env->ft0.fs[!FP_ENDIAN_IDX])
  31 +#define FSTH1 (env->ft1.fs[!FP_ENDIAN_IDX])
  32 +#define FSTH2 (env->ft2.fs[!FP_ENDIAN_IDX])
  33 +#define DT0 (env->ft0.d)
  34 +#define DT1 (env->ft1.d)
  35 +#define DT2 (env->ft2.d)
  36 +#define WT0 (env->ft0.w[FP_ENDIAN_IDX])
  37 +#define WT1 (env->ft1.w[FP_ENDIAN_IDX])
  38 +#define WT2 (env->ft2.w[FP_ENDIAN_IDX])
  39 +#define WTH0 (env->ft0.w[!FP_ENDIAN_IDX])
  40 +#define WTH1 (env->ft1.w[!FP_ENDIAN_IDX])
  41 +#define WTH2 (env->ft2.w[!FP_ENDIAN_IDX])
42 #endif 42 #endif
43 43
44 #include "cpu.h" 44 #include "cpu.h"
target-mips/translate.c
  View file @764dfc3
@@ -7386,9 +7386,9 @@ void fpu_dump_state(CPUState *env, FILE *f, @@ -7386,9 +7386,9 @@ void fpu_dump_state(CPUState *env, FILE *f,
7386 fpu_fprintf(f, "CP1 FCR0 0x%08x FCR31 0x%08x SR.FR %d fp_status 0x%08x(0x%02x)\n", 7386 fpu_fprintf(f, "CP1 FCR0 0x%08x FCR31 0x%08x SR.FR %d fp_status 0x%08x(0x%02x)\n",
7387 env->fpu->fcr0, env->fpu->fcr31, is_fpu64, env->fpu->fp_status, 7387 env->fpu->fcr0, env->fpu->fcr31, is_fpu64, env->fpu->fp_status,
7388 get_float_exception_flags(&env->fpu->fp_status)); 7388 get_float_exception_flags(&env->fpu->fp_status));
7389 - fpu_fprintf(f, "FT0: "); printfpr(&env->fpu->ft0);  
7390 - fpu_fprintf(f, "FT1: "); printfpr(&env->fpu->ft1);  
7391 - fpu_fprintf(f, "FT2: "); printfpr(&env->fpu->ft2); 7389 + fpu_fprintf(f, "FT0: "); printfpr(&env->ft0);
  7390 + fpu_fprintf(f, "FT1: "); printfpr(&env->ft1);
  7391 + fpu_fprintf(f, "FT2: "); printfpr(&env->ft2);
7392 for (i = 0; i < 32; (is_fpu64) ? i++ : (i += 2)) { 7392 for (i = 0; i < 32; (is_fpu64) ? i++ : (i += 2)) {
7393 fpu_fprintf(f, "%3s: ", fregnames[i]); 7393 fpu_fprintf(f, "%3s: ", fregnames[i]);
7394 printfpr(&env->fpu->fpr[i]); 7394 printfpr(&env->fpu->fpr[i]);