Commit 754f307871d1be5b3de113dd347f2d083d380e70
1 parent
68db3767
Remove cpu_T for ARM once and for all.
Signed-off-by: Filip Navara <filip.navara@gmail.com>
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28 deletions
target-arm/exec.h
@@ -20,8 +20,6 @@ | @@ -20,8 +20,6 @@ | ||
20 | #include "dyngen-exec.h" | 20 | #include "dyngen-exec.h" |
21 | 21 | ||
22 | register struct CPUARMState *env asm(AREG0); | 22 | register struct CPUARMState *env asm(AREG0); |
23 | -register uint32_t T0 asm(AREG1); | ||
24 | -register uint32_t T1 asm(AREG2); | ||
25 | 23 | ||
26 | #define M0 env->iwmmxt.val | 24 | #define M0 env->iwmmxt.val |
27 | 25 |
target-arm/translate.c
@@ -79,11 +79,9 @@ static TCGv_i64 cpu_V0, cpu_V1, cpu_M0; | @@ -79,11 +79,9 @@ static TCGv_i64 cpu_V0, cpu_V1, cpu_M0; | ||
79 | static TCGv_i32 cpu_R[16]; | 79 | static TCGv_i32 cpu_R[16]; |
80 | 80 | ||
81 | /* FIXME: These should be removed. */ | 81 | /* FIXME: These should be removed. */ |
82 | -static TCGv cpu_T[2]; | ||
83 | static TCGv cpu_F0s, cpu_F1s; | 82 | static TCGv cpu_F0s, cpu_F1s; |
84 | static TCGv_i64 cpu_F0d, cpu_F1d; | 83 | static TCGv_i64 cpu_F0d, cpu_F1d; |
85 | 84 | ||
86 | -#define ICOUNT_TEMP cpu_T[0] | ||
87 | #include "gen-icount.h" | 85 | #include "gen-icount.h" |
88 | 86 | ||
89 | static const char *regnames[] = | 87 | static const char *regnames[] = |
@@ -97,9 +95,6 @@ void arm_translate_init(void) | @@ -97,9 +95,6 @@ void arm_translate_init(void) | ||
97 | 95 | ||
98 | cpu_env = tcg_global_reg_new_ptr(TCG_AREG0, "env"); | 96 | cpu_env = tcg_global_reg_new_ptr(TCG_AREG0, "env"); |
99 | 97 | ||
100 | - cpu_T[0] = tcg_global_reg_new_i32(TCG_AREG1, "T0"); | ||
101 | - cpu_T[1] = tcg_global_reg_new_i32(TCG_AREG2, "T1"); | ||
102 | - | ||
103 | for (i = 0; i < 16; i++) { | 98 | for (i = 0; i < 16; i++) { |
104 | cpu_R[i] = tcg_global_mem_new_i32(TCG_AREG0, | 99 | cpu_R[i] = tcg_global_mem_new_i32(TCG_AREG0, |
105 | offsetof(CPUState, regs[i]), | 100 | offsetof(CPUState, regs[i]), |
@@ -823,27 +818,6 @@ static inline void gen_set_pc_im(uint32_t val) | @@ -823,27 +818,6 @@ static inline void gen_set_pc_im(uint32_t val) | ||
823 | tcg_gen_movi_i32(cpu_R[15], val); | 818 | tcg_gen_movi_i32(cpu_R[15], val); |
824 | } | 819 | } |
825 | 820 | ||
826 | -static inline void gen_movl_reg_TN(DisasContext *s, int reg, int t) | ||
827 | -{ | ||
828 | - TCGv tmp; | ||
829 | - if (reg == 15) { | ||
830 | - tmp = new_tmp(); | ||
831 | - tcg_gen_andi_i32(tmp, cpu_T[t], ~1); | ||
832 | - } else { | ||
833 | - tmp = cpu_T[t]; | ||
834 | - } | ||
835 | - tcg_gen_mov_i32(cpu_R[reg], tmp); | ||
836 | - if (reg == 15) { | ||
837 | - dead_tmp(tmp); | ||
838 | - s->is_jmp = DISAS_JUMP; | ||
839 | - } | ||
840 | -} | ||
841 | - | ||
842 | -static inline void gen_movl_reg_T1(DisasContext *s, int reg) | ||
843 | -{ | ||
844 | - gen_movl_reg_TN(s, reg, 1); | ||
845 | -} | ||
846 | - | ||
847 | /* Force a TB lookup after an instruction that changes the CPU state. */ | 821 | /* Force a TB lookup after an instruction that changes the CPU state. */ |
848 | static inline void gen_lookup_tb(DisasContext *s) | 822 | static inline void gen_lookup_tb(DisasContext *s) |
849 | { | 823 | { |