Commit 74e9115560fbdd6342f3e1a42ced6bd76b227f82
1 parent
f3e3285d
Fix PowerMac NVRAM device.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3521 c046a42c-6fe2-441c-8c8c-71466251a162
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5 changed files
with
33 additions
and
16 deletions
hw/mac_nvram.c
... | ... | @@ -26,6 +26,9 @@ |
26 | 26 | #include "ppc_mac.h" |
27 | 27 | |
28 | 28 | struct MacIONVRAMState { |
29 | + target_phys_addr_t mem_base; | |
30 | + target_phys_addr_t size; | |
31 | + int mem_index; | |
29 | 32 | uint8_t data[0x2000]; |
30 | 33 | }; |
31 | 34 | |
... | ... | @@ -58,6 +61,8 @@ static void macio_nvram_writeb (void *opaque, |
58 | 61 | target_phys_addr_t addr, uint32_t value) |
59 | 62 | { |
60 | 63 | MacIONVRAMState *s = opaque; |
64 | + | |
65 | + addr -= s->mem_base; | |
61 | 66 | addr = (addr >> 4) & 0x1fff; |
62 | 67 | s->data[addr] = value; |
63 | 68 | // printf("macio_nvram_writeb %04x = %02x\n", addr, value); |
... | ... | @@ -68,6 +73,7 @@ static uint32_t macio_nvram_readb (void *opaque, target_phys_addr_t addr) |
68 | 73 | MacIONVRAMState *s = opaque; |
69 | 74 | uint32_t value; |
70 | 75 | |
76 | + addr -= s->mem_base; | |
71 | 77 | addr = (addr >> 4) & 0x1fff; |
72 | 78 | value = s->data[addr]; |
73 | 79 | // printf("macio_nvram_readb %04x = %02x\n", addr, value); |
... | ... | @@ -87,17 +93,29 @@ static CPUReadMemoryFunc *nvram_read[] = { |
87 | 93 | &macio_nvram_readb, |
88 | 94 | }; |
89 | 95 | |
90 | -MacIONVRAMState *macio_nvram_init (int *mem_index) | |
96 | +MacIONVRAMState *macio_nvram_init (int *mem_index, target_phys_addr_t size) | |
91 | 97 | { |
92 | 98 | MacIONVRAMState *s; |
99 | + | |
93 | 100 | s = qemu_mallocz(sizeof(MacIONVRAMState)); |
94 | 101 | if (!s) |
95 | 102 | return NULL; |
96 | - *mem_index = cpu_register_io_memory(0, nvram_read, nvram_write, s); | |
103 | + s->size = size; | |
104 | + s->mem_index = cpu_register_io_memory(0, nvram_read, nvram_write, s); | |
105 | + *mem_index = s->mem_index; | |
97 | 106 | |
98 | 107 | return s; |
99 | 108 | } |
100 | 109 | |
110 | +void macio_nvram_map (void *opaque, target_phys_addr_t mem_base) | |
111 | +{ | |
112 | + MacIONVRAMState *s; | |
113 | + | |
114 | + s = opaque; | |
115 | + s->mem_base = mem_base; | |
116 | + cpu_register_physical_memory(mem_base, s->size, s->mem_index); | |
117 | +} | |
118 | + | |
101 | 119 | static uint8_t nvram_chksum (const uint8_t *buf, int n) |
102 | 120 | { |
103 | 121 | int sum, i; | ... | ... |
hw/macio.c
... | ... | @@ -31,7 +31,7 @@ struct macio_state_t { |
31 | 31 | int pic_mem_index; |
32 | 32 | int dbdma_mem_index; |
33 | 33 | int cuda_mem_index; |
34 | - int nvram_mem_index; | |
34 | + void *nvram; | |
35 | 35 | int nb_ide; |
36 | 36 | int ide_mem_index[4]; |
37 | 37 | }; |
... | ... | @@ -68,14 +68,12 @@ static void macio_map (PCIDevice *pci_dev, int region_num, |
68 | 68 | macio_state->ide_mem_index[i]); |
69 | 69 | } |
70 | 70 | } |
71 | - if (macio_state->nvram_mem_index >= 0) { | |
72 | - cpu_register_physical_memory(addr + 0x60000, 0x20000, | |
73 | - macio_state->nvram_mem_index); | |
74 | - } | |
71 | + if (macio_state->nvram != NULL) | |
72 | + macio_nvram_map(macio_state->nvram, addr + 0x60000); | |
75 | 73 | } |
76 | 74 | |
77 | 75 | void macio_init (PCIBus *bus, int device_id, int is_oldworld, int pic_mem_index, |
78 | - int dbdma_mem_index, int cuda_mem_index, int nvram_mem_index, | |
76 | + int dbdma_mem_index, int cuda_mem_index, void *nvram, | |
79 | 77 | int nb_ide, int *ide_mem_index) |
80 | 78 | { |
81 | 79 | PCIDevice *d; |
... | ... | @@ -90,7 +88,7 @@ void macio_init (PCIBus *bus, int device_id, int is_oldworld, int pic_mem_index, |
90 | 88 | macio_state->pic_mem_index = pic_mem_index; |
91 | 89 | macio_state->dbdma_mem_index = dbdma_mem_index; |
92 | 90 | macio_state->cuda_mem_index = cuda_mem_index; |
93 | - macio_state->nvram_mem_index = nvram_mem_index; | |
91 | + macio_state->nvram = nvram; | |
94 | 92 | if (nb_ide > 4) |
95 | 93 | nb_ide = 4; |
96 | 94 | macio_state->nb_ide = nb_ide; | ... | ... |
hw/ppc_chrp.c
... | ... | @@ -264,7 +264,7 @@ static void ppc_core99_init (int ram_size, int vga_ram_size, |
264 | 264 | dbdma_init(&dbdma_mem_index); |
265 | 265 | |
266 | 266 | macio_init(pci_bus, 0x0022, 0, pic_mem_index, dbdma_mem_index, |
267 | - cuda_mem_index, -1, 2, ide_mem_index); | |
267 | + cuda_mem_index, NULL, 2, ide_mem_index); | |
268 | 268 | |
269 | 269 | if (usb_enabled) { |
270 | 270 | usb_ohci_init_pci(pci_bus, 3, -1); |
... | ... | @@ -274,9 +274,9 @@ static void ppc_core99_init (int ram_size, int vga_ram_size, |
274 | 274 | graphic_depth = 15; |
275 | 275 | #if 0 /* XXX: this is ugly but needed for now, or OHW won't boot */ |
276 | 276 | /* The NewWorld NVRAM is not located in the MacIO device */ |
277 | - nvr = macio_nvram_init(&nvram_mem_index); | |
277 | + nvr = macio_nvram_init(&nvram_mem_index, 0x2000); | |
278 | 278 | pmac_format_nvram_partition(nvr, 0x2000); |
279 | - cpu_register_physical_memory(0xFFF04000, 0x20000, nvram_mem_index); | |
279 | + macio_nvram_map(nvr, 0xFFF04000); | |
280 | 280 | nvram.opaque = nvr; |
281 | 281 | nvram.read_fn = &macio_nvram_read; |
282 | 282 | nvram.write_fn = &macio_nvram_write; | ... | ... |
hw/ppc_mac.h
... | ... | @@ -43,7 +43,7 @@ void cuda_init (int *cuda_mem_index, qemu_irq irq); |
43 | 43 | |
44 | 44 | /* MacIO */ |
45 | 45 | void macio_init (PCIBus *bus, int device_id, int is_oldworld, int pic_mem_index, |
46 | - int dbdma_mem_index, int cuda_mem_index, int nvram_mem_index, | |
46 | + int dbdma_mem_index, int cuda_mem_index, void *nvram, | |
47 | 47 | int nb_ide, int *ide_mem_index); |
48 | 48 | |
49 | 49 | /* NewWorld PowerMac IDE */ |
... | ... | @@ -62,7 +62,8 @@ PCIBus *pci_pmac_init(qemu_irq *pic); |
62 | 62 | /* Mac NVRAM */ |
63 | 63 | typedef struct MacIONVRAMState MacIONVRAMState; |
64 | 64 | |
65 | -MacIONVRAMState *macio_nvram_init (int *mem_index); | |
65 | +MacIONVRAMState *macio_nvram_init (int *mem_index, target_phys_addr_t size); | |
66 | +void macio_nvram_map (void *opaque, target_phys_addr_t mem_base); | |
66 | 67 | void pmac_format_nvram_partition (MacIONVRAMState *nvr, int len); |
67 | 68 | uint32_t macio_nvram_read (void *opaque, uint32_t addr); |
68 | 69 | void macio_nvram_write (void *opaque, uint32_t addr, uint32_t val); | ... | ... |
hw/ppc_oldworld.c
... | ... | @@ -271,13 +271,13 @@ static void ppc_heathrow_init (int ram_size, int vga_ram_size, |
271 | 271 | adb_kbd_init(&adb_bus); |
272 | 272 | adb_mouse_init(&adb_bus); |
273 | 273 | |
274 | - nvr = macio_nvram_init(&nvram_mem_index); | |
274 | + nvr = macio_nvram_init(&nvram_mem_index, 0x2000); | |
275 | 275 | pmac_format_nvram_partition(nvr, 0x2000); |
276 | 276 | |
277 | 277 | dbdma_init(&dbdma_mem_index); |
278 | 278 | |
279 | 279 | macio_init(pci_bus, 0x0017, 1, pic_mem_index, dbdma_mem_index, |
280 | - cuda_mem_index, nvram_mem_index, 0, NULL); | |
280 | + cuda_mem_index, nvr, 0, NULL); | |
281 | 281 | |
282 | 282 | if (usb_enabled) { |
283 | 283 | usb_ohci_init_pci(pci_bus, 3, -1); | ... | ... |