Commit 748b9d8ef0680a989e1229f2e83db278a188ff4e
1 parent
1a7b60e7
Eliminate some uses of T2
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4065 c046a42c-6fe2-441c-8c8c-71466251a162
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1 changed file
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13 additions
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13 deletions
target-sparc/translate.c
| @@ -2019,23 +2019,23 @@ static void disas_sparc_insn(DisasContext * dc) | @@ -2019,23 +2019,23 @@ static void disas_sparc_insn(DisasContext * dc) | ||
| 2019 | save_state(dc); | 2019 | save_state(dc); |
| 2020 | tcg_gen_helper_0_1(helper_trap, cpu_T[0]); | 2020 | tcg_gen_helper_0_1(helper_trap, cpu_T[0]); |
| 2021 | } else if (cond != 0) { | 2021 | } else if (cond != 0) { |
| 2022 | + TCGv r_cond = tcg_temp_new(TCG_TYPE_TL); | ||
| 2022 | #ifdef TARGET_SPARC64 | 2023 | #ifdef TARGET_SPARC64 |
| 2023 | /* V9 icc/xcc */ | 2024 | /* V9 icc/xcc */ |
| 2024 | int cc = GET_FIELD_SP(insn, 11, 12); | 2025 | int cc = GET_FIELD_SP(insn, 11, 12); |
| 2025 | - flush_T2(dc); | 2026 | + |
| 2026 | save_state(dc); | 2027 | save_state(dc); |
| 2027 | if (cc == 0) | 2028 | if (cc == 0) |
| 2028 | - gen_cond(cpu_T[2], 0, cond); | 2029 | + gen_cond(r_cond, 0, cond); |
| 2029 | else if (cc == 2) | 2030 | else if (cc == 2) |
| 2030 | - gen_cond(cpu_T[2], 1, cond); | 2031 | + gen_cond(r_cond, 1, cond); |
| 2031 | else | 2032 | else |
| 2032 | goto illegal_insn; | 2033 | goto illegal_insn; |
| 2033 | #else | 2034 | #else |
| 2034 | - flush_T2(dc); | ||
| 2035 | save_state(dc); | 2035 | save_state(dc); |
| 2036 | - gen_cond(cpu_T[2], 0, cond); | 2036 | + gen_cond(r_cond, 0, cond); |
| 2037 | #endif | 2037 | #endif |
| 2038 | - tcg_gen_helper_0_2(helper_trapcc, cpu_T[0], cpu_T[2]); | 2038 | + tcg_gen_helper_0_2(helper_trapcc, cpu_T[0], r_cond); |
| 2039 | } | 2039 | } |
| 2040 | gen_op_next_insn(); | 2040 | gen_op_next_insn(); |
| 2041 | tcg_gen_exit_tb(0); | 2041 | tcg_gen_exit_tb(0); |
| @@ -3433,25 +3433,25 @@ static void disas_sparc_insn(DisasContext * dc) | @@ -3433,25 +3433,25 @@ static void disas_sparc_insn(DisasContext * dc) | ||
| 3433 | { | 3433 | { |
| 3434 | int cc = GET_FIELD_SP(insn, 11, 12); | 3434 | int cc = GET_FIELD_SP(insn, 11, 12); |
| 3435 | int cond = GET_FIELD_SP(insn, 14, 17); | 3435 | int cond = GET_FIELD_SP(insn, 14, 17); |
| 3436 | - TCGv r_zero; | 3436 | + TCGv r_cond; |
| 3437 | int l1; | 3437 | int l1; |
| 3438 | 3438 | ||
| 3439 | - flush_T2(dc); | 3439 | + r_cond = tcg_temp_new(TCG_TYPE_TL); |
| 3440 | if (insn & (1 << 18)) { | 3440 | if (insn & (1 << 18)) { |
| 3441 | if (cc == 0) | 3441 | if (cc == 0) |
| 3442 | - gen_cond(cpu_T[2], 0, cond); | 3442 | + gen_cond(r_cond, 0, cond); |
| 3443 | else if (cc == 2) | 3443 | else if (cc == 2) |
| 3444 | - gen_cond(cpu_T[2], 1, cond); | 3444 | + gen_cond(r_cond, 1, cond); |
| 3445 | else | 3445 | else |
| 3446 | goto illegal_insn; | 3446 | goto illegal_insn; |
| 3447 | } else { | 3447 | } else { |
| 3448 | - gen_fcond(cpu_T[2], cc, cond); | 3448 | + gen_fcond(r_cond, cc, cond); |
| 3449 | } | 3449 | } |
| 3450 | 3450 | ||
| 3451 | l1 = gen_new_label(); | 3451 | l1 = gen_new_label(); |
| 3452 | 3452 | ||
| 3453 | - r_zero = tcg_const_tl(0); | ||
| 3454 | - tcg_gen_brcond_tl(TCG_COND_EQ, cpu_T[2], r_zero, l1); | 3453 | + tcg_gen_brcond_tl(TCG_COND_EQ, r_cond, |
| 3454 | + tcg_const_tl(0), l1); | ||
| 3455 | if (IS_IMM) { /* immediate */ | 3455 | if (IS_IMM) { /* immediate */ |
| 3456 | rs2 = GET_FIELD_SPs(insn, 0, 10); | 3456 | rs2 = GET_FIELD_SPs(insn, 0, 10); |
| 3457 | gen_movl_simm_T1(rs2); | 3457 | gen_movl_simm_T1(rs2); |