gwj / at91sam9263 · Commits

Commit 73e517236c9304c09ccd2b95ceb56068a248be3d

Authored by edgar_igl
1 parent e83a8673

CRIS: Concistent use of btarget and make it possible to single-step over delayslots. 

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4389 c046a42c-6fe2-441c-8c8c-71466251a162
Inline Side-by-side
Showing 1 changed file with 14 additions and 10 deletions
target-cris/translate.c
  View file @73e5172
@@ -2509,7 +2509,7 @@ static unsigned int dec_jasc_im(DisasContext *dc) @@ -2509,7 +2509,7 @@ static unsigned int dec_jasc_im(DisasContext *dc)
2509 cris_cc_mask(dc, 0); 2509 cris_cc_mask(dc, 0);
2510 /* Store the return address in Pd. */ 2510 /* Store the return address in Pd. */
2511 tcg_gen_movi_tl(cpu_T[0], imm); 2511 tcg_gen_movi_tl(cpu_T[0], imm);
2512 - t_gen_mov_env_TN(btarget, cpu_T[0]); 2512 + tcg_gen_mov_tl(env_btarget, cpu_T[0]);
2513 tcg_gen_movi_tl(cpu_T[0], dc->pc + 8 + 4); 2513 tcg_gen_movi_tl(cpu_T[0], dc->pc + 8 + 4);
2514 t_gen_mov_preg_TN(dc->op2, cpu_T[0]); 2514 t_gen_mov_preg_TN(dc->op2, cpu_T[0]);
2515 cris_prepare_dyn_jmp(dc); 2515 cris_prepare_dyn_jmp(dc);
@@ -2522,7 +2522,7 @@ static unsigned int dec_jasc_r(DisasContext *dc) @@ -2522,7 +2522,7 @@ static unsigned int dec_jasc_r(DisasContext *dc)
2522 cris_cc_mask(dc, 0); 2522 cris_cc_mask(dc, 0);
2523 /* Store the return address in Pd. */ 2523 /* Store the return address in Pd. */
2524 t_gen_mov_TN_reg(cpu_T[0], dc->op1); 2524 t_gen_mov_TN_reg(cpu_T[0], dc->op1);
2525 - t_gen_mov_env_TN(btarget, cpu_T[0]); 2525 + tcg_gen_mov_tl(env_btarget, cpu_T[0]);
2526 tcg_gen_movi_tl(cpu_T[0], dc->pc + 4 + 4); 2526 tcg_gen_movi_tl(cpu_T[0], dc->pc + 4 + 4);
2527 t_gen_mov_preg_TN(dc->op2, cpu_T[0]); 2527 t_gen_mov_preg_TN(dc->op2, cpu_T[0]);
2528 cris_prepare_dyn_jmp(dc); 2528 cris_prepare_dyn_jmp(dc);
@@ -2557,7 +2557,7 @@ static unsigned int dec_bas_im(DisasContext *dc) @@ -2557,7 +2557,7 @@ static unsigned int dec_bas_im(DisasContext *dc)
2557 cris_cc_mask(dc, 0); 2557 cris_cc_mask(dc, 0);
2558 /* Stor the return address in Pd. */ 2558 /* Stor the return address in Pd. */
2559 tcg_gen_movi_tl(cpu_T[0], dc->pc + simm); 2559 tcg_gen_movi_tl(cpu_T[0], dc->pc + simm);
2560 - t_gen_mov_env_TN(btarget, cpu_T[0]); 2560 + tcg_gen_mov_tl(env_btarget, cpu_T[0]);
2561 tcg_gen_movi_tl(cpu_T[0], dc->pc + 8); 2561 tcg_gen_movi_tl(cpu_T[0], dc->pc + 8);
2562 t_gen_mov_preg_TN(dc->op2, cpu_T[0]); 2562 t_gen_mov_preg_TN(dc->op2, cpu_T[0]);
2563 cris_prepare_dyn_jmp(dc); 2563 cris_prepare_dyn_jmp(dc);
@@ -2573,7 +2573,7 @@ static unsigned int dec_basc_im(DisasContext *dc) @@ -2573,7 +2573,7 @@ static unsigned int dec_basc_im(DisasContext *dc)
2573 cris_cc_mask(dc, 0); 2573 cris_cc_mask(dc, 0);
2574 /* Stor the return address in Pd. */ 2574 /* Stor the return address in Pd. */
2575 tcg_gen_movi_tl(cpu_T[0], dc->pc + simm); 2575 tcg_gen_movi_tl(cpu_T[0], dc->pc + simm);
2576 - t_gen_mov_env_TN(btarget, cpu_T[0]); 2576 + tcg_gen_mov_tl(env_btarget, cpu_T[0]);
2577 tcg_gen_movi_tl(cpu_T[0], dc->pc + 12); 2577 tcg_gen_movi_tl(cpu_T[0], dc->pc + 12);
2578 t_gen_mov_preg_TN(dc->op2, cpu_T[0]); 2578 t_gen_mov_preg_TN(dc->op2, cpu_T[0]);
2579 cris_prepare_dyn_jmp(dc); 2579 cris_prepare_dyn_jmp(dc);
@@ -2813,10 +2813,12 @@ gen_intermediate_code_internal(CPUState *env, TranslationBlock *tb, @@ -2813,10 +2813,12 @@ gen_intermediate_code_internal(CPUState *env, TranslationBlock *tb,
2813 if (!logfile) 2813 if (!logfile)
2814 logfile = stderr; 2814 logfile = stderr;
2815 2815
2816 - if (tb->pc & 1)  
2817 - cpu_abort(env, "unaligned pc=%x erp=%x\n",  
2818 - env->pc, env->pregs[PR_ERP]);  
2819 - pc_start = tb->pc; 2816 + /* Odd PC indicates that branch is rexecuting due to exception in the
  2817 + * delayslot, like in real hw.
  2818 + * FIXME: we need to handle the case were the branch and the insn in
  2819 + * the delayslot do not share pages.
  2820 + */
  2821 + pc_start = tb->pc & ~1;
2820 dc->env = env; 2822 dc->env = env;
2821 dc->tb = tb; 2823 dc->tb = tb;
2822 2824
@@ -2905,14 +2907,16 @@ gen_intermediate_code_internal(CPUState *env, TranslationBlock *tb, @@ -2905,14 +2907,16 @@ gen_intermediate_code_internal(CPUState *env, TranslationBlock *tb,
2905 } 2907 }
2906 } 2908 }
2907 2909
2908 - if (env->singlestep_enabled) 2910 + /* If we are rexecuting a branch due to exceptions on
  2911 + delay slots dont break. */
  2912 + if (!(tb->pc & 1) && env->singlestep_enabled)
2909 break; 2913 break;
2910 } while (!dc->is_jmp && gen_opc_ptr < gen_opc_end 2914 } while (!dc->is_jmp && gen_opc_ptr < gen_opc_end
2911 && ((dc->pc < next_page_start) || dc->delayed_branch)); 2915 && ((dc->pc < next_page_start) || dc->delayed_branch));
2912 2916
2913 if (dc->delayed_branch == 1) { 2917 if (dc->delayed_branch == 1) {
2914 /* Reexecute the last insn. */ 2918 /* Reexecute the last insn. */
2915 - dc->pc = dc->ppc; 2919 + dc->pc = dc->ppc | 1;
2916 } 2920 }
2917 2921
2918 if (!dc->is_jmp) { 2922 if (!dc->is_jmp) {