gwj / at91sam9263 · Commits

Commit 7385ac0ba2456159a52b9b2cbb5f6c71921d0c23

Authored by ths
1 parent d8a5950a

Use the standard ASE check for MIPS-3D and MT. 


git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3427 c046a42c-6fe2-441c-8c8c-71466251a162
Inline Side-by-side
Showing 3 changed files with 80 additions and 93 deletions
target-mips/mips-defs.h
  View file @7385ac0
@@ -32,6 +32,8 @@ @@ -32,6 +32,8 @@
32 #define ASE_MDMX 0x00004000 32 #define ASE_MDMX 0x00004000
33 #define ASE_DSP 0x00008000 33 #define ASE_DSP 0x00008000
34 #define ASE_DSPR2 0x00010000 34 #define ASE_DSPR2 0x00010000
  35 +#define ASE_MT 0x00020000
  36 +#define ASE_SMARTMIPS 0x00040000
35 37
36 /* Chip specific instructions. */ 38 /* Chip specific instructions. */
37 /* Currently void */ 39 /* Currently void */
target-mips/translate.c
  View file @7385ac0
@@ -749,12 +749,6 @@ static always_inline void check_cp1_64bitmode(DisasContext *ctx) @@ -749,12 +749,6 @@ static always_inline void check_cp1_64bitmode(DisasContext *ctx)
749 generate_exception(ctx, EXCP_RI); 749 generate_exception(ctx, EXCP_RI);
750 } 750 }
751 751
752 -static always_inline void check_cp1_3d(CPUState *env, DisasContext *ctx)  
753 -{  
754 - if (unlikely(!(env->fpu->fcr0 & (1 << FCR0_3D))))  
755 - generate_exception(ctx, EXCP_RI);  
756 -}  
757 -  
758 /* 752 /*
759 * Verify if floating point register is valid; an operation is not defined 753 * Verify if floating point register is valid; an operation is not defined
760 * if bit 0 of any register specification is set and the FR bit in the 754 * if bit 0 of any register specification is set and the FR bit in the
@@ -780,14 +774,6 @@ static always_inline void check_insn(CPUState *env, DisasContext *ctx, int flags @@ -780,14 +774,6 @@ static always_inline void check_insn(CPUState *env, DisasContext *ctx, int flags
780 generate_exception(ctx, EXCP_RI); 774 generate_exception(ctx, EXCP_RI);
781 } 775 }
782 776
783 -/* This code generates a "reserved instruction" exception if the  
784 - CPU is not MIPS MT capable. */  
785 -static always_inline void check_mips_mt(CPUState *env, DisasContext *ctx)  
786 -{  
787 - if (unlikely(!(env->CP0_Config3 & (1 << CP0C3_MT))))  
788 - generate_exception(ctx, EXCP_RI);  
789 -}  
790 -  
791 /* This code generates a "reserved instruction" exception if 64-bit 777 /* This code generates a "reserved instruction" exception if 64-bit
792 instructions are not enabled. */ 778 instructions are not enabled. */
793 static always_inline void check_mips_64(DisasContext *ctx) 779 static always_inline void check_mips_64(DisasContext *ctx)
@@ -1971,17 +1957,17 @@ static void gen_mfc0 (CPUState *env, DisasContext *ctx, int reg, int sel) @@ -1971,17 +1957,17 @@ static void gen_mfc0 (CPUState *env, DisasContext *ctx, int reg, int sel)
1971 rn = "Index"; 1957 rn = "Index";
1972 break; 1958 break;
1973 case 1: 1959 case 1:
1974 - check_mips_mt(env, ctx); 1960 + check_insn(env, ctx, ASE_MT);
1975 gen_op_mfc0_mvpcontrol(); 1961 gen_op_mfc0_mvpcontrol();
1976 rn = "MVPControl"; 1962 rn = "MVPControl";
1977 break; 1963 break;
1978 case 2: 1964 case 2:
1979 - check_mips_mt(env, ctx); 1965 + check_insn(env, ctx, ASE_MT);
1980 gen_op_mfc0_mvpconf0(); 1966 gen_op_mfc0_mvpconf0();
1981 rn = "MVPConf0"; 1967 rn = "MVPConf0";
1982 break; 1968 break;
1983 case 3: 1969 case 3:
1984 - check_mips_mt(env, ctx); 1970 + check_insn(env, ctx, ASE_MT);
1985 gen_op_mfc0_mvpconf1(); 1971 gen_op_mfc0_mvpconf1();
1986 rn = "MVPConf1"; 1972 rn = "MVPConf1";
1987 break; 1973 break;
@@ -1996,37 +1982,37 @@ static void gen_mfc0 (CPUState *env, DisasContext *ctx, int reg, int sel) @@ -1996,37 +1982,37 @@ static void gen_mfc0 (CPUState *env, DisasContext *ctx, int reg, int sel)
1996 rn = "Random"; 1982 rn = "Random";
1997 break; 1983 break;
1998 case 1: 1984 case 1:
1999 - check_mips_mt(env, ctx); 1985 + check_insn(env, ctx, ASE_MT);
2000 gen_op_mfc0_vpecontrol(); 1986 gen_op_mfc0_vpecontrol();
2001 rn = "VPEControl"; 1987 rn = "VPEControl";
2002 break; 1988 break;
2003 case 2: 1989 case 2:
2004 - check_mips_mt(env, ctx); 1990 + check_insn(env, ctx, ASE_MT);
2005 gen_op_mfc0_vpeconf0(); 1991 gen_op_mfc0_vpeconf0();
2006 rn = "VPEConf0"; 1992 rn = "VPEConf0";
2007 break; 1993 break;
2008 case 3: 1994 case 3:
2009 - check_mips_mt(env, ctx); 1995 + check_insn(env, ctx, ASE_MT);
2010 gen_op_mfc0_vpeconf1(); 1996 gen_op_mfc0_vpeconf1();
2011 rn = "VPEConf1"; 1997 rn = "VPEConf1";
2012 break; 1998 break;
2013 case 4: 1999 case 4:
2014 - check_mips_mt(env, ctx); 2000 + check_insn(env, ctx, ASE_MT);
2015 gen_op_mfc0_yqmask(); 2001 gen_op_mfc0_yqmask();
2016 rn = "YQMask"; 2002 rn = "YQMask";
2017 break; 2003 break;
2018 case 5: 2004 case 5:
2019 - check_mips_mt(env, ctx); 2005 + check_insn(env, ctx, ASE_MT);
2020 gen_op_mfc0_vpeschedule(); 2006 gen_op_mfc0_vpeschedule();
2021 rn = "VPESchedule"; 2007 rn = "VPESchedule";
2022 break; 2008 break;
2023 case 6: 2009 case 6:
2024 - check_mips_mt(env, ctx); 2010 + check_insn(env, ctx, ASE_MT);
2025 gen_op_mfc0_vpeschefback(); 2011 gen_op_mfc0_vpeschefback();
2026 rn = "VPEScheFBack"; 2012 rn = "VPEScheFBack";
2027 break; 2013 break;
2028 case 7: 2014 case 7:
2029 - check_mips_mt(env, ctx); 2015 + check_insn(env, ctx, ASE_MT);
2030 gen_op_mfc0_vpeopt(); 2016 gen_op_mfc0_vpeopt();
2031 rn = "VPEOpt"; 2017 rn = "VPEOpt";
2032 break; 2018 break;
@@ -2041,37 +2027,37 @@ static void gen_mfc0 (CPUState *env, DisasContext *ctx, int reg, int sel) @@ -2041,37 +2027,37 @@ static void gen_mfc0 (CPUState *env, DisasContext *ctx, int reg, int sel)
2041 rn = "EntryLo0"; 2027 rn = "EntryLo0";
2042 break; 2028 break;
2043 case 1: 2029 case 1:
2044 - check_mips_mt(env, ctx); 2030 + check_insn(env, ctx, ASE_MT);
2045 gen_op_mfc0_tcstatus(); 2031 gen_op_mfc0_tcstatus();
2046 rn = "TCStatus"; 2032 rn = "TCStatus";
2047 break; 2033 break;
2048 case 2: 2034 case 2:
2049 - check_mips_mt(env, ctx); 2035 + check_insn(env, ctx, ASE_MT);
2050 gen_op_mfc0_tcbind(); 2036 gen_op_mfc0_tcbind();
2051 rn = "TCBind"; 2037 rn = "TCBind";
2052 break; 2038 break;
2053 case 3: 2039 case 3:
2054 - check_mips_mt(env, ctx); 2040 + check_insn(env, ctx, ASE_MT);
2055 gen_op_mfc0_tcrestart(); 2041 gen_op_mfc0_tcrestart();
2056 rn = "TCRestart"; 2042 rn = "TCRestart";
2057 break; 2043 break;
2058 case 4: 2044 case 4:
2059 - check_mips_mt(env, ctx); 2045 + check_insn(env, ctx, ASE_MT);
2060 gen_op_mfc0_tchalt(); 2046 gen_op_mfc0_tchalt();
2061 rn = "TCHalt"; 2047 rn = "TCHalt";
2062 break; 2048 break;
2063 case 5: 2049 case 5:
2064 - check_mips_mt(env, ctx); 2050 + check_insn(env, ctx, ASE_MT);
2065 gen_op_mfc0_tccontext(); 2051 gen_op_mfc0_tccontext();
2066 rn = "TCContext"; 2052 rn = "TCContext";
2067 break; 2053 break;
2068 case 6: 2054 case 6:
2069 - check_mips_mt(env, ctx); 2055 + check_insn(env, ctx, ASE_MT);
2070 gen_op_mfc0_tcschedule(); 2056 gen_op_mfc0_tcschedule();
2071 rn = "TCSchedule"; 2057 rn = "TCSchedule";
2072 break; 2058 break;
2073 case 7: 2059 case 7:
2074 - check_mips_mt(env, ctx); 2060 + check_insn(env, ctx, ASE_MT);
2075 gen_op_mfc0_tcschefback(); 2061 gen_op_mfc0_tcschefback();
2076 rn = "TCScheFBack"; 2062 rn = "TCScheFBack";
2077 break; 2063 break;
@@ -2539,17 +2525,17 @@ static void gen_mtc0 (CPUState *env, DisasContext *ctx, int reg, int sel) @@ -2539,17 +2525,17 @@ static void gen_mtc0 (CPUState *env, DisasContext *ctx, int reg, int sel)
2539 rn = "Index"; 2525 rn = "Index";
2540 break; 2526 break;
2541 case 1: 2527 case 1:
2542 - check_mips_mt(env, ctx); 2528 + check_insn(env, ctx, ASE_MT);
2543 gen_op_mtc0_mvpcontrol(); 2529 gen_op_mtc0_mvpcontrol();
2544 rn = "MVPControl"; 2530 rn = "MVPControl";
2545 break; 2531 break;
2546 case 2: 2532 case 2:
2547 - check_mips_mt(env, ctx); 2533 + check_insn(env, ctx, ASE_MT);
2548 /* ignored */ 2534 /* ignored */
2549 rn = "MVPConf0"; 2535 rn = "MVPConf0";
2550 break; 2536 break;
2551 case 3: 2537 case 3:
2552 - check_mips_mt(env, ctx); 2538 + check_insn(env, ctx, ASE_MT);
2553 /* ignored */ 2539 /* ignored */
2554 rn = "MVPConf1"; 2540 rn = "MVPConf1";
2555 break; 2541 break;
@@ -2564,37 +2550,37 @@ static void gen_mtc0 (CPUState *env, DisasContext *ctx, int reg, int sel) @@ -2564,37 +2550,37 @@ static void gen_mtc0 (CPUState *env, DisasContext *ctx, int reg, int sel)
2564 rn = "Random"; 2550 rn = "Random";
2565 break; 2551 break;
2566 case 1: 2552 case 1:
2567 - check_mips_mt(env, ctx); 2553 + check_insn(env, ctx, ASE_MT);
2568 gen_op_mtc0_vpecontrol(); 2554 gen_op_mtc0_vpecontrol();
2569 rn = "VPEControl"; 2555 rn = "VPEControl";
2570 break; 2556 break;
2571 case 2: 2557 case 2:
2572 - check_mips_mt(env, ctx); 2558 + check_insn(env, ctx, ASE_MT);
2573 gen_op_mtc0_vpeconf0(); 2559 gen_op_mtc0_vpeconf0();
2574 rn = "VPEConf0"; 2560 rn = "VPEConf0";
2575 break; 2561 break;
2576 case 3: 2562 case 3:
2577 - check_mips_mt(env, ctx); 2563 + check_insn(env, ctx, ASE_MT);
2578 gen_op_mtc0_vpeconf1(); 2564 gen_op_mtc0_vpeconf1();
2579 rn = "VPEConf1"; 2565 rn = "VPEConf1";
2580 break; 2566 break;
2581 case 4: 2567 case 4:
2582 - check_mips_mt(env, ctx); 2568 + check_insn(env, ctx, ASE_MT);
2583 gen_op_mtc0_yqmask(); 2569 gen_op_mtc0_yqmask();
2584 rn = "YQMask"; 2570 rn = "YQMask";
2585 break; 2571 break;
2586 case 5: 2572 case 5:
2587 - check_mips_mt(env, ctx); 2573 + check_insn(env, ctx, ASE_MT);
2588 gen_op_mtc0_vpeschedule(); 2574 gen_op_mtc0_vpeschedule();
2589 rn = "VPESchedule"; 2575 rn = "VPESchedule";
2590 break; 2576 break;
2591 case 6: 2577 case 6:
2592 - check_mips_mt(env, ctx); 2578 + check_insn(env, ctx, ASE_MT);
2593 gen_op_mtc0_vpeschefback(); 2579 gen_op_mtc0_vpeschefback();
2594 rn = "VPEScheFBack"; 2580 rn = "VPEScheFBack";
2595 break; 2581 break;
2596 case 7: 2582 case 7:
2597 - check_mips_mt(env, ctx); 2583 + check_insn(env, ctx, ASE_MT);
2598 gen_op_mtc0_vpeopt(); 2584 gen_op_mtc0_vpeopt();
2599 rn = "VPEOpt"; 2585 rn = "VPEOpt";
2600 break; 2586 break;
@@ -2609,37 +2595,37 @@ static void gen_mtc0 (CPUState *env, DisasContext *ctx, int reg, int sel) @@ -2609,37 +2595,37 @@ static void gen_mtc0 (CPUState *env, DisasContext *ctx, int reg, int sel)
2609 rn = "EntryLo0"; 2595 rn = "EntryLo0";
2610 break; 2596 break;
2611 case 1: 2597 case 1:
2612 - check_mips_mt(env, ctx); 2598 + check_insn(env, ctx, ASE_MT);
2613 gen_op_mtc0_tcstatus(); 2599 gen_op_mtc0_tcstatus();
2614 rn = "TCStatus"; 2600 rn = "TCStatus";
2615 break; 2601 break;
2616 case 2: 2602 case 2:
2617 - check_mips_mt(env, ctx); 2603 + check_insn(env, ctx, ASE_MT);
2618 gen_op_mtc0_tcbind(); 2604 gen_op_mtc0_tcbind();
2619 rn = "TCBind"; 2605 rn = "TCBind";
2620 break; 2606 break;
2621 case 3: 2607 case 3:
2622 - check_mips_mt(env, ctx); 2608 + check_insn(env, ctx, ASE_MT);
2623 gen_op_mtc0_tcrestart(); 2609 gen_op_mtc0_tcrestart();
2624 rn = "TCRestart"; 2610 rn = "TCRestart";
2625 break; 2611 break;
2626 case 4: 2612 case 4:
2627 - check_mips_mt(env, ctx); 2613 + check_insn(env, ctx, ASE_MT);
2628 gen_op_mtc0_tchalt(); 2614 gen_op_mtc0_tchalt();
2629 rn = "TCHalt"; 2615 rn = "TCHalt";
2630 break; 2616 break;
2631 case 5: 2617 case 5:
2632 - check_mips_mt(env, ctx); 2618 + check_insn(env, ctx, ASE_MT);
2633 gen_op_mtc0_tccontext(); 2619 gen_op_mtc0_tccontext();
2634 rn = "TCContext"; 2620 rn = "TCContext";
2635 break; 2621 break;
2636 case 6: 2622 case 6:
2637 - check_mips_mt(env, ctx); 2623 + check_insn(env, ctx, ASE_MT);
2638 gen_op_mtc0_tcschedule(); 2624 gen_op_mtc0_tcschedule();
2639 rn = "TCSchedule"; 2625 rn = "TCSchedule";
2640 break; 2626 break;
2641 case 7: 2627 case 7:
2642 - check_mips_mt(env, ctx); 2628 + check_insn(env, ctx, ASE_MT);
2643 gen_op_mtc0_tcschefback(); 2629 gen_op_mtc0_tcschefback();
2644 rn = "TCScheFBack"; 2630 rn = "TCScheFBack";
2645 break; 2631 break;
@@ -3139,17 +3125,17 @@ static void gen_dmfc0 (CPUState *env, DisasContext *ctx, int reg, int sel) @@ -3139,17 +3125,17 @@ static void gen_dmfc0 (CPUState *env, DisasContext *ctx, int reg, int sel)
3139 rn = "Index"; 3125 rn = "Index";
3140 break; 3126 break;
3141 case 1: 3127 case 1:
3142 - check_mips_mt(env, ctx); 3128 + check_insn(env, ctx, ASE_MT);
3143 gen_op_mfc0_mvpcontrol(); 3129 gen_op_mfc0_mvpcontrol();
3144 rn = "MVPControl"; 3130 rn = "MVPControl";
3145 break; 3131 break;
3146 case 2: 3132 case 2:
3147 - check_mips_mt(env, ctx); 3133 + check_insn(env, ctx, ASE_MT);
3148 gen_op_mfc0_mvpconf0(); 3134 gen_op_mfc0_mvpconf0();
3149 rn = "MVPConf0"; 3135 rn = "MVPConf0";
3150 break; 3136 break;
3151 case 3: 3137 case 3:
3152 - check_mips_mt(env, ctx); 3138 + check_insn(env, ctx, ASE_MT);
3153 gen_op_mfc0_mvpconf1(); 3139 gen_op_mfc0_mvpconf1();
3154 rn = "MVPConf1"; 3140 rn = "MVPConf1";
3155 break; 3141 break;
@@ -3164,37 +3150,37 @@ static void gen_dmfc0 (CPUState *env, DisasContext *ctx, int reg, int sel) @@ -3164,37 +3150,37 @@ static void gen_dmfc0 (CPUState *env, DisasContext *ctx, int reg, int sel)
3164 rn = "Random"; 3150 rn = "Random";
3165 break; 3151 break;
3166 case 1: 3152 case 1:
3167 - check_mips_mt(env, ctx); 3153 + check_insn(env, ctx, ASE_MT);
3168 gen_op_mfc0_vpecontrol(); 3154 gen_op_mfc0_vpecontrol();
3169 rn = "VPEControl"; 3155 rn = "VPEControl";
3170 break; 3156 break;
3171 case 2: 3157 case 2:
3172 - check_mips_mt(env, ctx); 3158 + check_insn(env, ctx, ASE_MT);
3173 gen_op_mfc0_vpeconf0(); 3159 gen_op_mfc0_vpeconf0();
3174 rn = "VPEConf0"; 3160 rn = "VPEConf0";
3175 break; 3161 break;
3176 case 3: 3162 case 3:
3177 - check_mips_mt(env, ctx); 3163 + check_insn(env, ctx, ASE_MT);
3178 gen_op_mfc0_vpeconf1(); 3164 gen_op_mfc0_vpeconf1();
3179 rn = "VPEConf1"; 3165 rn = "VPEConf1";
3180 break; 3166 break;
3181 case 4: 3167 case 4:
3182 - check_mips_mt(env, ctx); 3168 + check_insn(env, ctx, ASE_MT);
3183 gen_op_dmfc0_yqmask(); 3169 gen_op_dmfc0_yqmask();
3184 rn = "YQMask"; 3170 rn = "YQMask";
3185 break; 3171 break;
3186 case 5: 3172 case 5:
3187 - check_mips_mt(env, ctx); 3173 + check_insn(env, ctx, ASE_MT);
3188 gen_op_dmfc0_vpeschedule(); 3174 gen_op_dmfc0_vpeschedule();
3189 rn = "VPESchedule"; 3175 rn = "VPESchedule";
3190 break; 3176 break;
3191 case 6: 3177 case 6:
3192 - check_mips_mt(env, ctx); 3178 + check_insn(env, ctx, ASE_MT);
3193 gen_op_dmfc0_vpeschefback(); 3179 gen_op_dmfc0_vpeschefback();
3194 rn = "VPEScheFBack"; 3180 rn = "VPEScheFBack";
3195 break; 3181 break;
3196 case 7: 3182 case 7:
3197 - check_mips_mt(env, ctx); 3183 + check_insn(env, ctx, ASE_MT);
3198 gen_op_mfc0_vpeopt(); 3184 gen_op_mfc0_vpeopt();
3199 rn = "VPEOpt"; 3185 rn = "VPEOpt";
3200 break; 3186 break;
@@ -3209,37 +3195,37 @@ static void gen_dmfc0 (CPUState *env, DisasContext *ctx, int reg, int sel) @@ -3209,37 +3195,37 @@ static void gen_dmfc0 (CPUState *env, DisasContext *ctx, int reg, int sel)
3209 rn = "EntryLo0"; 3195 rn = "EntryLo0";
3210 break; 3196 break;
3211 case 1: 3197 case 1:
3212 - check_mips_mt(env, ctx); 3198 + check_insn(env, ctx, ASE_MT);
3213 gen_op_mfc0_tcstatus(); 3199 gen_op_mfc0_tcstatus();
3214 rn = "TCStatus"; 3200 rn = "TCStatus";
3215 break; 3201 break;
3216 case 2: 3202 case 2:
3217 - check_mips_mt(env, ctx); 3203 + check_insn(env, ctx, ASE_MT);
3218 gen_op_mfc0_tcbind(); 3204 gen_op_mfc0_tcbind();
3219 rn = "TCBind"; 3205 rn = "TCBind";
3220 break; 3206 break;
3221 case 3: 3207 case 3:
3222 - check_mips_mt(env, ctx); 3208 + check_insn(env, ctx, ASE_MT);
3223 gen_op_dmfc0_tcrestart(); 3209 gen_op_dmfc0_tcrestart();
3224 rn = "TCRestart"; 3210 rn = "TCRestart";
3225 break; 3211 break;
3226 case 4: 3212 case 4:
3227 - check_mips_mt(env, ctx); 3213 + check_insn(env, ctx, ASE_MT);
3228 gen_op_dmfc0_tchalt(); 3214 gen_op_dmfc0_tchalt();
3229 rn = "TCHalt"; 3215 rn = "TCHalt";
3230 break; 3216 break;
3231 case 5: 3217 case 5:
3232 - check_mips_mt(env, ctx); 3218 + check_insn(env, ctx, ASE_MT);
3233 gen_op_dmfc0_tccontext(); 3219 gen_op_dmfc0_tccontext();
3234 rn = "TCContext"; 3220 rn = "TCContext";
3235 break; 3221 break;
3236 case 6: 3222 case 6:
3237 - check_mips_mt(env, ctx); 3223 + check_insn(env, ctx, ASE_MT);
3238 gen_op_dmfc0_tcschedule(); 3224 gen_op_dmfc0_tcschedule();
3239 rn = "TCSchedule"; 3225 rn = "TCSchedule";
3240 break; 3226 break;
3241 case 7: 3227 case 7:
3242 - check_mips_mt(env, ctx); 3228 + check_insn(env, ctx, ASE_MT);
3243 gen_op_dmfc0_tcschefback(); 3229 gen_op_dmfc0_tcschefback();
3244 rn = "TCScheFBack"; 3230 rn = "TCScheFBack";
3245 break; 3231 break;
@@ -3696,17 +3682,17 @@ static void gen_dmtc0 (CPUState *env, DisasContext *ctx, int reg, int sel) @@ -3696,17 +3682,17 @@ static void gen_dmtc0 (CPUState *env, DisasContext *ctx, int reg, int sel)
3696 rn = "Index"; 3682 rn = "Index";
3697 break; 3683 break;
3698 case 1: 3684 case 1:
3699 - check_mips_mt(env, ctx); 3685 + check_insn(env, ctx, ASE_MT);
3700 gen_op_mtc0_mvpcontrol(); 3686 gen_op_mtc0_mvpcontrol();
3701 rn = "MVPControl"; 3687 rn = "MVPControl";
3702 break; 3688 break;
3703 case 2: 3689 case 2:
3704 - check_mips_mt(env, ctx); 3690 + check_insn(env, ctx, ASE_MT);
3705 /* ignored */ 3691 /* ignored */
3706 rn = "MVPConf0"; 3692 rn = "MVPConf0";
3707 break; 3693 break;
3708 case 3: 3694 case 3:
3709 - check_mips_mt(env, ctx); 3695 + check_insn(env, ctx, ASE_MT);
3710 /* ignored */ 3696 /* ignored */
3711 rn = "MVPConf1"; 3697 rn = "MVPConf1";
3712 break; 3698 break;
@@ -3721,37 +3707,37 @@ static void gen_dmtc0 (CPUState *env, DisasContext *ctx, int reg, int sel) @@ -3721,37 +3707,37 @@ static void gen_dmtc0 (CPUState *env, DisasContext *ctx, int reg, int sel)
3721 rn = "Random"; 3707 rn = "Random";
3722 break; 3708 break;
3723 case 1: 3709 case 1:
3724 - check_mips_mt(env, ctx); 3710 + check_insn(env, ctx, ASE_MT);
3725 gen_op_mtc0_vpecontrol(); 3711 gen_op_mtc0_vpecontrol();
3726 rn = "VPEControl"; 3712 rn = "VPEControl";
3727 break; 3713 break;
3728 case 2: 3714 case 2:
3729 - check_mips_mt(env, ctx); 3715 + check_insn(env, ctx, ASE_MT);
3730 gen_op_mtc0_vpeconf0(); 3716 gen_op_mtc0_vpeconf0();
3731 rn = "VPEConf0"; 3717 rn = "VPEConf0";
3732 break; 3718 break;
3733 case 3: 3719 case 3:
3734 - check_mips_mt(env, ctx); 3720 + check_insn(env, ctx, ASE_MT);
3735 gen_op_mtc0_vpeconf1(); 3721 gen_op_mtc0_vpeconf1();
3736 rn = "VPEConf1"; 3722 rn = "VPEConf1";
3737 break; 3723 break;
3738 case 4: 3724 case 4:
3739 - check_mips_mt(env, ctx); 3725 + check_insn(env, ctx, ASE_MT);
3740 gen_op_mtc0_yqmask(); 3726 gen_op_mtc0_yqmask();
3741 rn = "YQMask"; 3727 rn = "YQMask";
3742 break; 3728 break;
3743 case 5: 3729 case 5:
3744 - check_mips_mt(env, ctx); 3730 + check_insn(env, ctx, ASE_MT);
3745 gen_op_mtc0_vpeschedule(); 3731 gen_op_mtc0_vpeschedule();
3746 rn = "VPESchedule"; 3732 rn = "VPESchedule";
3747 break; 3733 break;
3748 case 6: 3734 case 6:
3749 - check_mips_mt(env, ctx); 3735 + check_insn(env, ctx, ASE_MT);
3750 gen_op_mtc0_vpeschefback(); 3736 gen_op_mtc0_vpeschefback();
3751 rn = "VPEScheFBack"; 3737 rn = "VPEScheFBack";
3752 break; 3738 break;
3753 case 7: 3739 case 7:
3754 - check_mips_mt(env, ctx); 3740 + check_insn(env, ctx, ASE_MT);
3755 gen_op_mtc0_vpeopt(); 3741 gen_op_mtc0_vpeopt();
3756 rn = "VPEOpt"; 3742 rn = "VPEOpt";
3757 break; 3743 break;
@@ -3766,37 +3752,37 @@ static void gen_dmtc0 (CPUState *env, DisasContext *ctx, int reg, int sel) @@ -3766,37 +3752,37 @@ static void gen_dmtc0 (CPUState *env, DisasContext *ctx, int reg, int sel)
3766 rn = "EntryLo0"; 3752 rn = "EntryLo0";
3767 break; 3753 break;
3768 case 1: 3754 case 1:
3769 - check_mips_mt(env, ctx); 3755 + check_insn(env, ctx, ASE_MT);
3770 gen_op_mtc0_tcstatus(); 3756 gen_op_mtc0_tcstatus();
3771 rn = "TCStatus"; 3757 rn = "TCStatus";
3772 break; 3758 break;
3773 case 2: 3759 case 2:
3774 - check_mips_mt(env, ctx); 3760 + check_insn(env, ctx, ASE_MT);
3775 gen_op_mtc0_tcbind(); 3761 gen_op_mtc0_tcbind();
3776 rn = "TCBind"; 3762 rn = "TCBind";
3777 break; 3763 break;
3778 case 3: 3764 case 3:
3779 - check_mips_mt(env, ctx); 3765 + check_insn(env, ctx, ASE_MT);
3780 gen_op_mtc0_tcrestart(); 3766 gen_op_mtc0_tcrestart();
3781 rn = "TCRestart"; 3767 rn = "TCRestart";
3782 break; 3768 break;
3783 case 4: 3769 case 4:
3784 - check_mips_mt(env, ctx); 3770 + check_insn(env, ctx, ASE_MT);
3785 gen_op_mtc0_tchalt(); 3771 gen_op_mtc0_tchalt();
3786 rn = "TCHalt"; 3772 rn = "TCHalt";
3787 break; 3773 break;
3788 case 5: 3774 case 5:
3789 - check_mips_mt(env, ctx); 3775 + check_insn(env, ctx, ASE_MT);
3790 gen_op_mtc0_tccontext(); 3776 gen_op_mtc0_tccontext();
3791 rn = "TCContext"; 3777 rn = "TCContext";
3792 break; 3778 break;
3793 case 6: 3779 case 6:
3794 - check_mips_mt(env, ctx); 3780 + check_insn(env, ctx, ASE_MT);
3795 gen_op_mtc0_tcschedule(); 3781 gen_op_mtc0_tcschedule();
3796 rn = "TCSchedule"; 3782 rn = "TCSchedule";
3797 break; 3783 break;
3798 case 7: 3784 case 7:
3799 - check_mips_mt(env, ctx); 3785 + check_insn(env, ctx, ASE_MT);
3800 gen_op_mtc0_tcschefback(); 3786 gen_op_mtc0_tcschefback();
3801 rn = "TCScheFBack"; 3787 rn = "TCScheFBack";
3802 break; 3788 break;
@@ -4636,7 +4622,7 @@ static void gen_cp0 (CPUState *env, DisasContext *ctx, uint32_t opc, int rt, int @@ -4636,7 +4622,7 @@ static void gen_cp0 (CPUState *env, DisasContext *ctx, uint32_t opc, int rt, int
4636 break; 4622 break;
4637 #endif 4623 #endif
4638 case OPC_MFTR: 4624 case OPC_MFTR:
4639 - check_mips_mt(env, ctx); 4625 + check_insn(env, ctx, ASE_MT);
4640 if (rd == 0) { 4626 if (rd == 0) {
4641 /* Treat as NOP. */ 4627 /* Treat as NOP. */
4642 return; 4628 return;
@@ -4647,7 +4633,7 @@ static void gen_cp0 (CPUState *env, DisasContext *ctx, uint32_t opc, int rt, int @@ -4647,7 +4633,7 @@ static void gen_cp0 (CPUState *env, DisasContext *ctx, uint32_t opc, int rt, int
4647 opn = "mftr"; 4633 opn = "mftr";
4648 break; 4634 break;
4649 case OPC_MTTR: 4635 case OPC_MTTR:
4650 - check_mips_mt(env, ctx); 4636 + check_insn(env, ctx, ASE_MT);
4651 GEN_LOAD_REG_TN(T0, rt); 4637 GEN_LOAD_REG_TN(T0, rt);
4652 gen_mttr(env, ctx, rd, (ctx->opcode >> 5) & 1, 4638 gen_mttr(env, ctx, rd, (ctx->opcode >> 5) & 1,
4653 ctx->opcode & 0x7, (ctx->opcode >> 4) & 1); 4639 ctx->opcode & 0x7, (ctx->opcode >> 4) & 1);
@@ -5893,7 +5879,6 @@ static void gen_flt3_arith (DisasContext *ctx, uint32_t opc, @@ -5893,7 +5879,6 @@ static void gen_flt3_arith (DisasContext *ctx, uint32_t opc,
5893 #if defined(TARGET_MIPSN32) || defined(TARGET_MIPS64) 5879 #if defined(TARGET_MIPSN32) || defined(TARGET_MIPS64)
5894 5880
5895 /* MDMX extension to MIPS64 */ 5881 /* MDMX extension to MIPS64 */
5896 -/* MIPS-3D extension to MIPS64 */  
5897 5882
5898 #endif 5883 #endif
5899 5884
@@ -6133,13 +6118,13 @@ static void decode_opc (CPUState *env, DisasContext *ctx) @@ -6133,13 +6118,13 @@ static void decode_opc (CPUState *env, DisasContext *ctx)
6133 GEN_STORE_TN_REG(rt, T0); 6118 GEN_STORE_TN_REG(rt, T0);
6134 break; 6119 break;
6135 case OPC_FORK: 6120 case OPC_FORK:
6136 - check_mips_mt(env, ctx); 6121 + check_insn(env, ctx, ASE_MT);
6137 GEN_LOAD_REG_TN(T0, rt); 6122 GEN_LOAD_REG_TN(T0, rt);
6138 GEN_LOAD_REG_TN(T1, rs); 6123 GEN_LOAD_REG_TN(T1, rs);
6139 gen_op_fork(); 6124 gen_op_fork();
6140 break; 6125 break;
6141 case OPC_YIELD: 6126 case OPC_YIELD:
6142 - check_mips_mt(env, ctx); 6127 + check_insn(env, ctx, ASE_MT);
6143 GEN_LOAD_REG_TN(T0, rs); 6128 GEN_LOAD_REG_TN(T0, rs);
6144 gen_op_yield(); 6129 gen_op_yield();
6145 GEN_STORE_TN_REG(rd, T0); 6130 GEN_STORE_TN_REG(rd, T0);
@@ -6219,19 +6204,19 @@ static void decode_opc (CPUState *env, DisasContext *ctx) @@ -6219,19 +6204,19 @@ static void decode_opc (CPUState *env, DisasContext *ctx)
6219 op2 = MASK_MFMC0(ctx->opcode); 6204 op2 = MASK_MFMC0(ctx->opcode);
6220 switch (op2) { 6205 switch (op2) {
6221 case OPC_DMT: 6206 case OPC_DMT:
6222 - check_mips_mt(env, ctx); 6207 + check_insn(env, ctx, ASE_MT);
6223 gen_op_dmt(); 6208 gen_op_dmt();
6224 break; 6209 break;
6225 case OPC_EMT: 6210 case OPC_EMT:
6226 - check_mips_mt(env, ctx); 6211 + check_insn(env, ctx, ASE_MT);
6227 gen_op_emt(); 6212 gen_op_emt();
6228 break; 6213 break;
6229 case OPC_DVPE: 6214 case OPC_DVPE:
6230 - check_mips_mt(env, ctx); 6215 + check_insn(env, ctx, ASE_MT);
6231 gen_op_dvpe(); 6216 gen_op_dvpe();
6232 break; 6217 break;
6233 case OPC_EVPE: 6218 case OPC_EVPE:
6234 - check_mips_mt(env, ctx); 6219 + check_insn(env, ctx, ASE_MT);
6235 gen_op_evpe(); 6220 gen_op_evpe();
6236 break; 6221 break;
6237 case OPC_DI: 6222 case OPC_DI:
@@ -6336,7 +6321,7 @@ static void decode_opc (CPUState *env, DisasContext *ctx) @@ -6336,7 +6321,7 @@ static void decode_opc (CPUState *env, DisasContext *ctx)
6336 #endif 6321 #endif
6337 case OPC_BC1ANY2: 6322 case OPC_BC1ANY2:
6338 case OPC_BC1ANY4: 6323 case OPC_BC1ANY4:
6339 - check_cp1_3d(env, ctx); 6324 + check_insn(env, ctx, ASE_MIPS3D);
6340 /* fall through */ 6325 /* fall through */
6341 case OPC_BC1: 6326 case OPC_BC1:
6342 gen_compute_branch1(env, ctx, MASK_BC1(ctx->opcode), 6327 gen_compute_branch1(env, ctx, MASK_BC1(ctx->opcode),
target-mips/translate_init.c
  View file @7385ac0
@@ -199,7 +199,7 @@ static mips_def_t mips_defs[] = @@ -199,7 +199,7 @@ static mips_def_t mips_defs[] =
199 .CP0_SRSConf4_rw_bitmask = 0x3fffffff, 199 .CP0_SRSConf4_rw_bitmask = 0x3fffffff,
200 .CP0_SRSConf4 = (0x3fe << CP0SRSC4_SRS15) | 200 .CP0_SRSConf4 = (0x3fe << CP0SRSC4_SRS15) |
201 (0x3fe << CP0SRSC4_SRS14) | (0x3fe << CP0SRSC4_SRS13), 201 (0x3fe << CP0SRSC4_SRS14) | (0x3fe << CP0SRSC4_SRS13),
202 - .insn_flags = CPU_MIPS32R2 | ASE_MIPS16 | ASE_DSP, 202 + .insn_flags = CPU_MIPS32R2 | ASE_MIPS16 | ASE_DSP | ASE_MT,
203 }, 203 },
204 #if defined(TARGET_MIPSN32) || defined(TARGET_MIPS64) 204 #if defined(TARGET_MIPSN32) || defined(TARGET_MIPS64)
205 { 205 {