Commit 73133662c6db9e58d02716d9517b3947c853de68
1 parent
bf82d818
i8259 PIC support
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@1486 c046a42c-6fe2-441c-8c8c-71466251a162
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7 additions
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62 deletions
hw/mips_r4k.c
1 | #include "vl.h" | 1 | #include "vl.h" |
2 | 2 | ||
3 | -#define DEBUG_IRQ_COUNT | ||
4 | - | ||
5 | #define BIOS_FILENAME "mips_bios.bin" | 3 | #define BIOS_FILENAME "mips_bios.bin" |
6 | //#define BIOS_FILENAME "system.bin" | 4 | //#define BIOS_FILENAME "system.bin" |
7 | #define KERNEL_LOAD_ADDR 0x80010000 | 5 | #define KERNEL_LOAD_ADDR 0x80010000 |
8 | #define INITRD_LOAD_ADDR 0x80800000 | 6 | #define INITRD_LOAD_ADDR 0x80800000 |
9 | 7 | ||
10 | -/* MIPS R4K IRQ controler */ | ||
11 | -#if defined(DEBUG_IRQ_COUNT) | ||
12 | -static uint64_t irq_count[16]; | ||
13 | -#endif | ||
14 | - | ||
15 | extern FILE *logfile; | 8 | extern FILE *logfile; |
16 | 9 | ||
17 | -void mips_set_irq (int n_IRQ, int level) | 10 | +static void pic_irq_request(void *opaque, int level) |
18 | { | 11 | { |
19 | - uint32_t mask; | ||
20 | - | ||
21 | - if (n_IRQ < 0 || n_IRQ >= 8) | ||
22 | - return; | ||
23 | - mask = 0x100 << n_IRQ; | ||
24 | - if (level != 0) { | ||
25 | -#if 1 | ||
26 | - if (logfile) { | ||
27 | - fprintf(logfile, "%s n %d l %d mask %08x %08x\n", | ||
28 | - __func__, n_IRQ, level, mask, cpu_single_env->CP0_Status); | ||
29 | - } | ||
30 | -#endif | ||
31 | - cpu_single_env->CP0_Cause |= mask; | ||
32 | - if ((cpu_single_env->CP0_Status & 0x00000001) && | ||
33 | - (cpu_single_env->CP0_Status & mask)) { | ||
34 | -#if defined(DEBUG_IRQ_COUNT) | ||
35 | - irq_count[n_IRQ]++; | ||
36 | -#endif | ||
37 | -#if 1 | ||
38 | - if (logfile) | ||
39 | - fprintf(logfile, "%s raise IRQ\n", __func__); | ||
40 | -#endif | ||
41 | - cpu_interrupt(cpu_single_env, CPU_INTERRUPT_HARD); | ||
42 | - } | 12 | + if (level) { |
13 | + cpu_single_env->CP0_Cause |= 0x00000400; | ||
14 | + cpu_interrupt(cpu_single_env, CPU_INTERRUPT_HARD); | ||
43 | } else { | 15 | } else { |
44 | - cpu_single_env->CP0_Cause &= ~mask; | ||
45 | - } | ||
46 | -} | ||
47 | - | ||
48 | -void pic_set_irq (int n_IRQ, int level) | ||
49 | -{ | ||
50 | - mips_set_irq(n_IRQ + 2, level); | ||
51 | -} | ||
52 | - | ||
53 | -void pic_info (void) | ||
54 | -{ | ||
55 | - term_printf("IRQ asserted: %02x mask: %02x\n", | ||
56 | - (cpu_single_env->CP0_Cause >> 8) & 0xFF, | ||
57 | - (cpu_single_env->CP0_Status >> 8) & 0xFF); | ||
58 | -} | ||
59 | - | ||
60 | -void irq_info (void) | ||
61 | -{ | ||
62 | -#if !defined(DEBUG_IRQ_COUNT) | ||
63 | - term_printf("irq statistic code not compiled.\n"); | ||
64 | -#else | ||
65 | - int i; | ||
66 | - int64_t count; | ||
67 | - | ||
68 | - term_printf("IRQ statistics:\n"); | ||
69 | - for (i = 0; i < 8; i++) { | ||
70 | - count = irq_count[i]; | ||
71 | - if (count > 0) | ||
72 | - term_printf("%2d: %lld\n", i, count); | 16 | + cpu_single_env->CP0_Cause &= ~0x00000400; |
17 | + cpu_reset_interrupt(cpu_single_env, CPU_INTERRUPT_HARD); | ||
73 | } | 18 | } |
74 | -#endif | ||
75 | } | 19 | } |
76 | 20 | ||
77 | void cpu_mips_irqctrl_init (void) | 21 | void cpu_mips_irqctrl_init (void) |
@@ -295,6 +239,7 @@ void mips_r4k_init (int ram_size, int vga_ram_size, int boot_device, | @@ -295,6 +239,7 @@ void mips_r4k_init (int ram_size, int vga_ram_size, int boot_device, | ||
295 | cpu_register_physical_memory(0x14000000, 0x00010000, io_memory); | 239 | cpu_register_physical_memory(0x14000000, 0x00010000, io_memory); |
296 | isa_mem_base = 0x10000000; | 240 | isa_mem_base = 0x10000000; |
297 | 241 | ||
242 | + isa_pic = pic_init(pic_irq_request, cpu_single_env); | ||
298 | serial_init(0x3f8, 4, serial_hds[0]); | 243 | serial_init(0x3f8, 4, serial_hds[0]); |
299 | vga_initialize(NULL, ds, phys_ram_base + ram_size, ram_size, | 244 | vga_initialize(NULL, ds, phys_ram_base + ram_size, ram_size, |
300 | vga_ram_size); | 245 | vga_ram_size); |