gwj / at91sam9263 · Commits

Commit 72ccba795bbd3668e9dc3a26fda1444b8fb1621b

Authored by blueswir1
1 parent 7c96d46e

Fix mulscc with high bits set in either src1 or src2 

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5201 c046a42c-6fe2-441c-8c8c-71466251a162
Inline Side-by-side
Showing 1 changed file with 3 additions and 2 deletions
target-sparc/translate.c
  View file @72ccba7
... ... @@ -697,9 +697,9 @@ static inline void gen_op_mulscc(TCGv dst, TCGv src1, TCGv src2)
697 697 if (!(env->y & 1))
698 698 T1 = 0;
699 699 */
700   - tcg_gen_mov_tl(cpu_cc_src, src1);
  700 + tcg_gen_andi_tl(cpu_cc_src, src1, 0xffffffff);
701 701 tcg_gen_andi_tl(r_temp, cpu_y, 0x1);
702   - tcg_gen_mov_tl(cpu_cc_src2, src2);
  702 + tcg_gen_andi_tl(cpu_cc_src2, src2, 0xffffffff);
703 703 tcg_gen_brcondi_tl(TCG_COND_NE, r_temp, 0, l1);
704 704 tcg_gen_movi_tl(cpu_cc_src2, 0);
705 705 gen_set_label(l1);
... ... @@ -709,6 +709,7 @@ static inline void gen_op_mulscc(TCGv dst, TCGv src1, TCGv src2)
709 709 tcg_gen_andi_tl(r_temp, cpu_cc_src, 0x1);
710 710 tcg_gen_shli_tl(r_temp, r_temp, 31);
711 711 tcg_gen_shri_tl(cpu_tmp0, cpu_y, 1);
  712 + tcg_gen_andi_tl(cpu_tmp0, cpu_tmp0, 0x7fffffff);
712 713 tcg_gen_or_tl(cpu_tmp0, cpu_tmp0, r_temp);
713 714 tcg_gen_andi_tl(cpu_y, cpu_tmp0, 0xffffffff);
714 715  
... ...