gwj / at91sam9263 · Commits

Commit 72c3a3ee4d57a335164f51689d99dc69472203da

Authored by aurel32
1 parent 1fc7bf6e

target-mips: optimize gen_cp1() 

Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@7041 c046a42c-6fe2-441c-8c8c-71466251a162
Inline Side-by-side
Showing 1 changed file with 5 additions and 15 deletions
target-mips/translate.c
  View file @72c3a3e
@@ -5578,7 +5578,7 @@ static void gen_compute_branch1 (CPUState *env, DisasContext *ctx, uint32_t op, @@ -5578,7 +5578,7 @@ static void gen_compute_branch1 (CPUState *env, DisasContext *ctx, uint32_t op,
5578 static void gen_cp1 (DisasContext *ctx, uint32_t opc, int rt, int fs) 5578 static void gen_cp1 (DisasContext *ctx, uint32_t opc, int rt, int fs)
5579 { 5579 {
5580 const char *opn = "cp1 move"; 5580 const char *opn = "cp1 move";
5581 - TCGv t0 = tcg_temp_local_new(); 5581 + TCGv t0 = tcg_temp_new();
5582 5582
5583 switch (opc) { 5583 switch (opc) {
5584 case OPC_MFC1: 5584 case OPC_MFC1:
@@ -5613,28 +5613,18 @@ static void gen_cp1 (DisasContext *ctx, uint32_t opc, int rt, int fs) @@ -5613,28 +5613,18 @@ static void gen_cp1 (DisasContext *ctx, uint32_t opc, int rt, int fs)
5613 gen_helper_1i(ctc1, t0, fs); 5613 gen_helper_1i(ctc1, t0, fs);
5614 opn = "ctc1"; 5614 opn = "ctc1";
5615 break; 5615 break;
  5616 +#if defined(TARGET_MIPS64)
5616 case OPC_DMFC1: 5617 case OPC_DMFC1:
5617 - {  
5618 - TCGv_i64 fp0 = tcg_temp_new_i64();  
5619 -  
5620 - gen_load_fpr64(ctx, fp0, fs);  
5621 - tcg_gen_trunc_i64_tl(t0, fp0);  
5622 - tcg_temp_free_i64(fp0);  
5623 - } 5618 + gen_load_fpr64(ctx, t0, fs);
5624 gen_store_gpr(t0, rt); 5619 gen_store_gpr(t0, rt);
5625 opn = "dmfc1"; 5620 opn = "dmfc1";
5626 break; 5621 break;
5627 case OPC_DMTC1: 5622 case OPC_DMTC1:
5628 gen_load_gpr(t0, rt); 5623 gen_load_gpr(t0, rt);
5629 - {  
5630 - TCGv_i64 fp0 = tcg_temp_new_i64();  
5631 -  
5632 - tcg_gen_extu_tl_i64(fp0, t0);  
5633 - gen_store_fpr64(ctx, fp0, fs);  
5634 - tcg_temp_free_i64(fp0);  
5635 - } 5624 + gen_store_fpr64(ctx, t0, fs);
5636 opn = "dmtc1"; 5625 opn = "dmtc1";
5637 break; 5626 break;
  5627 +#endif
5638 case OPC_MFHC1: 5628 case OPC_MFHC1:
5639 { 5629 {
5640 TCGv_i32 fp0 = tcg_temp_new_i32(); 5630 TCGv_i32 fp0 = tcg_temp_new_i32();