gwj / at91sam9263 · Commits

Commit 72af9170882c435d19705f774f62828467d63e87

Authored by Edgar E. Iglesias
1 parent f2964260

ETRAX: Simplify serport control logic. 

Signed-off-by: Edgar E. Iglesias <edgar.iglesias@gmail.com>
Inline Side-by-side
Showing 1 changed file with 44 additions and 83 deletions
hw/etraxfs_ser.c
  View file @72af917
... ... @@ -30,16 +30,17 @@
30 30  
31 31 #define D(x)
32 32  
33   -#define RW_TR_CTRL 0x00
34   -#define RW_TR_DMA_EN 0x04
35   -#define RW_REC_CTRL 0x08
36   -#define RW_DOUT 0x1c
37   -#define RS_STAT_DIN 0x20
38   -#define R_STAT_DIN 0x24
39   -#define RW_INTR_MASK 0x2c
40   -#define RW_ACK_INTR 0x30
41   -#define R_INTR 0x34
42   -#define R_MASKED_INTR 0x38
  33 +#define RW_TR_CTRL (0x00 / 4)
  34 +#define RW_TR_DMA_EN (0x04 / 4)
  35 +#define RW_REC_CTRL (0x08 / 4)
  36 +#define RW_DOUT (0x1c / 4)
  37 +#define RS_STAT_DIN (0x20 / 4)
  38 +#define R_STAT_DIN (0x24 / 4)
  39 +#define RW_INTR_MASK (0x2c / 4)
  40 +#define RW_ACK_INTR (0x30 / 4)
  41 +#define R_INTR (0x34 / 4)
  42 +#define R_MASKED_INTR (0x38 / 4)
  43 +#define R_MAX (0x3c / 4)
43 44  
44 45 #define STAT_DAV 16
45 46 #define STAT_TR_IDLE 22
... ... @@ -51,30 +52,20 @@ struct etrax_serial
51 52 CharDriverState *chr;
52 53 qemu_irq *irq;
53 54  
  55 + /* This pending thing is a hack. */
54 56 int pending_tx;
55 57  
56 58 /* Control registers. */
57   - uint32_t rw_tr_ctrl;
58   - uint32_t rw_tr_dma_en;
59   - uint32_t rw_rec_ctrl;
60   - uint32_t rs_stat_din;
61   - uint32_t r_stat_din;
62   - uint32_t rw_intr_mask;
63   - uint32_t rw_ack_intr;
64   - uint32_t r_intr;
65   - uint32_t r_masked_intr;
  59 + uint32_t regs[R_MAX];
66 60 };
67 61  
68 62 static void ser_update_irq(struct etrax_serial *s)
69 63 {
70   - s->r_intr &= ~(s->rw_ack_intr);
71   - s->r_masked_intr = s->r_intr & s->rw_intr_mask;
72   -
73   - D(printf("irq_mask=%x r_intr=%x rmi=%x airq=%x \n",
74   - s->rw_intr_mask, s->r_intr,
75   - s->r_masked_intr, s->rw_ack_intr));
76   - qemu_set_irq(s->irq[0], !!s->r_masked_intr);
77   - s->rw_ack_intr = 0;
  64 + s->regs[R_INTR] &= ~(s->regs[RW_ACK_INTR]);
  65 + s->regs[R_MASKED_INTR] = s->regs[R_INTR] & s->regs[RW_INTR_MASK];
  66 +
  67 + qemu_set_irq(s->irq[0], !!s->regs[R_MASKED_INTR]);
  68 + s->regs[RW_ACK_INTR] = 0;
78 69 }
79 70  
80 71 static uint32_t ser_readl (void *opaque, target_phys_addr_t addr)
... ... @@ -83,40 +74,20 @@ static uint32_t ser_readl (void *opaque, target_phys_addr_t addr)
83 74 D(CPUState *env = s->env);
84 75 uint32_t r = 0;
85 76  
  77 + addr >>= 2;
86 78 switch (addr)
87 79 {
88   - case RW_TR_CTRL:
89   - r = s->rw_tr_ctrl;
90   - break;
91   - case RW_TR_DMA_EN:
92   - r = s->rw_tr_dma_en;
93   - break;
94   - case RS_STAT_DIN:
95   - r = s->rs_stat_din;
96   - /* clear dav. */
97   - s->rs_stat_din &= ~(1 << STAT_DAV);
98   - break;
99 80 case R_STAT_DIN:
100   - r = s->rs_stat_din;
101   - break;
102   - case RW_ACK_INTR:
103   - D(printf("load rw_ack_intr=%x\n", s->rw_ack_intr));
104   - r = s->rw_ack_intr;
  81 + r = s->regs[RS_STAT_DIN];
105 82 break;
106   - case RW_INTR_MASK:
107   - r = s->rw_intr_mask;
108   - break;
109   - case R_INTR:
110   - D(printf("load r_intr=%x\n", s->r_intr));
111   - r = s->r_intr;
112   - break;
113   - case R_MASKED_INTR:
114   - D(printf("load r_maked_intr=%x\n", s->r_masked_intr));
115   - r = s->r_masked_intr;
  83 + case RS_STAT_DIN:
  84 + r = s->regs[addr];
  85 + /* Read side-effect: clear dav. */
  86 + s->regs[addr] &= ~(1 << STAT_DAV);
116 87 break;
117   -
118 88 default:
119   - D(printf ("%s %x\n", __func__, addr));
  89 + r = s->regs[addr];
  90 + D(printf ("%s %x=%x\n", __func__, addr, r));
120 91 break;
121 92 }
122 93 return r;
... ... @@ -129,36 +100,26 @@ ser_writel (void *opaque, target_phys_addr_t addr, uint32_t value)
129 100 unsigned char ch = value;
130 101 D(CPUState *env = s->env);
131 102  
  103 + D(printf ("%s %x %x\n", __func__, addr, value));
  104 + addr >>= 2;
132 105 switch (addr)
133 106 {
134   - case RW_TR_CTRL:
135   - D(printf("rw_tr_ctrl=%x\n", value));
136   - s->rw_tr_ctrl = value;
137   - break;
138   - case RW_TR_DMA_EN:
139   - D(printf("rw_tr_dma_en=%x\n", value));
140   - s->rw_tr_dma_en = value;
141   - break;
142 107 case RW_DOUT:
143 108 qemu_chr_write(s->chr, &ch, 1);
144   - s->r_intr |= 1;
  109 + s->regs[R_INTR] |= 1;
145 110 s->pending_tx = 1;
  111 + s->regs[addr] = value;
146 112 break;
147 113 case RW_ACK_INTR:
148   - D(printf("rw_ack_intr=%x\n", value));
149   - s->rw_ack_intr = value;
150   - if (s->pending_tx && (s->rw_ack_intr & 1)) {
151   - s->r_intr |= 1;
  114 + s->regs[addr] = value;
  115 + if (s->pending_tx && (s->regs[addr] & 1)) {
  116 + s->regs[R_INTR] |= 1;
152 117 s->pending_tx = 0;
153   - s->rw_ack_intr &= ~1;
  118 + s->regs[addr] &= ~1;
154 119 }
155 120 break;
156   - case RW_INTR_MASK:
157   - D(printf("r_intr_mask=%x\n", value));
158   - s->rw_intr_mask = value;
159   - break;
160 121 default:
161   - D(printf ("%s %x %x\n", __func__, addr, value));
  122 + s->regs[addr] = value;
162 123 break;
163 124 }
164 125 ser_update_irq(s);
... ... @@ -178,10 +139,10 @@ static void serial_receive(void *opaque, const uint8_t *buf, int size)
178 139 {
179 140 struct etrax_serial *s = opaque;
180 141  
181   - s->r_intr |= 8;
182   - s->rs_stat_din &= ~0xff;
183   - s->rs_stat_din |= (buf[0] & 0xff);
184   - s->rs_stat_din |= (1 << STAT_DAV); /* dav. */
  142 + s->regs[R_INTR] |= 8;
  143 + s->regs[RS_STAT_DIN] &= ~0xff;
  144 + s->regs[RS_STAT_DIN] |= (buf[0] & 0xff);
  145 + s->regs[RS_STAT_DIN] |= (1 << STAT_DAV); /* dav. */
185 146 ser_update_irq(s);
186 147 }
187 148  
... ... @@ -191,10 +152,10 @@ static int serial_can_receive(void *opaque)
191 152 int r;
192 153  
193 154 /* Is the receiver enabled? */
194   - r = s->rw_rec_ctrl & 1;
  155 + r = s->regs[RW_REC_CTRL] & 1;
195 156  
196 157 /* Pending rx data? */
197   - r |= !(s->r_intr & 8);
  158 + r |= !(s->regs[R_INTR] & 8);
198 159 return r;
199 160 }
200 161  
... ... @@ -216,12 +177,12 @@ void etraxfs_ser_init(CPUState *env, qemu_irq *irq, CharDriverState *chr,
216 177 s->chr = chr;
217 178  
218 179 /* transmitter begins ready and idle. */
219   - s->rs_stat_din |= (1 << STAT_TR_RDY);
220   - s->rs_stat_din |= (1 << STAT_TR_IDLE);
  180 + s->regs[RS_STAT_DIN] |= (1 << STAT_TR_RDY);
  181 + s->regs[RS_STAT_DIN] |= (1 << STAT_TR_IDLE);
221 182  
222 183 qemu_chr_add_handlers(chr, serial_can_receive, serial_receive,
223 184 serial_event, s);
224 185  
225 186 ser_regs = cpu_register_io_memory(0, ser_read, ser_write, s);
226   - cpu_register_physical_memory (base, 0x3c, ser_regs);
  187 + cpu_register_physical_memory (base, R_MAX * 4, ser_regs);
227 188 }
... ...