gwj / at91sam9263 · Commits

Commit 725cb90bf7e2487fe5aa5621cc10afe6d169e310

Authored by bellard
1 parent a3c25997

sparc64 fixes (Blue Swirl) 


git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@2062 c046a42c-6fe2-441c-8c8c-71466251a162
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Showing 4 changed files with 72 additions and 4 deletions
sparc-dis.c
  View file @725cb90
... ... @@ -2887,7 +2887,9 @@ print_insn_sparc (memaddr, info)
2887 2887 {
2888 2888 const char *name;
2889 2889  
2890   - if (info->mach == bfd_mach_sparc_v9)
  2890 + if ((info->mach == bfd_mach_sparc_v8plusa) ||
  2891 + ((info->mach >= bfd_mach_sparc_v9) &&
  2892 + (info->mach <= bfd_mach_sparc_v9b)))
2891 2893 name = sparc_decode_asi_v9 (X_ASI (insn));
2892 2894 else
2893 2895 name = sparc_decode_asi_v8 (X_ASI (insn));
... ...
target-sparc/cpu.h
  View file @725cb90
... ... @@ -210,6 +210,7 @@ typedef struct CPUSPARCState {
210 210 uint64_t version;
211 211 uint64_t fprs;
212 212 uint64_t tick_cmpr, stick_cmpr;
  213 + uint64_t gsr;
213 214 #endif
214 215 #if !defined(TARGET_SPARC64) && !defined(reg_T2)
215 216 target_ulong t2;
... ...
target-sparc/op.c
  View file @725cb90
... ... @@ -1514,6 +1514,9 @@ void OPPROTO op_saved(void)
1514 1514 env->cansave++;
1515 1515 if (env->otherwin == 0)
1516 1516 env->canrestore--;
  1517 + else
  1518 + env->otherwin--;
  1519 + FORCE_RET();
1517 1520 }
1518 1521  
1519 1522 void OPPROTO op_restored(void)
... ... @@ -1525,6 +1528,7 @@ void OPPROTO op_restored(void)
1525 1528 env->cansave--;
1526 1529 else
1527 1530 env->otherwin--;
  1531 + FORCE_RET();
1528 1532 }
1529 1533  
1530 1534 void OPPROTO op_popc(void)
... ... @@ -1571,3 +1575,23 @@ void OPPROTO op_st_asi()
1571 1575 helper_st_asi(PARAM1, PARAM2, PARAM3);
1572 1576 }
1573 1577  
  1578 +#ifdef TARGET_SPARC64
  1579 +void OPPROTO op_alignaddr()
  1580 +{
  1581 + uint64_t tmp;
  1582 +
  1583 + tmp = T0 + T1;
  1584 + env->gsr &= ~7ULL;
  1585 + env->gsr |= tmp & 7ULL;
  1586 + T0 = tmp & ~7ULL;
  1587 +}
  1588 +
  1589 +void OPPROTO op_faligndata()
  1590 +{
  1591 + uint64_t tmp;
  1592 +
  1593 + tmp = (*((uint64_t *)&DT0)) << ((env->gsr & 7) * 8);
  1594 + tmp |= (*((uint64_t *)&DT1)) >> (64 - (env->gsr & 7) * 8);
  1595 + (*((uint64_t *)&DT0)) = tmp;
  1596 +}
  1597 +#endif
... ...
target-sparc/translate.c
  View file @725cb90
... ... @@ -364,6 +364,9 @@ GEN32(gen_op_store_DT1_fpr, gen_op_store_DT1_fpr_fprf);
364 364 case 0x80: /* Primary address space */ \
365 365 gen_op_##width##_raw(); \
366 366 break; \
  367 + case 0x82: /* Primary address space, non-faulting load */ \
  368 + gen_op_##width##_raw(); \
  369 + break; \
367 370 default: \
368 371 break; \
369 372 } \
... ... @@ -1151,6 +1154,12 @@ static void disas_sparc_insn(DisasContext * dc)
1151 1154 gen_op_movl_T0_env(offsetof(CPUSPARCState, fprs));
1152 1155 gen_movl_T0_reg(rd);
1153 1156 break;
  1157 + case 0x13: /* Graphics Status */
  1158 + if (gen_trap_ifnofpu(dc))
  1159 + goto jmp_insn;
  1160 + gen_op_movtl_T0_env(offsetof(CPUSPARCState, gsr));
  1161 + gen_movl_T0_reg(rd);
  1162 + break;
1154 1163 case 0x17: /* Tick compare */
1155 1164 gen_op_movtl_T0_env(offsetof(CPUSPARCState, tick_cmpr));
1156 1165 gen_movl_T0_reg(rd);
... ... @@ -1166,7 +1175,6 @@ static void disas_sparc_insn(DisasContext * dc)
1166 1175 case 0x10: /* Performance Control */
1167 1176 case 0x11: /* Performance Instrumentation Counter */
1168 1177 case 0x12: /* Dispatch Control */
1169   - case 0x13: /* Graphics Status */
1170 1178 case 0x14: /* Softint set, WO */
1171 1179 case 0x15: /* Softint clear, WO */
1172 1180 case 0x16: /* Softint write */
... ... @@ -1870,6 +1878,11 @@ static void disas_sparc_insn(DisasContext * dc)
1870 1878 gen_op_sir();
1871 1879 #endif
1872 1880 break;
  1881 + case 0x13: /* Graphics Status */
  1882 + if (gen_trap_ifnofpu(dc))
  1883 + goto jmp_insn;
  1884 + gen_op_movtl_env_T0(offsetof(CPUSPARCState, gsr));
  1885 + break;
1873 1886 case 0x17: /* Tick compare */
1874 1887 #if !defined(CONFIG_USER_ONLY)
1875 1888 if (!supervisor(dc))
... ... @@ -1895,7 +1908,6 @@ static void disas_sparc_insn(DisasContext * dc)
1895 1908 case 0x10: /* Performance Control */
1896 1909 case 0x11: /* Performance Instrumentation Counter */
1897 1910 case 0x12: /* Dispatch Control */
1898   - case 0x13: /* Graphics Status */
1899 1911 case 0x14: /* Softint set */
1900 1912 case 0x15: /* Softint clear */
1901 1913 case 0x16: /* Softint write */
... ... @@ -2077,7 +2089,36 @@ static void disas_sparc_insn(DisasContext * dc)
2077 2089 }
2078 2090 case 0x36: /* UltraSparc shutdown, VIS */
2079 2091 {
2080   - // XXX
  2092 + int opf = GET_FIELD_SP(insn, 5, 13);
  2093 + rs1 = GET_FIELD(insn, 13, 17);
  2094 + rs2 = GET_FIELD(insn, 27, 31);
  2095 +
  2096 + switch (opf) {
  2097 + case 0x018: /* VIS I alignaddr */
  2098 + if (gen_trap_ifnofpu(dc))
  2099 + goto jmp_insn;
  2100 + gen_movl_reg_T0(rs1);
  2101 + gen_movl_reg_T1(rs2);
  2102 + gen_op_alignaddr();
  2103 + gen_movl_T0_reg(rd);
  2104 + break;
  2105 + case 0x01a: /* VIS I alignaddrl */
  2106 + if (gen_trap_ifnofpu(dc))
  2107 + goto jmp_insn;
  2108 + // XXX
  2109 + break;
  2110 + case 0x048: /* VIS I faligndata */
  2111 + if (gen_trap_ifnofpu(dc))
  2112 + goto jmp_insn;
  2113 + gen_op_load_fpr_DT0(rs1);
  2114 + gen_op_load_fpr_DT1(rs2);
  2115 + gen_op_faligndata();
  2116 + gen_op_store_DT0_fpr(rd);
  2117 + break;
  2118 + default:
  2119 + goto illegal_insn;
  2120 + }
  2121 + break;
2081 2122 }
2082 2123 #endif
2083 2124 default:
... ...