gwj / at91sam9263 · Commits

Commit 71ac3b08ae5d60d9f21879691dc54633b9d88294

Authored by aliguori
1 parent 429d0a3d

Update bochs bios 

They have applied all of our patches and they have an additional HPET fix.

Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>



git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6289 c046a42c-6fe2-441c-8c8c-71466251a162
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Showing 6 changed files with 1 additions and 344 deletions
pc-bios/bios-pq/0002_e820-high-mem.patch deleted 100644 → 0
  View file @429d0a3
1   -From: Izik Eidus <izike@qumranet.com>
2   -
3   -add support to memory above the pci hole
4   -
5   -the new memory region is mapped after address 0x100000000,
6   -the bios take the size of the memory after the 0x100000000 from
7   -three new cmos bytes.
8   -
9   -diff --git a/bios/rombios.c b/bios/rombios.c
10   -index 1be0816..b70f249 100644
11   ---- a/bios/rombios.c
12   -+++ b/bios/rombios.c
13   -@@ -4442,22 +4442,25 @@ BX_DEBUG_INT15("case default:\n");
14   - #endif // BX_USE_PS2_MOUSE
15   -
16   -
17   --void set_e820_range(ES, DI, start, end, type)
18   -+void set_e820_range(ES, DI, start, end, extra_start, extra_end, type)
19   - Bit16u ES;
20   - Bit16u DI;
21   - Bit32u start;
22   - Bit32u end;
23   -+ Bit8u extra_start;
24   -+ Bit8u extra_end;
25   - Bit16u type;
26   - {
27   - write_word(ES, DI, start);
28   - write_word(ES, DI+2, start >> 16);
29   -- write_word(ES, DI+4, 0x00);
30   -+ write_word(ES, DI+4, extra_start);
31   - write_word(ES, DI+6, 0x00);
32   -
33   - end -= start;
34   -+ extra_end -= extra_start;
35   - write_word(ES, DI+8, end);
36   - write_word(ES, DI+10, end >> 16);
37   -- write_word(ES, DI+12, 0x0000);
38   -+ write_word(ES, DI+12, extra_end);
39   - write_word(ES, DI+14, 0x0000);
40   -
41   - write_word(ES, DI+16, type);
42   -@@ -4470,7 +4473,9 @@ int15_function32(regs, ES, DS, FLAGS)
43   - Bit16u ES, DS, FLAGS;
44   - {
45   - Bit32u extended_memory_size=0; // 64bits long
46   -+ Bit32u extra_lowbits_memory_size=0;
47   - Bit16u CX,DX;
48   -+ Bit8u extra_highbits_memory_size=0;
49   -
50   - BX_DEBUG_INT15("int15 AX=%04x\n",regs.u.r16.ax);
51   -
52   -@@ -4544,11 +4549,18 @@ ASM_END
53   - extended_memory_size += (1L * 1024 * 1024);
54   - }
55   -
56   -+ extra_lowbits_memory_size = inb_cmos(0x5c);
57   -+ extra_lowbits_memory_size <<= 8;
58   -+ extra_lowbits_memory_size |= inb_cmos(0x5b);
59   -+ extra_lowbits_memory_size *= 64;
60   -+ extra_lowbits_memory_size *= 1024;
61   -+ extra_highbits_memory_size = inb_cmos(0x5d);
62   -+
63   - switch(regs.u.r16.bx)
64   - {
65   - case 0:
66   - set_e820_range(ES, regs.u.r16.di,
67   -- 0x0000000L, 0x0009f000L, 1);
68   -+ 0x0000000L, 0x0009f000L, 0, 0, 1);
69   - regs.u.r32.ebx = 1;
70   - regs.u.r32.eax = 0x534D4150;
71   - regs.u.r32.ecx = 0x14;
72   -@@ -4557,7 +4569,7 @@ ASM_END
73   - break;
74   - case 1:
75   - set_e820_range(ES, regs.u.r16.di,
76   -- 0x0009f000L, 0x000a0000L, 2);
77   -+ 0x0009f000L, 0x000a0000L, 0, 0, 2);
78   - regs.u.r32.ebx = 2;
79   - regs.u.r32.eax = 0x534D4150;
80   - regs.u.r32.ecx = 0x14;
81   -@@ -4566,7 +4578,7 @@ ASM_END
82   - break;
83   - case 2:
84   - set_e820_range(ES, regs.u.r16.di,
85   -- 0x000e8000L, 0x00100000L, 2);
86   -+ 0x000e8000L, 0x00100000L, 0, 0, 2);
87   - regs.u.r32.ebx = 3;
88   - regs.u.r32.eax = 0x534D4150;
89   - regs.u.r32.ecx = 0x14;
90   -@@ -4577,7 +4589,7 @@ ASM_END
91   - #if BX_ROMBIOS32
92   - set_e820_range(ES, regs.u.r16.di,
93   - 0x00100000L,
94   -- extended_memory_size - ACPI_DATA_SIZE, 1);
95   -+ extended_memory_size - ACPI_DATA_SIZE ,0, 0, 1);
96   - regs.u.r32.ebx = 4;
97   - #else
98   - set_e820_range(ES, regs.u.r16.di,
99   -@@ -4593,7 +4605,7 @@ ASM_END
100   - case 4:
101   - set_e820_range(ES, regs.u.r16.di,
102   - extended_memory_size - ACPI_DATA_SIZE,
103   -- extended_memory_size, 3); // ACPI RAM
104   -+ extended_memory_size ,0, 0, 3); // ACPI RAM
105   - regs.u.r32.ebx = 5;
106   - regs.u.r32.eax = 0x534D4150;
107   - regs.u.r32.ecx = 0x14;
108   -@@ -4603,7 +4615,20 @@ ASM_END
109   - case 5:
110   - /* 256KB BIOS area at the end of 4 GB */
111   - set_e820_range(ES, regs.u.r16.di,
112   -- 0xfffc0000L, 0x00000000L, 2);
113   -+ 0xfffc0000L, 0x00000000L ,0, 0, 2);
114   -+ if (extra_highbits_memory_size || extra_lowbits_memory_size)
115   -+ regs.u.r32.ebx = 6;
116   -+ else
117   -+ regs.u.r32.ebx = 0;
118   -+ regs.u.r32.eax = 0x534D4150;
119   -+ regs.u.r32.ecx = 0x14;
120   -+ CLEAR_CF();
121   -+ return;
122   -+ case 6:
123   -+ /* Maping of memory above 4 GB */
124   -+ set_e820_range(ES, regs.u.r16.di, 0x00000000L,
125   -+ extra_lowbits_memory_size, 1, extra_highbits_memory_size
126   -+ + 1, 1);
127   - regs.u.r32.ebx = 0;
128   - regs.u.r32.eax = 0x534D4150;
129   - regs.u.r32.ecx = 0x14;
pc-bios/bios-pq/0003_smp-startup-poll.patch deleted 100644 → 0
  View file @429d0a3
1   -From: Avi Kivity <avi@qumranet.com>
2   -
3   -instead of timing out, wait until all cpus are up
4   -
5   -diff --git a/bios/rombios32.c b/bios/rombios32.c
6   -index ef98a41..05ba40d 100644
7   ---- a/bios/rombios32.c
8   -+++ b/bios/rombios32.c
9   -@@ -512,7 +512,12 @@ void smp_probe(void)
10   - sipi_vector = AP_BOOT_ADDR >> 12;
11   - writel(APIC_BASE + APIC_ICR_LOW, 0x000C4600 | sipi_vector);
12   -
13   -+#ifndef BX_QEMU
14   - delay_ms(10);
15   -+#else
16   -+ while (cmos_readb(0x5f) + 1 != readw(&smp_cpus))
17   -+ ;
18   -+#endif
19   - }
20   - BX_INFO("Found %d cpu(s)\n", readw(&smp_cpus));
21   - }
pc-bios/bios-pq/0005_hpet.patch deleted 100644 → 0
  View file @429d0a3
1   -BOCHS BIOS changes to support HPET in QEMU.
2   -
3   -Signed-off-by Beth Kon <eak@us.ibm.com>
4   -
5   -Index: bochs-2.3.7/bios/acpi-dsdt.dsl
6   -===================================================================
7   ---- bochs-2.3.7.orig/bios/acpi-dsdt.dsl 2008-10-15 12:39:14.000000000 -0500
8   -+++ bochs-2.3.7/bios/acpi-dsdt.dsl 2008-10-28 07:58:40.000000000 -0500
9   -@@ -159,6 +159,26 @@
10   - Return (MEMP)
11   - }
12   - }
13   -+#ifdef BX_QEMU
14   -+ Device(HPET) {
15   -+ Name(_HID, EISAID("PNP0103"))
16   -+ Name(_UID, 0)
17   -+ Method (_STA, 0, NotSerialized) {
18   -+ Return(0x0F)
19   -+ }
20   -+ Name(_CRS, ResourceTemplate() {
21   -+ DWordMemory(
22   -+ ResourceConsumer, PosDecode, MinFixed, MaxFixed,
23   -+ NonCacheable, ReadWrite,
24   -+ 0x00000000,
25   -+ 0xFED00000,
26   -+ 0xFED003FF,
27   -+ 0x00000000,
28   -+ 0x00000400 /* 1K memory: FED00000 - FED003FF */
29   -+ )
30   -+ })
31   -+ }
32   -+#endif
33   - }
34   -
35   - Scope(\_SB.PCI0) {
36   -Index: bochs-2.3.7/bios/rombios32.c
37   -===================================================================
38   ---- bochs-2.3.7.orig/bios/rombios32.c 2008-10-15 12:39:36.000000000 -0500
39   -+++ bochs-2.3.7/bios/rombios32.c 2008-11-12 14:41:41.000000000 -0600
40   -@@ -1087,7 +1087,11 @@
41   - struct rsdt_descriptor_rev1
42   - {
43   - ACPI_TABLE_HEADER_DEF /* ACPI common table header */
44   -+#ifdef BX_QEMU
45   -+ uint32_t table_offset_entry [4]; /* Array of pointers to other */
46   -+#else
47   - uint32_t table_offset_entry [3]; /* Array of pointers to other */
48   -+#endif
49   - /* ACPI tables */
50   - };
51   -
52   -@@ -1227,6 +1231,32 @@
53   - #endif
54   - };
55   -
56   -+#ifdef BX_QEMU
57   -+/*
58   -+ * * ACPI 2.0 Generic Address Space definition.
59   -+ * */
60   -+struct acpi_20_generic_address {
61   -+ uint8_t address_space_id;
62   -+ uint8_t register_bit_width;
63   -+ uint8_t register_bit_offset;
64   -+ uint8_t reserved;
65   -+ uint64_t address;
66   -+};
67   -+
68   -+/*
69   -+ * * HPET Description Table
70   -+ * */
71   -+struct acpi_20_hpet {
72   -+ ACPI_TABLE_HEADER_DEF /* ACPI common table header */
73   -+ uint32_t timer_block_id;
74   -+ struct acpi_20_generic_address addr;
75   -+ uint8_t hpet_number;
76   -+ uint16_t min_tick;
77   -+ uint8_t page_protect;
78   -+};
79   -+#define ACPI_HPET_ADDRESS 0xFED00000UL
80   -+#endif
81   -+
82   - struct madt_io_apic
83   - {
84   - APIC_HEADER_DEF
85   -@@ -1237,6 +1267,17 @@
86   - * lines start */
87   - };
88   -
89   -+#ifdef BX_QEMU
90   -+struct madt_int_override
91   -+{
92   -+ APIC_HEADER_DEF
93   -+ uint8_t bus; /* Identifies ISA Bus */
94   -+ uint8_t source; /* Bus-relative interrupt source */
95   -+ uint32_t gsi; /* GSI that source will signal */
96   -+ uint16_t flags; /* MPS INTI flags */
97   -+};
98   -+#endif
99   -+
100   - #include "acpi-dsdt.hex"
101   -
102   - static inline uint16_t cpu_to_le16(uint16_t x)
103   -@@ -1342,6 +1383,10 @@
104   - struct facs_descriptor_rev1 *facs;
105   - struct multiple_apic_table *madt;
106   - uint8_t *dsdt, *ssdt;
107   -+#ifdef BX_QEMU
108   -+ struct acpi_20_hpet *hpet;
109   -+ uint32_t hpet_addr;
110   -+#endif
111   - uint32_t base_addr, rsdt_addr, fadt_addr, addr, facs_addr, dsdt_addr, ssdt_addr;
112   - uint32_t acpi_tables_size, madt_addr, madt_size;
113   - int i;
114   -@@ -1384,10 +1429,21 @@
115   - madt_addr = addr;
116   - madt_size = sizeof(*madt) +
117   - sizeof(struct madt_processor_apic) * smp_cpus +
118   -+#ifdef BX_QEMU
119   -+ sizeof(struct madt_io_apic) + sizeof(struct madt_int_override);
120   -+#else
121   - sizeof(struct madt_io_apic);
122   -+#endif
123   - madt = (void *)(addr);
124   - addr += madt_size;
125   -
126   -+#ifdef BX_QEMU
127   -+ addr = (addr + 7) & ~7;
128   -+ hpet_addr = addr;
129   -+ hpet = (void *)(addr);
130   -+ addr += sizeof(*hpet);
131   -+#endif
132   -+
133   - acpi_tables_size = addr - base_addr;
134   -
135   - BX_INFO("ACPI tables: RSDP addr=0x%08lx ACPI DATA addr=0x%08lx size=0x%x\n",
136   -@@ -1410,6 +1466,9 @@
137   - rsdt->table_offset_entry[0] = cpu_to_le32(fadt_addr);
138   - rsdt->table_offset_entry[1] = cpu_to_le32(madt_addr);
139   - rsdt->table_offset_entry[2] = cpu_to_le32(ssdt_addr);
140   -+#ifdef BX_QEMU
141   -+ rsdt->table_offset_entry[3] = cpu_to_le32(hpet_addr);
142   -+#endif
143   - acpi_build_table_header((struct acpi_table_header *)rsdt,
144   - "RSDT", sizeof(*rsdt), 1);
145   -
146   -@@ -1448,6 +1507,9 @@
147   - {
148   - struct madt_processor_apic *apic;
149   - struct madt_io_apic *io_apic;
150   -+#ifdef BX_QEMU
151   -+ struct madt_int_override *int_override;
152   -+#endif
153   -
154   - memset(madt, 0, madt_size);
155   - madt->local_apic_address = cpu_to_le32(0xfee00000);
156   -@@ -1467,10 +1529,34 @@
157   - io_apic->io_apic_id = smp_cpus;
158   - io_apic->address = cpu_to_le32(0xfec00000);
159   - io_apic->interrupt = cpu_to_le32(0);
160   -+#ifdef BX_QEMU
161   -+ io_apic++;
162   -+
163   -+ int_override = (void *)io_apic;
164   -+ int_override->type = APIC_XRUPT_OVERRIDE;
165   -+ int_override->length = sizeof(*int_override);
166   -+ int_override->bus = cpu_to_le32(0);
167   -+ int_override->source = cpu_to_le32(0);
168   -+ int_override->gsi = cpu_to_le32(2);
169   -+ int_override->flags = cpu_to_le32(0);
170   -+#endif
171   -
172   - acpi_build_table_header((struct acpi_table_header *)madt,
173   - "APIC", madt_size, 1);
174   - }
175   -+
176   -+#ifdef BX_QEMU
177   -+ /* HPET */
178   -+ memset(hpet, 0, sizeof(*hpet));
179   -+ /* Note timer_block_id value must be kept in sync with value advertised by
180   -+ * emulated hpet
181   -+ */
182   -+ hpet->timer_block_id = cpu_to_le32(0x8086a201);
183   -+ hpet->addr.address = cpu_to_le32(ACPI_HPET_ADDRESS);
184   -+ acpi_build_table_header((struct acpi_table_header *)hpet,
185   -+ "HPET", sizeof(*hpet), 1);
186   -+#endif
187   -+
188   - }
189   -
190   - /* SMBIOS entry point -- must be written to a 16-bit aligned address
pc-bios/bios-pq/HEAD
  View file @71ac3b0
1   -370a7e0d8419bc05192d766c11b7221e5ffc0f75
  1 +7342176bb0fa9d6cc63b37f6ac239e3f70b74219
... ...
pc-bios/bios-pq/series
  View file @71ac3b0
1 1 0001_bx-qemu.patch
2   -0002_e820-high-mem.patch
3   -0003_smp-startup-poll.patch
4   -0005_hpet.patch
... ...
pc-bios/bios.bin
View file @71ac3b0
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