gwj / at91sam9263 · Commits

Commit 71968fa65b9088fa746a5b99c093a7e835e3fade

Authored by aurel32
1 parent a9c43f8e

target-sh4: add prefi, icbi, synco 

(Vladimir Prus)

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6013 c046a42c-6fe2-441c-8c8c-71466251a162
Inline Side-by-side
Showing 2 changed files with 27 additions and 0 deletions
target-sh4/cpu.h
  View file @71968fa
@@ -89,6 +89,10 @@ typedef struct tlb_t { @@ -89,6 +89,10 @@ typedef struct tlb_t {
89 89
90 #define NB_MMU_MODES 2 90 #define NB_MMU_MODES 2
91 91
  92 +enum sh_features {
  93 + SH_FEATURE_SH4A = 1,
  94 +};
  95 +
92 typedef struct CPUSH4State { 96 typedef struct CPUSH4State {
93 int id; /* CPU model */ 97 int id; /* CPU model */
94 98
@@ -113,6 +117,9 @@ typedef struct CPUSH4State { @@ -113,6 +117,9 @@ typedef struct CPUSH4State {
113 /* float point status register */ 117 /* float point status register */
114 float_status fp_status; 118 float_status fp_status;
115 119
  120 + /* The features that we should emulate. See sh_features above. */
  121 + uint32_t features;
  122 +
116 /* Those belong to the specific unit (SH7750) but are handled here */ 123 /* Those belong to the specific unit (SH7750) but are handled here */
117 uint32_t mmucr; /* MMU control register */ 124 uint32_t mmucr; /* MMU control register */
118 uint32_t pteh; /* page table entry high register */ 125 uint32_t pteh; /* page table entry high register */
target-sh4/translate.c
  View file @71968fa
@@ -49,6 +49,7 @@ typedef struct DisasContext { @@ -49,6 +49,7 @@ typedef struct DisasContext {
49 int memidx; 49 int memidx;
50 uint32_t delayed_pc; 50 uint32_t delayed_pc;
51 int singlestep_enabled; 51 int singlestep_enabled;
  52 + uint32_t features;
52 } DisasContext; 53 } DisasContext;
53 54
54 #if defined(CONFIG_USER_ONLY) 55 #if defined(CONFIG_USER_ONLY)
@@ -206,6 +207,7 @@ typedef struct { @@ -206,6 +207,7 @@ typedef struct {
206 uint32_t pvr; 207 uint32_t pvr;
207 uint32_t prr; 208 uint32_t prr;
208 uint32_t cvr; 209 uint32_t cvr;
  210 + uint32_t features;
209 } sh4_def_t; 211 } sh4_def_t;
210 212
211 static sh4_def_t sh4_defs[] = { 213 static sh4_def_t sh4_defs[] = {
@@ -227,6 +229,7 @@ static sh4_def_t sh4_defs[] = { @@ -227,6 +229,7 @@ static sh4_def_t sh4_defs[] = {
227 .pvr = 0x10300700, 229 .pvr = 0x10300700,
228 .prr = 0x00000200, 230 .prr = 0x00000200,
229 .cvr = 0x71440211, 231 .cvr = 0x71440211,
  232 + .features = SH_FEATURE_SH4A,
230 }, 233 },
231 }; 234 };
232 235
@@ -271,6 +274,7 @@ CPUSH4State *cpu_sh4_init(const char *cpu_model) @@ -271,6 +274,7 @@ CPUSH4State *cpu_sh4_init(const char *cpu_model)
271 env = qemu_mallocz(sizeof(CPUSH4State)); 274 env = qemu_mallocz(sizeof(CPUSH4State));
272 if (!env) 275 if (!env)
273 return NULL; 276 return NULL;
  277 + env->features = def->features;
274 cpu_exec_init(env); 278 cpu_exec_init(env);
275 sh4_translate_init(); 279 sh4_translate_init();
276 env->cpu_model_str = cpu_model; 280 env->cpu_model_str = cpu_model;
@@ -1562,6 +1566,21 @@ static void _decode_opc(DisasContext * ctx) @@ -1562,6 +1566,21 @@ static void _decode_opc(DisasContext * ctx)
1562 return; 1566 return;
1563 case 0x0083: /* pref @Rn */ 1567 case 0x0083: /* pref @Rn */
1564 return; 1568 return;
  1569 + case 0x00d3: /* prefi @Rn */
  1570 + if (ctx->features & SH_FEATURE_SH4A)
  1571 + return;
  1572 + else
  1573 + break;
  1574 + case 0x00e3: /* icbi @Rn */
  1575 + if (ctx->features & SH_FEATURE_SH4A)
  1576 + return;
  1577 + else
  1578 + break;
  1579 + case 0x00ab: /* synco */
  1580 + if (ctx->features & SH_FEATURE_SH4A)
  1581 + return;
  1582 + else
  1583 + break;
1565 case 0x4024: /* rotcl Rn */ 1584 case 0x4024: /* rotcl Rn */
1566 { 1585 {
1567 TCGv tmp = tcg_temp_new(); 1586 TCGv tmp = tcg_temp_new();
@@ -1805,6 +1824,7 @@ gen_intermediate_code_internal(CPUState * env, TranslationBlock * tb, @@ -1805,6 +1824,7 @@ gen_intermediate_code_internal(CPUState * env, TranslationBlock * tb,
1805 ctx.delayed_pc = -1; /* use delayed pc from env pointer */ 1824 ctx.delayed_pc = -1; /* use delayed pc from env pointer */
1806 ctx.tb = tb; 1825 ctx.tb = tb;
1807 ctx.singlestep_enabled = env->singlestep_enabled; 1826 ctx.singlestep_enabled = env->singlestep_enabled;
  1827 + ctx.features = env->features;
1808 1828
1809 #ifdef DEBUG_DISAS 1829 #ifdef DEBUG_DISAS
1810 if (loglevel & CPU_LOG_TB_CPU) { 1830 if (loglevel & CPU_LOG_TB_CPU) {