gwj / at91sam9263 · Commits

Commit 70c0de96a3ed38d9e9a67bddea0f35a871aac095

Authored by blueswir1
1 parent 2bc1abb7

Use qemu_irqs between dma controllers and esp, lance 


git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@2873 c046a42c-6fe2-441c-8c8c-71466251a162
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Showing 5 changed files with 37 additions and 42 deletions
hw/esp.c
  View file @70c0de9
... ... @@ -51,6 +51,7 @@ do { printf("ESP: " fmt , ##args); } while (0)
51 51 typedef struct ESPState ESPState;
52 52  
53 53 struct ESPState {
  54 + qemu_irq irq;
54 55 BlockDriverState **bd;
55 56 uint8_t rregs[ESP_REGS];
56 57 uint8_t wregs[ESP_REGS];
... ... @@ -126,7 +127,7 @@ static int get_cmd(ESPState *s, uint8_t *buf)
126 127 s->rregs[4] = STAT_IN;
127 128 s->rregs[5] = INTR_DC;
128 129 s->rregs[6] = SEQ_0;
129   - espdma_raise_irq(s->dma_opaque);
  130 + qemu_irq_raise(s->irq);
130 131 return 0;
131 132 }
132 133 s->current_dev = s->scsi_dev[target];
... ... @@ -156,7 +157,7 @@ static void do_cmd(ESPState *s, uint8_t *buf)
156 157 }
157 158 s->rregs[5] = INTR_BS | INTR_FC;
158 159 s->rregs[6] = SEQ_CD;
159   - espdma_raise_irq(s->dma_opaque);
  160 + qemu_irq_raise(s->irq);
160 161 }
161 162  
162 163 static void handle_satn(ESPState *s)
... ... @@ -178,7 +179,7 @@ static void handle_satn_stop(ESPState *s)
178 179 s->rregs[4] = STAT_IN | STAT_TC | STAT_CD;
179 180 s->rregs[5] = INTR_BS | INTR_FC;
180 181 s->rregs[6] = SEQ_CD;
181   - espdma_raise_irq(s->dma_opaque);
  182 + qemu_irq_raise(s->irq);
182 183 }
183 184 }
184 185  
... ... @@ -198,7 +199,7 @@ static void write_response(ESPState *s)
198 199 s->ti_wptr = 0;
199 200 s->rregs[7] = 2;
200 201 }
201   - espdma_raise_irq(s->dma_opaque);
  202 + qemu_irq_raise(s->irq);
202 203 }
203 204  
204 205 static void esp_dma_done(ESPState *s)
... ... @@ -209,7 +210,7 @@ static void esp_dma_done(ESPState *s)
209 210 s->rregs[7] = 0;
210 211 s->rregs[0] = 0;
211 212 s->rregs[1] = 0;
212   - espdma_raise_irq(s->dma_opaque);
  213 + qemu_irq_raise(s->irq);
213 214 }
214 215  
215 216 static void esp_do_dma(ESPState *s)
... ... @@ -362,7 +363,7 @@ static uint32_t esp_mem_readb(void *opaque, target_phys_addr_t addr)
362 363 } else {
363 364 s->rregs[2] = s->ti_buf[s->ti_rptr++];
364 365 }
365   - espdma_raise_irq(s->dma_opaque);
  366 + qemu_irq_raise(s->irq);
366 367 }
367 368 if (s->ti_size == 0) {
368 369 s->ti_rptr = 0;
... ... @@ -373,7 +374,7 @@ static uint32_t esp_mem_readb(void *opaque, target_phys_addr_t addr)
373 374 // interrupt
374 375 // Clear interrupt/error status bits
375 376 s->rregs[4] &= ~(STAT_IN | STAT_GE | STAT_PE);
376   - espdma_clear_irq(s->dma_opaque);
  377 + qemu_irq_lower(s->irq);
377 378 break;
378 379 default:
379 380 break;
... ... @@ -436,7 +437,7 @@ static void esp_mem_writeb(void *opaque, target_phys_addr_t addr, uint32_t val)
436 437 DPRINTF("Bus reset (%2.2x)\n", val);
437 438 s->rregs[5] = INTR_RST;
438 439 if (!(s->wregs[8] & 0x40)) {
439   - espdma_raise_irq(s->dma_opaque);
  440 + qemu_irq_raise(s->irq);
440 441 }
441 442 break;
442 443 case 0x10:
... ... @@ -565,7 +566,7 @@ void esp_scsi_attach(void *opaque, BlockDriverState *bd, int id)
565 566 }
566 567  
567 568 void *esp_init(BlockDriverState **bd, target_phys_addr_t espaddr,
568   - void *dma_opaque)
  569 + void *dma_opaque, qemu_irq irq)
569 570 {
570 571 ESPState *s;
571 572 int esp_io_memory;
... ... @@ -575,6 +576,7 @@ void *esp_init(BlockDriverState **bd, target_phys_addr_t espaddr,
575 576 return NULL;
576 577  
577 578 s->bd = bd;
  579 + s->irq = irq;
578 580 s->dma_opaque = dma_opaque;
579 581 sparc32_dma_set_reset_data(dma_opaque, esp_reset, s);
580 582  
... ...
hw/pcnet.c
  View file @70c0de9
... ... @@ -2018,7 +2018,7 @@ static CPUWriteMemoryFunc *lance_mem_write[3] = {
2018 2018 (CPUWriteMemoryFunc *)&pcnet_ioport_writew,
2019 2019 };
2020 2020  
2021   -void *lance_init(NICInfo *nd, target_phys_addr_t leaddr, void *dma_opaque,
  2021 +void lance_init(NICInfo *nd, target_phys_addr_t leaddr, void *dma_opaque,
2022 2022 qemu_irq irq)
2023 2023 {
2024 2024 PCNetState *d;
... ... @@ -2026,7 +2026,7 @@ void *lance_init(NICInfo *nd, target_phys_addr_t leaddr, void *dma_opaque,
2026 2026  
2027 2027 d = qemu_mallocz(sizeof(PCNetState));
2028 2028 if (!d)
2029   - return NULL;
  2029 + return;
2030 2030  
2031 2031 lance_io_memory =
2032 2032 cpu_register_io_memory(0, lance_mem_read, lance_mem_write, d);
... ... @@ -2041,7 +2041,5 @@ void *lance_init(NICInfo *nd, target_phys_addr_t leaddr, void *dma_opaque,
2041 2041 d->phys_mem_write = ledma_memory_write;
2042 2042  
2043 2043 pcnet_common_init(d, nd, "lance");
2044   -
2045   - return d;
2046 2044 }
2047 2045 #endif /* TARGET_SPARC */
... ...
hw/sparc32_dma.c
  View file @70c0de9
... ... @@ -115,22 +115,18 @@ void ledma_memory_write(void *opaque, target_phys_addr_t addr,
115 115 }
116 116 }
117 117  
118   -void espdma_raise_irq(void *opaque)
  118 +static void dma_set_irq(void *opaque, int irq, int level)
119 119 {
120 120 DMAState *s = opaque;
121   -
122   - DPRINTF("Raise ESP IRQ\n");
123   - s->dmaregs[0] |= DMA_INTR;
124   - qemu_irq_raise(s->irq);
125   -}
126   -
127   -void espdma_clear_irq(void *opaque)
128   -{
129   - DMAState *s = opaque;
130   -
131   - s->dmaregs[0] &= ~DMA_INTR;
132   - DPRINTF("Lower ESP IRQ\n");
133   - qemu_irq_lower(s->irq);
  121 + if (level) {
  122 + DPRINTF("Raise ESP IRQ\n");
  123 + s->dmaregs[0] |= DMA_INTR;
  124 + qemu_irq_raise(s->irq);
  125 + } else {
  126 + s->dmaregs[0] &= ~DMA_INTR;
  127 + DPRINTF("Lower ESP IRQ\n");
  128 + qemu_irq_lower(s->irq);
  129 + }
134 130 }
135 131  
136 132 void espdma_memory_read(void *opaque, uint8_t *buf, int len)
... ... @@ -241,7 +237,8 @@ static int dma_load(QEMUFile *f, void *opaque, int version_id)
241 237 return 0;
242 238 }
243 239  
244   -void *sparc32_dma_init(target_phys_addr_t daddr, qemu_irq irq, void *iommu)
  240 +void *sparc32_dma_init(target_phys_addr_t daddr, qemu_irq parent_irq,
  241 + void *iommu, qemu_irq **dev_irq)
245 242 {
246 243 DMAState *s;
247 244 int dma_io_memory;
... ... @@ -250,7 +247,7 @@ void *sparc32_dma_init(target_phys_addr_t daddr, qemu_irq irq, void *iommu)
250 247 if (!s)
251 248 return NULL;
252 249  
253   - s->irq = irq;
  250 + s->irq = parent_irq;
254 251 s->iommu = iommu;
255 252  
256 253 dma_io_memory = cpu_register_io_memory(0, dma_mem_read, dma_mem_write, s);
... ... @@ -258,6 +255,7 @@ void *sparc32_dma_init(target_phys_addr_t daddr, qemu_irq irq, void *iommu)
258 255  
259 256 register_savevm("sparc32_dma", daddr, 2, dma_save, dma_load, s);
260 257 qemu_register_reset(dma_reset, s);
  258 + *dev_irq = qemu_allocate_irqs(dma_set_irq, s, 1);
261 259  
262 260 return s;
263 261 }
... ...
hw/sun4m.c
  View file @70c0de9
... ... @@ -262,9 +262,9 @@ static void sun4m_hw_init(const struct hwdef *hwdef, int ram_size,
262 262 {
263 263 CPUState *env, *envs[MAX_CPUS];
264 264 unsigned int i;
265   - void *iommu, *espdma, *ledma, *main_esp, *main_lance = NULL;
  265 + void *iommu, *espdma, *ledma, *main_esp;
266 266 const sparc_def_t *def;
267   - qemu_irq *slavio_irq;
  267 + qemu_irq *slavio_irq, *espdma_irq, *ledma_irq;
268 268  
269 269 /* init CPUs */
270 270 sparc_find_by_name(cpu_model, &def);
... ... @@ -296,9 +296,9 @@ static void sun4m_hw_init(const struct hwdef *hwdef, int ram_size,
296 296 slavio_intctl_set_cpu(slavio_intctl, i, envs[i]);
297 297 }
298 298 espdma = sparc32_dma_init(hwdef->dma_base, slavio_irq[hwdef->esp_irq],
299   - iommu);
  299 + iommu, &espdma_irq);
300 300 ledma = sparc32_dma_init(hwdef->dma_base + 16ULL,
301   - slavio_irq[hwdef->le_irq], iommu);
  301 + slavio_irq[hwdef->le_irq], iommu, &ledma_irq);
302 302  
303 303 if (graphic_depth != 8 && graphic_depth != 24) {
304 304 fprintf(stderr, "qemu: Unsupported depth: %d\n", graphic_depth);
... ... @@ -309,8 +309,7 @@ static void sun4m_hw_init(const struct hwdef *hwdef, int ram_size,
309 309 if (nd_table[0].vlan) {
310 310 if (nd_table[0].model == NULL
311 311 || strcmp(nd_table[0].model, "lance") == 0) {
312   - main_lance = lance_init(&nd_table[0], hwdef->le_base, ledma,
313   - slavio_irq[hwdef->le_irq]);
  312 + lance_init(&nd_table[0], hwdef->le_base, ledma, *ledma_irq);
314 313 } else {
315 314 fprintf(stderr, "qemu: Unsupported NIC: %s\n", nd_table[0].model);
316 315 exit (1);
... ... @@ -331,7 +330,7 @@ static void sun4m_hw_init(const struct hwdef *hwdef, int ram_size,
331 330 slavio_serial_init(hwdef->serial_base, slavio_irq[hwdef->ser_irq],
332 331 serial_hds[1], serial_hds[0]);
333 332 fdctrl_init(slavio_irq[hwdef->fd_irq], 0, 1, hwdef->fd_base, fd_table);
334   - main_esp = esp_init(bs_table, hwdef->esp_base, espdma);
  333 + main_esp = esp_init(bs_table, hwdef->esp_base, espdma, *espdma_irq);
335 334  
336 335 for (i = 0; i < MAX_DISKS; i++) {
337 336 if (bs_table[i]) {
... ...
... ... @@ -1046,7 +1046,7 @@ void pci_rtl8139_init(PCIBus *bus, NICInfo *nd, int devfn);
1046 1046 /* pcnet.c */
1047 1047  
1048 1048 void pci_pcnet_init(PCIBus *bus, NICInfo *nd, int devfn);
1049   -void *lance_init(NICInfo *nd, target_phys_addr_t leaddr, void *dma_opaque,
  1049 +void lance_init(NICInfo *nd, target_phys_addr_t leaddr, void *dma_opaque,
1050 1050 qemu_irq irq);
1051 1051  
1052 1052 /* vmmouse.c */
... ... @@ -1263,17 +1263,15 @@ void slavio_set_power_fail(void *opaque, int power_failing);
1263 1263 /* esp.c */
1264 1264 void esp_scsi_attach(void *opaque, BlockDriverState *bd, int id);
1265 1265 void *esp_init(BlockDriverState **bd, target_phys_addr_t espaddr,
1266   - void *dma_opaque);
  1266 + void *dma_opaque, qemu_irq irq);
1267 1267  
1268 1268 /* sparc32_dma.c */
1269   -void *sparc32_dma_init(target_phys_addr_t daddr, qemu_irq irq, void *iommu);
1270   -void ledma_set_irq(void *opaque, int isr);
  1269 +void *sparc32_dma_init(target_phys_addr_t daddr, qemu_irq parent_irq,
  1270 + void *iommu, qemu_irq **dev_irq);
1271 1271 void ledma_memory_read(void *opaque, target_phys_addr_t addr,
1272 1272 uint8_t *buf, int len, int do_bswap);
1273 1273 void ledma_memory_write(void *opaque, target_phys_addr_t addr,
1274 1274 uint8_t *buf, int len, int do_bswap);
1275   -void espdma_raise_irq(void *opaque);
1276   -void espdma_clear_irq(void *opaque);
1277 1275 void espdma_memory_read(void *opaque, uint8_t *buf, int len);
1278 1276 void espdma_memory_write(void *opaque, uint8_t *buf, int len);
1279 1277 void sparc32_dma_set_reset_data(void *opaque, void (*dev_reset)(void *opaque),
... ...