Commit 70a194b930797263bd6cb962d7f09596a07b4fef
1 parent
25731098
fixed invalid Linux asm/unistd.h header for PowerPC and gcc 3.3
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@367 c046a42c-6fe2-441c-8c8c-71466251a162
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linux-user/syscall.c
@@ -68,6 +68,129 @@ | @@ -68,6 +68,129 @@ | ||
68 | #define VFAT_IOCTL_READDIR_BOTH _IOR('r', 1, struct dirent [2]) | 68 | #define VFAT_IOCTL_READDIR_BOTH _IOR('r', 1, struct dirent [2]) |
69 | #define VFAT_IOCTL_READDIR_SHORT _IOR('r', 2, struct dirent [2]) | 69 | #define VFAT_IOCTL_READDIR_SHORT _IOR('r', 2, struct dirent [2]) |
70 | 70 | ||
71 | + | ||
72 | +#if defined(__powerpc__) | ||
73 | +#undef __syscall_nr | ||
74 | +#undef __sc_loadargs_0 | ||
75 | +#undef __sc_loadargs_1 | ||
76 | +#undef __sc_loadargs_2 | ||
77 | +#undef __sc_loadargs_3 | ||
78 | +#undef __sc_loadargs_4 | ||
79 | +#undef __sc_loadargs_5 | ||
80 | +#undef __sc_asm_input_0 | ||
81 | +#undef __sc_asm_input_1 | ||
82 | +#undef __sc_asm_input_2 | ||
83 | +#undef __sc_asm_input_3 | ||
84 | +#undef __sc_asm_input_4 | ||
85 | +#undef __sc_asm_input_5 | ||
86 | +#undef _syscall0 | ||
87 | +#undef _syscall1 | ||
88 | +#undef _syscall2 | ||
89 | +#undef _syscall3 | ||
90 | +#undef _syscall4 | ||
91 | +#undef _syscall5 | ||
92 | + | ||
93 | +/* need to redefine syscalls as Linux kernel defines are incorrect for | ||
94 | + the clobber list */ | ||
95 | +/* On powerpc a system call basically clobbers the same registers like a | ||
96 | + * function call, with the exception of LR (which is needed for the | ||
97 | + * "sc; bnslr" sequence) and CR (where only CR0.SO is clobbered to signal | ||
98 | + * an error return status). | ||
99 | + */ | ||
100 | + | ||
101 | +#define __syscall_nr(nr, type, name, args...) \ | ||
102 | + unsigned long __sc_ret, __sc_err; \ | ||
103 | + { \ | ||
104 | + register unsigned long __sc_0 __asm__ ("r0"); \ | ||
105 | + register unsigned long __sc_3 __asm__ ("r3"); \ | ||
106 | + register unsigned long __sc_4 __asm__ ("r4"); \ | ||
107 | + register unsigned long __sc_5 __asm__ ("r5"); \ | ||
108 | + register unsigned long __sc_6 __asm__ ("r6"); \ | ||
109 | + register unsigned long __sc_7 __asm__ ("r7"); \ | ||
110 | + \ | ||
111 | + __sc_loadargs_##nr(name, args); \ | ||
112 | + __asm__ __volatile__ \ | ||
113 | + ("sc \n\t" \ | ||
114 | + "mfcr %0 " \ | ||
115 | + : "=&r" (__sc_0), \ | ||
116 | + "=&r" (__sc_3), "=&r" (__sc_4), \ | ||
117 | + "=&r" (__sc_5), "=&r" (__sc_6), \ | ||
118 | + "=&r" (__sc_7) \ | ||
119 | + : __sc_asm_input_##nr \ | ||
120 | + : "cr0", "ctr", "memory", \ | ||
121 | + "r8", "r9", "r10","r11", "r12"); \ | ||
122 | + __sc_ret = __sc_3; \ | ||
123 | + __sc_err = __sc_0; \ | ||
124 | + } \ | ||
125 | + if (__sc_err & 0x10000000) \ | ||
126 | + { \ | ||
127 | + errno = __sc_ret; \ | ||
128 | + __sc_ret = -1; \ | ||
129 | + } \ | ||
130 | + return (type) __sc_ret | ||
131 | + | ||
132 | +#define __sc_loadargs_0(name, dummy...) \ | ||
133 | + __sc_0 = __NR_##name | ||
134 | +#define __sc_loadargs_1(name, arg1) \ | ||
135 | + __sc_loadargs_0(name); \ | ||
136 | + __sc_3 = (unsigned long) (arg1) | ||
137 | +#define __sc_loadargs_2(name, arg1, arg2) \ | ||
138 | + __sc_loadargs_1(name, arg1); \ | ||
139 | + __sc_4 = (unsigned long) (arg2) | ||
140 | +#define __sc_loadargs_3(name, arg1, arg2, arg3) \ | ||
141 | + __sc_loadargs_2(name, arg1, arg2); \ | ||
142 | + __sc_5 = (unsigned long) (arg3) | ||
143 | +#define __sc_loadargs_4(name, arg1, arg2, arg3, arg4) \ | ||
144 | + __sc_loadargs_3(name, arg1, arg2, arg3); \ | ||
145 | + __sc_6 = (unsigned long) (arg4) | ||
146 | +#define __sc_loadargs_5(name, arg1, arg2, arg3, arg4, arg5) \ | ||
147 | + __sc_loadargs_4(name, arg1, arg2, arg3, arg4); \ | ||
148 | + __sc_7 = (unsigned long) (arg5) | ||
149 | + | ||
150 | +#define __sc_asm_input_0 "0" (__sc_0) | ||
151 | +#define __sc_asm_input_1 __sc_asm_input_0, "1" (__sc_3) | ||
152 | +#define __sc_asm_input_2 __sc_asm_input_1, "2" (__sc_4) | ||
153 | +#define __sc_asm_input_3 __sc_asm_input_2, "3" (__sc_5) | ||
154 | +#define __sc_asm_input_4 __sc_asm_input_3, "4" (__sc_6) | ||
155 | +#define __sc_asm_input_5 __sc_asm_input_4, "5" (__sc_7) | ||
156 | + | ||
157 | +#define _syscall0(type,name) \ | ||
158 | +type name(void) \ | ||
159 | +{ \ | ||
160 | + __syscall_nr(0, type, name); \ | ||
161 | +} | ||
162 | + | ||
163 | +#define _syscall1(type,name,type1,arg1) \ | ||
164 | +type name(type1 arg1) \ | ||
165 | +{ \ | ||
166 | + __syscall_nr(1, type, name, arg1); \ | ||
167 | +} | ||
168 | + | ||
169 | +#define _syscall2(type,name,type1,arg1,type2,arg2) \ | ||
170 | +type name(type1 arg1, type2 arg2) \ | ||
171 | +{ \ | ||
172 | + __syscall_nr(2, type, name, arg1, arg2); \ | ||
173 | +} | ||
174 | + | ||
175 | +#define _syscall3(type,name,type1,arg1,type2,arg2,type3,arg3) \ | ||
176 | +type name(type1 arg1, type2 arg2, type3 arg3) \ | ||
177 | +{ \ | ||
178 | + __syscall_nr(3, type, name, arg1, arg2, arg3); \ | ||
179 | +} | ||
180 | + | ||
181 | +#define _syscall4(type,name,type1,arg1,type2,arg2,type3,arg3,type4,arg4) \ | ||
182 | +type name(type1 arg1, type2 arg2, type3 arg3, type4 arg4) \ | ||
183 | +{ \ | ||
184 | + __syscall_nr(4, type, name, arg1, arg2, arg3, arg4); \ | ||
185 | +} | ||
186 | + | ||
187 | +#define _syscall5(type,name,type1,arg1,type2,arg2,type3,arg3,type4,arg4,type5,arg5) \ | ||
188 | +type name(type1 arg1, type2 arg2, type3 arg3, type4 arg4, type5 arg5) \ | ||
189 | +{ \ | ||
190 | + __syscall_nr(5, type, name, arg1, arg2, arg3, arg4, arg5); \ | ||
191 | +} | ||
192 | +#endif | ||
193 | + | ||
71 | #define __NR_sys_uname __NR_uname | 194 | #define __NR_sys_uname __NR_uname |
72 | #define __NR_sys_getcwd1 __NR_getcwd | 195 | #define __NR_sys_getcwd1 __NR_getcwd |
73 | #define __NR_sys_statfs __NR_statfs | 196 | #define __NR_sys_statfs __NR_statfs |