gwj / at91sam9263 · Commits

Commit 70976a7926b42d87e0c575412b85a8f5c1e48fad

Authored by aurel32
1 parent e60f469c

Fix off-by-one errors for Altivec and SPE registers 

Altivec and SPE both have 34 registers in their register sets, not 35
with a missing register 32.

GDB would ask for register 32 of the Altivec (resp. SPE) registers and
the code would claim it had zero width.  The QEMU GDB stub code would
then return an E14 to GDB, which would complain about not being sure
whether p packets were supported or not.

Signed-off-by: Nathan Froyd <froydnj@codesourcery.com>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6769 c046a42c-6fe2-441c-8c8c-71466251a162
Inline Side-by-side
Showing 1 changed file with 8 additions and 8 deletions
target-ppc/translate_init.c
  View file @70976a7
@@ -9379,11 +9379,11 @@ static int gdb_get_avr_reg(CPUState *env, uint8_t *mem_buf, int n) @@ -9379,11 +9379,11 @@ static int gdb_get_avr_reg(CPUState *env, uint8_t *mem_buf, int n)
9379 #endif 9379 #endif
9380 return 16; 9380 return 16;
9381 } 9381 }
9382 - if (n == 33) { 9382 + if (n == 32) {
9383 stl_p(mem_buf, env->vscr); 9383 stl_p(mem_buf, env->vscr);
9384 return 4; 9384 return 4;
9385 } 9385 }
9386 - if (n == 34) { 9386 + if (n == 33) {
9387 stl_p(mem_buf, (uint32_t)env->spr[SPR_VRSAVE]); 9387 stl_p(mem_buf, (uint32_t)env->spr[SPR_VRSAVE]);
9388 return 4; 9388 return 4;
9389 } 9389 }
@@ -9402,11 +9402,11 @@ static int gdb_set_avr_reg(CPUState *env, uint8_t *mem_buf, int n) @@ -9402,11 +9402,11 @@ static int gdb_set_avr_reg(CPUState *env, uint8_t *mem_buf, int n)
9402 #endif 9402 #endif
9403 return 16; 9403 return 16;
9404 } 9404 }
9405 - if (n == 33) { 9405 + if (n == 32) {
9406 env->vscr = ldl_p(mem_buf); 9406 env->vscr = ldl_p(mem_buf);
9407 return 4; 9407 return 4;
9408 } 9408 }
9409 - if (n == 34) { 9409 + if (n == 33) {
9410 env->spr[SPR_VRSAVE] = (target_ulong)ldl_p(mem_buf); 9410 env->spr[SPR_VRSAVE] = (target_ulong)ldl_p(mem_buf);
9411 return 4; 9411 return 4;
9412 } 9412 }
@@ -9423,11 +9423,11 @@ static int gdb_get_spe_reg(CPUState *env, uint8_t *mem_buf, int n) @@ -9423,11 +9423,11 @@ static int gdb_get_spe_reg(CPUState *env, uint8_t *mem_buf, int n)
9423 #endif 9423 #endif
9424 return 4; 9424 return 4;
9425 } 9425 }
9426 - if (n == 33) { 9426 + if (n == 32) {
9427 stq_p(mem_buf, env->spe_acc); 9427 stq_p(mem_buf, env->spe_acc);
9428 return 8; 9428 return 8;
9429 } 9429 }
9430 - if (n == 34) { 9430 + if (n == 33) {
9431 /* SPEFSCR not implemented */ 9431 /* SPEFSCR not implemented */
9432 memset(mem_buf, 0, 4); 9432 memset(mem_buf, 0, 4);
9433 return 4; 9433 return 4;
@@ -9447,11 +9447,11 @@ static int gdb_set_spe_reg(CPUState *env, uint8_t *mem_buf, int n) @@ -9447,11 +9447,11 @@ static int gdb_set_spe_reg(CPUState *env, uint8_t *mem_buf, int n)
9447 #endif 9447 #endif
9448 return 4; 9448 return 4;
9449 } 9449 }
9450 - if (n == 33) { 9450 + if (n == 32) {
9451 env->spe_acc = ldq_p(mem_buf); 9451 env->spe_acc = ldq_p(mem_buf);
9452 return 8; 9452 return 8;
9453 } 9453 }
9454 - if (n == 34) { 9454 + if (n == 33) {
9455 /* SPEFSCR not implemented */ 9455 /* SPEFSCR not implemented */
9456 return 4; 9456 return 4;
9457 } 9457 }