Commit 6f6260c7d68fffe349fbe134b1ef2cebb5bb5a1e

Authored by Blue Swirl
1 parent 430c7ec7

Sparc32: convert sparc32_dma to qdev

Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
hw/sparc32_dma.c
@@ -21,9 +21,11 @@ @@ -21,9 +21,11 @@
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
22 * THE SOFTWARE. 22 * THE SOFTWARE.
23 */ 23 */
  24 +
24 #include "hw.h" 25 #include "hw.h"
25 #include "sparc32_dma.h" 26 #include "sparc32_dma.h"
26 #include "sun4m.h" 27 #include "sun4m.h"
  28 +#include "sysbus.h"
27 29
28 /* debug DMA */ 30 /* debug DMA */
29 //#define DEBUG_DMA 31 //#define DEBUG_DMA
@@ -60,6 +62,7 @@ @@ -60,6 +62,7 @@
60 typedef struct DMAState DMAState; 62 typedef struct DMAState DMAState;
61 63
62 struct DMAState { 64 struct DMAState {
  65 + SysBusDevice busdev;
63 uint32_t dmaregs[DMA_REGS]; 66 uint32_t dmaregs[DMA_REGS];
64 qemu_irq irq; 67 qemu_irq irq;
65 void *iommu; 68 void *iommu;
@@ -242,24 +245,56 @@ static int dma_load(QEMUFile *f, void *opaque, int version_id) @@ -242,24 +245,56 @@ static int dma_load(QEMUFile *f, void *opaque, int version_id)
242 } 245 }
243 246
244 void *sparc32_dma_init(target_phys_addr_t daddr, qemu_irq parent_irq, 247 void *sparc32_dma_init(target_phys_addr_t daddr, qemu_irq parent_irq,
245 - void *iommu, qemu_irq **dev_irq, qemu_irq **reset) 248 + void *iommu, qemu_irq *dev_irq, qemu_irq **reset)
246 { 249 {
247 - DMAState *s;  
248 - int dma_io_memory; 250 + DeviceState *dev;
  251 + SysBusDevice *s;
  252 + DMAState *d;
  253 +
  254 + dev = qdev_create(NULL, "sparc32_dma");
  255 + qdev_set_prop_ptr(dev, "iommu_opaque", iommu);
  256 + qdev_init(dev);
  257 + s = sysbus_from_qdev(dev);
  258 + sysbus_connect_irq(s, 0, parent_irq);
  259 + *dev_irq = qdev_get_gpio_in(dev, 0);
  260 + sysbus_mmio_map(s, 0, daddr);
  261 +
  262 + d = FROM_SYSBUS(DMAState, s);
  263 + *reset = &d->dev_reset;
  264 +
  265 + return d;
  266 +}
249 267
250 - s = qemu_mallocz(sizeof(DMAState)); 268 +static void sparc32_dma_init1(SysBusDevice *dev)
  269 +{
  270 + DMAState *s = FROM_SYSBUS(DMAState, dev);
  271 + int dma_io_memory;
251 272
252 - s->irq = parent_irq;  
253 - s->iommu = iommu; 273 + sysbus_init_irq(dev, &s->irq);
  274 + s->iommu = qdev_get_prop_ptr(&dev->qdev, "iommu_opaque");
254 275
255 dma_io_memory = cpu_register_io_memory(dma_mem_read, dma_mem_write, s); 276 dma_io_memory = cpu_register_io_memory(dma_mem_read, dma_mem_write, s);
256 - cpu_register_physical_memory(daddr, DMA_SIZE, dma_io_memory); 277 + sysbus_init_mmio(dev, DMA_SIZE, dma_io_memory);
257 278
258 - register_savevm("sparc32_dma", daddr, 2, dma_save, dma_load, s); 279 + register_savevm("sparc32_dma", -1, 2, dma_save, dma_load, s);
259 qemu_register_reset(dma_reset, s); 280 qemu_register_reset(dma_reset, s);
260 - *dev_irq = qemu_allocate_irqs(dma_set_irq, s, 1);  
261 281
262 - *reset = &s->dev_reset; 282 + qdev_init_gpio_in(&dev->qdev, dma_set_irq, 1);
  283 +}
263 284
264 - return s; 285 +static SysBusDeviceInfo sparc32_dma_info = {
  286 + .init = sparc32_dma_init1,
  287 + .qdev.name = "sparc32_dma",
  288 + .qdev.size = sizeof(DMAState),
  289 + .qdev.props = (DevicePropList[]) {
  290 + {.name = "iommu_opaque", .type = PROP_TYPE_PTR},
  291 + {.name = NULL}
  292 + }
  293 +};
  294 +
  295 +static void sparc32_dma_register_devices(void)
  296 +{
  297 + sysbus_register_withprop(&sparc32_dma_info);
265 } 298 }
  299 +
  300 +device_init(sparc32_dma_register_devices)
hw/sparc32_dma.h
@@ -3,7 +3,7 @@ @@ -3,7 +3,7 @@
3 3
4 /* sparc32_dma.c */ 4 /* sparc32_dma.c */
5 void *sparc32_dma_init(target_phys_addr_t daddr, qemu_irq parent_irq, 5 void *sparc32_dma_init(target_phys_addr_t daddr, qemu_irq parent_irq,
6 - void *iommu, qemu_irq **dev_irq, qemu_irq **reset); 6 + void *iommu, qemu_irq *dev_irq, qemu_irq **reset);
7 void ledma_memory_read(void *opaque, target_phys_addr_t addr, 7 void ledma_memory_read(void *opaque, target_phys_addr_t addr,
8 uint8_t *buf, int len, int do_bswap); 8 uint8_t *buf, int len, int do_bswap);
9 void ledma_memory_write(void *opaque, target_phys_addr_t addr, 9 void ledma_memory_write(void *opaque, target_phys_addr_t addr,
hw/sun4m.c
@@ -433,7 +433,7 @@ static void sun4m_hw_init(const struct sun4m_hwdef *hwdef, ram_addr_t RAM_size, @@ -433,7 +433,7 @@ static void sun4m_hw_init(const struct sun4m_hwdef *hwdef, ram_addr_t RAM_size,
433 unsigned int i; 433 unsigned int i;
434 void *iommu, *espdma, *ledma, *nvram; 434 void *iommu, *espdma, *ledma, *nvram;
435 qemu_irq *cpu_irqs[MAX_CPUS], *slavio_irq, *slavio_cpu_irq, 435 qemu_irq *cpu_irqs[MAX_CPUS], *slavio_irq, *slavio_cpu_irq,
436 - *espdma_irq, *ledma_irq; 436 + espdma_irq, ledma_irq;
437 qemu_irq *esp_reset, *le_reset; 437 qemu_irq *esp_reset, *le_reset;
438 qemu_irq fdc_tc; 438 qemu_irq fdc_tc;
439 qemu_irq *cpu_halt; 439 qemu_irq *cpu_halt;
@@ -537,7 +537,7 @@ static void sun4m_hw_init(const struct sun4m_hwdef *hwdef, ram_addr_t RAM_size, @@ -537,7 +537,7 @@ static void sun4m_hw_init(const struct sun4m_hwdef *hwdef, ram_addr_t RAM_size,
537 tcx_init(hwdef->tcx_base, hwdef->vram_size, graphic_width, graphic_height, 537 tcx_init(hwdef->tcx_base, hwdef->vram_size, graphic_width, graphic_height,
538 graphic_depth); 538 graphic_depth);
539 539
540 - lance_init(&nd_table[0], hwdef->le_base, ledma, *ledma_irq, le_reset); 540 + lance_init(&nd_table[0], hwdef->le_base, ledma, ledma_irq, le_reset);
541 541
542 nvram = m48t59_init(slavio_irq[0], hwdef->nvram_base, 0, 542 nvram = m48t59_init(slavio_irq[0], hwdef->nvram_base, 0,
543 hwdef->nvram_size, 8); 543 hwdef->nvram_size, 8);
@@ -578,7 +578,7 @@ static void sun4m_hw_init(const struct sun4m_hwdef *hwdef, ram_addr_t RAM_size, @@ -578,7 +578,7 @@ static void sun4m_hw_init(const struct sun4m_hwdef *hwdef, ram_addr_t RAM_size,
578 578
579 esp_init(hwdef->esp_base, 2, 579 esp_init(hwdef->esp_base, 2,
580 espdma_memory_read, espdma_memory_write, 580 espdma_memory_read, espdma_memory_write,
581 - espdma, *espdma_irq, esp_reset); 581 + espdma, espdma_irq, esp_reset);
582 582
583 if (hwdef->cs_base) 583 if (hwdef->cs_base)
584 cs_init(hwdef->cs_base, hwdef->cs_irq, slavio_intctl); 584 cs_init(hwdef->cs_base, hwdef->cs_irq, slavio_intctl);
@@ -1223,7 +1223,7 @@ static void sun4d_hw_init(const struct sun4d_hwdef *hwdef, ram_addr_t RAM_size, @@ -1223,7 +1223,7 @@ static void sun4d_hw_init(const struct sun4d_hwdef *hwdef, ram_addr_t RAM_size,
1223 unsigned int i; 1223 unsigned int i;
1224 void *iounits[MAX_IOUNITS], *espdma, *ledma, *nvram, *sbi; 1224 void *iounits[MAX_IOUNITS], *espdma, *ledma, *nvram, *sbi;
1225 qemu_irq *cpu_irqs[MAX_CPUS], *sbi_irq, *sbi_cpu_irq, 1225 qemu_irq *cpu_irqs[MAX_CPUS], *sbi_irq, *sbi_cpu_irq,
1226 - *espdma_irq, *ledma_irq; 1226 + espdma_irq, ledma_irq;
1227 qemu_irq *esp_reset, *le_reset; 1227 qemu_irq *esp_reset, *le_reset;
1228 ram_addr_t ram_offset, prom_offset; 1228 ram_addr_t ram_offset, prom_offset;
1229 unsigned long kernel_size; 1229 unsigned long kernel_size;
@@ -1315,7 +1315,7 @@ static void sun4d_hw_init(const struct sun4d_hwdef *hwdef, ram_addr_t RAM_size, @@ -1315,7 +1315,7 @@ static void sun4d_hw_init(const struct sun4d_hwdef *hwdef, ram_addr_t RAM_size,
1315 tcx_init(hwdef->tcx_base, hwdef->vram_size, graphic_width, graphic_height, 1315 tcx_init(hwdef->tcx_base, hwdef->vram_size, graphic_width, graphic_height,
1316 graphic_depth); 1316 graphic_depth);
1317 1317
1318 - lance_init(&nd_table[0], hwdef->le_base, ledma, *ledma_irq, le_reset); 1318 + lance_init(&nd_table[0], hwdef->le_base, ledma, ledma_irq, le_reset);
1319 1319
1320 nvram = m48t59_init(sbi_irq[0], hwdef->nvram_base, 0, 1320 nvram = m48t59_init(sbi_irq[0], hwdef->nvram_base, 0,
1321 hwdef->nvram_size, 8); 1321 hwdef->nvram_size, 8);
@@ -1337,7 +1337,7 @@ static void sun4d_hw_init(const struct sun4d_hwdef *hwdef, ram_addr_t RAM_size, @@ -1337,7 +1337,7 @@ static void sun4d_hw_init(const struct sun4d_hwdef *hwdef, ram_addr_t RAM_size,
1337 1337
1338 esp_init(hwdef->esp_base, 2, 1338 esp_init(hwdef->esp_base, 2,
1339 espdma_memory_read, espdma_memory_write, 1339 espdma_memory_read, espdma_memory_write,
1340 - espdma, *espdma_irq, esp_reset); 1340 + espdma, espdma_irq, esp_reset);
1341 1341
1342 kernel_size = sun4m_load_kernel(kernel_filename, initrd_filename, 1342 kernel_size = sun4m_load_kernel(kernel_filename, initrd_filename,
1343 RAM_size); 1343 RAM_size);
@@ -1443,7 +1443,7 @@ static void sun4c_hw_init(const struct sun4c_hwdef *hwdef, ram_addr_t RAM_size, @@ -1443,7 +1443,7 @@ static void sun4c_hw_init(const struct sun4c_hwdef *hwdef, ram_addr_t RAM_size,
1443 { 1443 {
1444 CPUState *env; 1444 CPUState *env;
1445 void *iommu, *espdma, *ledma, *nvram; 1445 void *iommu, *espdma, *ledma, *nvram;
1446 - qemu_irq *cpu_irqs, *slavio_irq, *espdma_irq, *ledma_irq; 1446 + qemu_irq *cpu_irqs, *slavio_irq, espdma_irq, ledma_irq;
1447 qemu_irq *esp_reset, *le_reset; 1447 qemu_irq *esp_reset, *le_reset;
1448 qemu_irq fdc_tc; 1448 qemu_irq fdc_tc;
1449 ram_addr_t ram_offset, prom_offset; 1449 ram_addr_t ram_offset, prom_offset;
@@ -1528,7 +1528,7 @@ static void sun4c_hw_init(const struct sun4c_hwdef *hwdef, ram_addr_t RAM_size, @@ -1528,7 +1528,7 @@ static void sun4c_hw_init(const struct sun4c_hwdef *hwdef, ram_addr_t RAM_size,
1528 tcx_init(hwdef->tcx_base, hwdef->vram_size, graphic_width, graphic_height, 1528 tcx_init(hwdef->tcx_base, hwdef->vram_size, graphic_width, graphic_height,
1529 graphic_depth); 1529 graphic_depth);
1530 1530
1531 - lance_init(&nd_table[0], hwdef->le_base, ledma, *ledma_irq, le_reset); 1531 + lance_init(&nd_table[0], hwdef->le_base, ledma, ledma_irq, le_reset);
1532 1532
1533 nvram = m48t59_init(slavio_irq[0], hwdef->nvram_base, 0, 1533 nvram = m48t59_init(slavio_irq[0], hwdef->nvram_base, 0,
1534 hwdef->nvram_size, 2); 1534 hwdef->nvram_size, 2);
@@ -1562,7 +1562,7 @@ static void sun4c_hw_init(const struct sun4c_hwdef *hwdef, ram_addr_t RAM_size, @@ -1562,7 +1562,7 @@ static void sun4c_hw_init(const struct sun4c_hwdef *hwdef, ram_addr_t RAM_size,
1562 1562
1563 esp_init(hwdef->esp_base, 2, 1563 esp_init(hwdef->esp_base, 2,
1564 espdma_memory_read, espdma_memory_write, 1564 espdma_memory_read, espdma_memory_write,
1565 - espdma, *espdma_irq, esp_reset); 1565 + espdma, espdma_irq, esp_reset);
1566 1566
1567 kernel_size = sun4m_load_kernel(kernel_filename, initrd_filename, 1567 kernel_size = sun4m_load_kernel(kernel_filename, initrd_filename,
1568 RAM_size); 1568 RAM_size);