Commit 6f551262b35aa5f95ef9a8a9e5b3e43871be66a6
1 parent
e0b8d65a
Use memory based registers in functions containing brconds
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4311 c046a42c-6fe2-441c-8c8c-71466251a162
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1 changed file
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57 additions
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44 deletions
target-sparc/translate.c
... | ... | @@ -459,22 +459,24 @@ static inline void gen_tag_tv(TCGv src1, TCGv src2) |
459 | 459 | static inline void gen_op_add_cc(TCGv dst, TCGv src1, TCGv src2) |
460 | 460 | { |
461 | 461 | tcg_gen_mov_tl(cpu_cc_src, src1); |
462 | + tcg_gen_mov_tl(cpu_cc_src2, src2); | |
462 | 463 | tcg_gen_add_tl(dst, src1, src2); |
463 | 464 | gen_cc_clear_icc(); |
464 | 465 | gen_cc_NZ_icc(dst); |
465 | 466 | gen_cc_C_add_icc(dst, cpu_cc_src); |
466 | - gen_cc_V_add_icc(dst, cpu_cc_src, src2); | |
467 | + gen_cc_V_add_icc(dst, cpu_cc_src, cpu_cc_src2); | |
467 | 468 | #ifdef TARGET_SPARC64 |
468 | 469 | gen_cc_clear_xcc(); |
469 | 470 | gen_cc_NZ_xcc(dst); |
470 | 471 | gen_cc_C_add_xcc(dst, cpu_cc_src); |
471 | - gen_cc_V_add_xcc(dst, cpu_cc_src, src2); | |
472 | + gen_cc_V_add_xcc(dst, cpu_cc_src, cpu_cc_src2); | |
472 | 473 | #endif |
473 | 474 | } |
474 | 475 | |
475 | 476 | static inline void gen_op_addx_cc(TCGv dst, TCGv src1, TCGv src2) |
476 | 477 | { |
477 | 478 | tcg_gen_mov_tl(cpu_cc_src, src1); |
479 | + tcg_gen_mov_tl(cpu_cc_src2, src2); | |
478 | 480 | gen_mov_reg_C(cpu_tmp0, cpu_psr); |
479 | 481 | tcg_gen_add_tl(dst, src1, cpu_tmp0); |
480 | 482 | gen_cc_clear_icc(); |
... | ... | @@ -483,40 +485,42 @@ static inline void gen_op_addx_cc(TCGv dst, TCGv src1, TCGv src2) |
483 | 485 | gen_cc_clear_xcc(); |
484 | 486 | gen_cc_C_add_xcc(dst, cpu_cc_src); |
485 | 487 | #endif |
486 | - tcg_gen_add_tl(dst, dst, src2); | |
488 | + tcg_gen_add_tl(dst, dst, cpu_cc_src2); | |
487 | 489 | gen_cc_NZ_icc(dst); |
488 | 490 | gen_cc_C_add_icc(dst, cpu_cc_src); |
489 | - gen_cc_V_add_icc(dst, cpu_cc_src, src2); | |
491 | + gen_cc_V_add_icc(dst, cpu_cc_src, cpu_cc_src2); | |
490 | 492 | #ifdef TARGET_SPARC64 |
491 | 493 | gen_cc_NZ_xcc(dst); |
492 | 494 | gen_cc_C_add_xcc(dst, cpu_cc_src); |
493 | - gen_cc_V_add_xcc(dst, cpu_cc_src, src2); | |
495 | + gen_cc_V_add_xcc(dst, cpu_cc_src, cpu_cc_src2); | |
494 | 496 | #endif |
495 | 497 | } |
496 | 498 | |
497 | 499 | static inline void gen_op_tadd_cc(TCGv dst, TCGv src1, TCGv src2) |
498 | 500 | { |
499 | 501 | tcg_gen_mov_tl(cpu_cc_src, src1); |
502 | + tcg_gen_mov_tl(cpu_cc_src2, src2); | |
500 | 503 | tcg_gen_add_tl(dst, src1, src2); |
501 | 504 | gen_cc_clear_icc(); |
502 | 505 | gen_cc_NZ_icc(dst); |
503 | 506 | gen_cc_C_add_icc(dst, cpu_cc_src); |
504 | - gen_cc_V_add_icc(dst, cpu_cc_src, src2); | |
505 | - gen_cc_V_tag(cpu_cc_src, src2); | |
507 | + gen_cc_V_add_icc(dst, cpu_cc_src, cpu_cc_src2); | |
508 | + gen_cc_V_tag(cpu_cc_src, cpu_cc_src2); | |
506 | 509 | #ifdef TARGET_SPARC64 |
507 | 510 | gen_cc_clear_xcc(); |
508 | 511 | gen_cc_NZ_xcc(dst); |
509 | 512 | gen_cc_C_add_xcc(dst, cpu_cc_src); |
510 | - gen_cc_V_add_xcc(dst, cpu_cc_src, src2); | |
513 | + gen_cc_V_add_xcc(dst, cpu_cc_src, cpu_cc_src2); | |
511 | 514 | #endif |
512 | 515 | } |
513 | 516 | |
514 | 517 | static inline void gen_op_tadd_ccTV(TCGv dst, TCGv src1, TCGv src2) |
515 | 518 | { |
516 | - gen_tag_tv(src1, src2); | |
517 | 519 | tcg_gen_mov_tl(cpu_cc_src, src1); |
520 | + tcg_gen_mov_tl(cpu_cc_src2, src2); | |
521 | + gen_tag_tv(cpu_cc_src, cpu_cc_src2); | |
518 | 522 | tcg_gen_add_tl(dst, src1, src2); |
519 | - gen_add_tv(dst, cpu_cc_src, src2); | |
523 | + gen_add_tv(dst, cpu_cc_src, cpu_cc_src2); | |
520 | 524 | gen_cc_clear_icc(); |
521 | 525 | gen_cc_NZ_icc(dst); |
522 | 526 | gen_cc_C_add_icc(dst, cpu_cc_src); |
... | ... | @@ -524,7 +528,7 @@ static inline void gen_op_tadd_ccTV(TCGv dst, TCGv src1, TCGv src2) |
524 | 528 | gen_cc_clear_xcc(); |
525 | 529 | gen_cc_NZ_xcc(dst); |
526 | 530 | gen_cc_C_add_xcc(dst, cpu_cc_src); |
527 | - gen_cc_V_add_xcc(dst, cpu_cc_src, src2); | |
531 | + gen_cc_V_add_xcc(dst, cpu_cc_src, cpu_cc_src2); | |
528 | 532 | #endif |
529 | 533 | } |
530 | 534 | |
... | ... | @@ -619,22 +623,24 @@ static inline void gen_sub_tv(TCGv dst, TCGv src1, TCGv src2) |
619 | 623 | static inline void gen_op_sub_cc(TCGv dst, TCGv src1, TCGv src2) |
620 | 624 | { |
621 | 625 | tcg_gen_mov_tl(cpu_cc_src, src1); |
626 | + tcg_gen_mov_tl(cpu_cc_src2, src2); | |
622 | 627 | tcg_gen_sub_tl(dst, src1, src2); |
623 | 628 | gen_cc_clear_icc(); |
624 | 629 | gen_cc_NZ_icc(dst); |
625 | - gen_cc_C_sub_icc(cpu_cc_src, src2); | |
626 | - gen_cc_V_sub_icc(dst, cpu_cc_src, src2); | |
630 | + gen_cc_C_sub_icc(cpu_cc_src, cpu_cc_src2); | |
631 | + gen_cc_V_sub_icc(dst, cpu_cc_src, cpu_cc_src2); | |
627 | 632 | #ifdef TARGET_SPARC64 |
628 | 633 | gen_cc_clear_xcc(); |
629 | 634 | gen_cc_NZ_xcc(dst); |
630 | - gen_cc_C_sub_xcc(cpu_cc_src, src2); | |
631 | - gen_cc_V_sub_xcc(dst, cpu_cc_src, src2); | |
635 | + gen_cc_C_sub_xcc(cpu_cc_src, cpu_cc_src2); | |
636 | + gen_cc_V_sub_xcc(dst, cpu_cc_src, cpu_cc_src2); | |
632 | 637 | #endif |
633 | 638 | } |
634 | 639 | |
635 | 640 | static inline void gen_op_subx_cc(TCGv dst, TCGv src1, TCGv src2) |
636 | 641 | { |
637 | 642 | tcg_gen_mov_tl(cpu_cc_src, src1); |
643 | + tcg_gen_mov_tl(cpu_cc_src2, src2); | |
638 | 644 | gen_mov_reg_C(cpu_tmp0, cpu_psr); |
639 | 645 | tcg_gen_sub_tl(dst, src1, cpu_tmp0); |
640 | 646 | gen_cc_clear_icc(); |
... | ... | @@ -643,58 +649,59 @@ static inline void gen_op_subx_cc(TCGv dst, TCGv src1, TCGv src2) |
643 | 649 | gen_cc_clear_xcc(); |
644 | 650 | gen_cc_C_sub_xcc(dst, cpu_cc_src); |
645 | 651 | #endif |
646 | - tcg_gen_sub_tl(dst, dst, src2); | |
652 | + tcg_gen_sub_tl(dst, dst, cpu_cc_src2); | |
647 | 653 | gen_cc_NZ_icc(dst); |
648 | 654 | gen_cc_C_sub_icc(dst, cpu_cc_src); |
649 | - gen_cc_V_sub_icc(dst, cpu_cc_src, src2); | |
655 | + gen_cc_V_sub_icc(dst, cpu_cc_src, cpu_cc_src2); | |
650 | 656 | #ifdef TARGET_SPARC64 |
651 | 657 | gen_cc_NZ_xcc(dst); |
652 | 658 | gen_cc_C_sub_xcc(dst, cpu_cc_src); |
653 | - gen_cc_V_sub_xcc(dst, cpu_cc_src, src2); | |
659 | + gen_cc_V_sub_xcc(dst, cpu_cc_src, cpu_cc_src2); | |
654 | 660 | #endif |
655 | 661 | } |
656 | 662 | |
657 | 663 | static inline void gen_op_tsub_cc(TCGv dst, TCGv src1, TCGv src2) |
658 | 664 | { |
659 | 665 | tcg_gen_mov_tl(cpu_cc_src, src1); |
666 | + tcg_gen_mov_tl(cpu_cc_src2, src2); | |
660 | 667 | tcg_gen_sub_tl(dst, src1, src2); |
661 | 668 | gen_cc_clear_icc(); |
662 | 669 | gen_cc_NZ_icc(dst); |
663 | - gen_cc_C_sub_icc(cpu_cc_src, src2); | |
664 | - gen_cc_V_sub_icc(dst, cpu_cc_src, src2); | |
665 | - gen_cc_V_tag(cpu_cc_src, src2); | |
670 | + gen_cc_C_sub_icc(cpu_cc_src, cpu_cc_src2); | |
671 | + gen_cc_V_sub_icc(dst, cpu_cc_src, cpu_cc_src2); | |
672 | + gen_cc_V_tag(cpu_cc_src, cpu_cc_src2); | |
666 | 673 | #ifdef TARGET_SPARC64 |
667 | 674 | gen_cc_clear_xcc(); |
668 | 675 | gen_cc_NZ_xcc(dst); |
669 | - gen_cc_C_sub_xcc(cpu_cc_src, src2); | |
670 | - gen_cc_V_sub_xcc(dst, cpu_cc_src, src2); | |
676 | + gen_cc_C_sub_xcc(cpu_cc_src, cpu_cc_src2); | |
677 | + gen_cc_V_sub_xcc(dst, cpu_cc_src, cpu_cc_src2); | |
671 | 678 | #endif |
672 | 679 | } |
673 | 680 | |
674 | 681 | static inline void gen_op_tsub_ccTV(TCGv dst, TCGv src1, TCGv src2) |
675 | 682 | { |
676 | - gen_tag_tv(src1, src2); | |
677 | 683 | tcg_gen_mov_tl(cpu_cc_src, src1); |
684 | + tcg_gen_mov_tl(cpu_cc_src2, src2); | |
685 | + gen_tag_tv(cpu_cc_src, cpu_cc_src2); | |
678 | 686 | tcg_gen_sub_tl(dst, src1, src2); |
679 | - gen_sub_tv(dst, cpu_cc_src, src2); | |
687 | + gen_sub_tv(dst, cpu_cc_src, cpu_cc_src2); | |
680 | 688 | gen_cc_clear_icc(); |
681 | 689 | gen_cc_NZ_icc(dst); |
682 | - gen_cc_C_sub_icc(cpu_cc_src, src2); | |
690 | + gen_cc_C_sub_icc(cpu_cc_src, cpu_cc_src2); | |
683 | 691 | #ifdef TARGET_SPARC64 |
684 | 692 | gen_cc_clear_xcc(); |
685 | 693 | gen_cc_NZ_xcc(dst); |
686 | - gen_cc_C_sub_xcc(cpu_cc_src, src2); | |
687 | - gen_cc_V_sub_xcc(dst, cpu_cc_src, src2); | |
694 | + gen_cc_C_sub_xcc(cpu_cc_src, cpu_cc_src2); | |
695 | + gen_cc_V_sub_xcc(dst, cpu_cc_src, cpu_cc_src2); | |
688 | 696 | #endif |
689 | 697 | } |
690 | 698 | |
691 | 699 | static inline void gen_op_mulscc(TCGv dst, TCGv src1, TCGv src2) |
692 | 700 | { |
693 | 701 | TCGv r_temp, r_temp2; |
694 | - int l1, l2; | |
702 | + int l1; | |
695 | 703 | |
696 | 704 | l1 = gen_new_label(); |
697 | - l2 = gen_new_label(); | |
698 | 705 | r_temp = tcg_temp_new(TCG_TYPE_TL); |
699 | 706 | r_temp2 = tcg_temp_new(TCG_TYPE_I32); |
700 | 707 | |
... | ... | @@ -702,19 +709,18 @@ static inline void gen_op_mulscc(TCGv dst, TCGv src1, TCGv src2) |
702 | 709 | if (!(env->y & 1)) |
703 | 710 | T1 = 0; |
704 | 711 | */ |
712 | + tcg_gen_mov_tl(cpu_cc_src, src1); | |
705 | 713 | tcg_gen_ld32u_tl(r_temp, cpu_env, offsetof(CPUSPARCState, y)); |
706 | 714 | tcg_gen_trunc_tl_i32(r_temp2, r_temp); |
707 | 715 | tcg_gen_andi_i32(r_temp2, r_temp2, 0x1); |
708 | - tcg_gen_brcond_i32(TCG_COND_EQ, r_temp2, tcg_const_i32(0), l1); | |
709 | 716 | tcg_gen_mov_tl(cpu_cc_src2, src2); |
710 | - tcg_gen_br(l2); | |
711 | - gen_set_label(l1); | |
717 | + tcg_gen_brcond_i32(TCG_COND_NE, r_temp2, tcg_const_i32(0), l1); | |
712 | 718 | tcg_gen_movi_tl(cpu_cc_src2, 0); |
713 | - gen_set_label(l2); | |
719 | + gen_set_label(l1); | |
714 | 720 | |
715 | 721 | // b2 = T0 & 1; |
716 | 722 | // env->y = (b2 << 31) | (env->y >> 1); |
717 | - tcg_gen_trunc_tl_i32(r_temp2, src1); | |
723 | + tcg_gen_trunc_tl_i32(r_temp2, cpu_cc_src); | |
718 | 724 | tcg_gen_andi_i32(r_temp2, r_temp2, 0x1); |
719 | 725 | tcg_gen_shli_i32(r_temp2, r_temp2, 31); |
720 | 726 | tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, y)); |
... | ... | @@ -730,7 +736,7 @@ static inline void gen_op_mulscc(TCGv dst, TCGv src1, TCGv src2) |
730 | 736 | // T0 = (b1 << 31) | (T0 >> 1); |
731 | 737 | // src1 = T0; |
732 | 738 | tcg_gen_shli_tl(cpu_tmp0, cpu_tmp0, 31); |
733 | - tcg_gen_shri_tl(cpu_cc_src, src1, 1); | |
739 | + tcg_gen_shri_tl(cpu_cc_src, cpu_cc_src, 1); | |
734 | 740 | tcg_gen_or_tl(cpu_cc_src, cpu_cc_src, cpu_tmp0); |
735 | 741 | |
736 | 742 | /* do addition and update flags */ |
... | ... | @@ -801,13 +807,15 @@ static inline void gen_op_sdivx(TCGv dst, TCGv src1, TCGv src2) |
801 | 807 | |
802 | 808 | l1 = gen_new_label(); |
803 | 809 | l2 = gen_new_label(); |
810 | + tcg_gen_mov_tl(cpu_cc_src, src1); | |
811 | + tcg_gen_mov_tl(cpu_cc_src2, src2); | |
804 | 812 | gen_trap_ifdivzero_tl(src2); |
805 | - tcg_gen_brcond_tl(TCG_COND_NE, src1, tcg_const_tl(INT64_MIN), l1); | |
806 | - tcg_gen_brcond_tl(TCG_COND_NE, src2, tcg_const_tl(-1), l1); | |
813 | + tcg_gen_brcond_tl(TCG_COND_NE, cpu_cc_src, tcg_const_tl(INT64_MIN), l1); | |
814 | + tcg_gen_brcond_tl(TCG_COND_NE, cpu_cc_src2, tcg_const_tl(-1), l1); | |
807 | 815 | tcg_gen_movi_i64(dst, INT64_MIN); |
808 | 816 | tcg_gen_br(l2); |
809 | 817 | gen_set_label(l1); |
810 | - tcg_gen_div_i64(dst, src1, src2); | |
818 | + tcg_gen_div_i64(dst, cpu_cc_src, cpu_cc_src2); | |
811 | 819 | gen_set_label(l2); |
812 | 820 | } |
813 | 821 | #endif |
... | ... | @@ -1958,7 +1966,8 @@ static void disas_sparc_insn(DisasContext * dc) |
1958 | 1966 | if (rs2 != 0) { |
1959 | 1967 | gen_movl_reg_TN(rs2, cpu_src2); |
1960 | 1968 | tcg_gen_add_tl(cpu_dst, cpu_src1, cpu_src2); |
1961 | - } | |
1969 | + } else | |
1970 | + tcg_gen_mov_tl(cpu_dst, cpu_src1); | |
1962 | 1971 | } |
1963 | 1972 | cond = GET_FIELD(insn, 3, 6); |
1964 | 1973 | if (cond == 0x8) { |
... | ... | @@ -2849,7 +2858,8 @@ static void disas_sparc_insn(DisasContext * dc) |
2849 | 2858 | if (rs2 != 0) { |
2850 | 2859 | gen_movl_reg_TN(rs2, cpu_src2); |
2851 | 2860 | tcg_gen_or_tl(cpu_dst, cpu_src1, cpu_src2); |
2852 | - } | |
2861 | + } else | |
2862 | + tcg_gen_mov_tl(cpu_dst, cpu_src1); | |
2853 | 2863 | } |
2854 | 2864 | } |
2855 | 2865 | gen_movl_TN_reg(rd, cpu_dst); |
... | ... | @@ -3885,7 +3895,8 @@ static void disas_sparc_insn(DisasContext * dc) |
3885 | 3895 | if (rs2) { |
3886 | 3896 | gen_movl_reg_TN(rs2, cpu_src2); |
3887 | 3897 | tcg_gen_add_tl(cpu_dst, cpu_src1, cpu_src2); |
3888 | - } | |
3898 | + } else | |
3899 | + tcg_gen_mov_tl(cpu_dst, cpu_src1); | |
3889 | 3900 | } |
3890 | 3901 | tcg_gen_helper_0_0(helper_restore); |
3891 | 3902 | gen_mov_pc_npc(dc, cpu_cond); |
... | ... | @@ -3904,7 +3915,8 @@ static void disas_sparc_insn(DisasContext * dc) |
3904 | 3915 | if (rs2) { |
3905 | 3916 | gen_movl_reg_TN(rs2, cpu_src2); |
3906 | 3917 | tcg_gen_add_tl(cpu_dst, cpu_src1, cpu_src2); |
3907 | - } | |
3918 | + } else | |
3919 | + tcg_gen_mov_tl(cpu_dst, cpu_src1); | |
3908 | 3920 | } |
3909 | 3921 | switch (xop) { |
3910 | 3922 | case 0x38: /* jmpl */ |
... | ... | @@ -3995,7 +4007,8 @@ static void disas_sparc_insn(DisasContext * dc) |
3995 | 4007 | if (rs2 != 0) { |
3996 | 4008 | gen_movl_reg_TN(rs2, cpu_src2); |
3997 | 4009 | tcg_gen_add_tl(cpu_addr, cpu_src1, cpu_src2); |
3998 | - } | |
4010 | + } else | |
4011 | + tcg_gen_mov_tl(cpu_addr, cpu_src1); | |
3999 | 4012 | } |
4000 | 4013 | if (xop < 4 || (xop > 7 && xop < 0x14 && xop != 0x0e) || |
4001 | 4014 | (xop > 0x17 && xop <= 0x1d ) || | ... | ... |