Commit 6ef99fc59c74a3fde6daaa005ff8a6159b720105

Authored by ths
1 parent a5d251bd

Add fpu register support to the gdb code, by Magnus Damm.


git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@2817 c046a42c-6fe2-441c-8c8c-71466251a162
Showing 1 changed file with 19 additions and 6 deletions
gdbstub.c
... ... @@ -657,6 +657,9 @@ static void cpu_gdb_write_registers(CPUState *env, uint8_t *mem_buf, int size)
657 657 }
658 658 }
659 659 #elif defined (TARGET_SH4)
  660 +
  661 +/* Hint: Use "set architecture sh4" in GDB to see fpu registers */
  662 +
660 663 static int cpu_gdb_read_registers(CPUState *env, uint8_t *mem_buf)
661 664 {
662 665 uint32_t *ptr = (uint32_t *)mem_buf;
... ... @@ -676,12 +679,14 @@ static int cpu_gdb_read_registers(CPUState *env, uint8_t *mem_buf)
676 679 SAVE (env->mach);
677 680 SAVE (env->macl);
678 681 SAVE (env->sr);
679   - SAVE (0); /* TICKS */
680   - SAVE (0); /* STALLS */
681   - SAVE (0); /* CYCLES */
682   - SAVE (0); /* INSTS */
683   - SAVE (0); /* PLR */
684   -
  682 + SAVE (env->fpul);
  683 + SAVE (env->fpscr);
  684 + for (i = 0; i < 16; i++)
  685 + SAVE(env->fregs[i + ((env->fpscr & FPSCR_FR) ? 16 : 0)]);
  686 + SAVE (env->ssr);
  687 + SAVE (env->spc);
  688 + for (i = 0; i < 8; i++) SAVE(env->gregs[i]);
  689 + for (i = 0; i < 8; i++) SAVE(env->gregs[i + 16]);
685 690 return ((uint8_t *)ptr - mem_buf);
686 691 }
687 692  
... ... @@ -704,6 +709,14 @@ static void cpu_gdb_write_registers(CPUState *env, uint8_t *mem_buf, int size)
704 709 LOAD (env->mach);
705 710 LOAD (env->macl);
706 711 LOAD (env->sr);
  712 + LOAD (env->fpul);
  713 + LOAD (env->fpscr);
  714 + for (i = 0; i < 16; i++)
  715 + LOAD(env->fregs[i + ((env->fpscr & FPSCR_FR) ? 16 : 0)]);
  716 + LOAD (env->ssr);
  717 + LOAD (env->spc);
  718 + for (i = 0; i < 8; i++) LOAD(env->gregs[i]);
  719 + for (i = 0; i < 8; i++) LOAD(env->gregs[i + 16]);
707 720 }
708 721 #else
709 722 static int cpu_gdb_read_registers(CPUState *env, uint8_t *mem_buf)
... ...