gwj / at91sam9263 · Commits

Commit 6e6b73631301d41e8b18de4d35937bc78b0117f3

Authored by blueswir1
1 parent b4e237aa

Register reset handlers 

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6136 c046a42c-6fe2-441c-8c8c-71466251a162
Inline Side-by-side
Showing 9 changed files with 159 additions and 19 deletions
hw/adb.c
  View file @6e6b736
... ... @@ -122,6 +122,8 @@ ADBDevice *adb_register_device(ADBBusState *s, int devaddr,
122 122 d->devreq = devreq;
123 123 d->devreset = devreset;
124 124 d->opaque = opaque;
  125 + qemu_register_reset(devreset, d);
  126 + d->devreset(d);
125 127 return d;
126 128 }
127 129  
... ... @@ -278,7 +280,6 @@ void adb_kbd_init(ADBBusState *bus)
278 280 s = qemu_mallocz(sizeof(KBDState));
279 281 d = adb_register_device(bus, ADB_KEYBOARD, adb_kbd_request,
280 282 adb_kbd_reset, s);
281   - adb_kbd_reset(d);
282 283 qemu_add_kbd_event_handler(adb_kbd_put_keycode, d);
283 284 }
284 285  
... ... @@ -420,6 +421,5 @@ void adb_mouse_init(ADBBusState *bus)
420 421 s = qemu_mallocz(sizeof(MouseState));
421 422 d = adb_register_device(bus, ADB_MOUSE, adb_mouse_request,
422 423 adb_mouse_reset, s);
423   - adb_mouse_reset(d);
424 424 qemu_add_mouse_event_handler(adb_mouse_event, d, 0, "QEMU ADB Mouse");
425 425 }
... ...
hw/cuda.c
  View file @6e6b736
... ... @@ -633,6 +633,33 @@ static CPUReadMemoryFunc *cuda_read[] = {
633 633 &cuda_readl,
634 634 };
635 635  
  636 +static void cuda_reset(void *opaque)
  637 +{
  638 + CUDAState *s = opaque;
  639 +
  640 + s->b = 0;
  641 + s->a = 0;
  642 + s->dirb = 0;
  643 + s->dira = 0;
  644 + s->sr = 0;
  645 + s->acr = 0;
  646 + s->pcr = 0;
  647 + s->ifr = 0;
  648 + s->ier = 0;
  649 + // s->ier = T1_INT | SR_INT;
  650 + s->anh = 0;
  651 + s->data_in_size = 0;
  652 + s->data_in_index = 0;
  653 + s->data_out_index = 0;
  654 + s->autopoll = 0;
  655 +
  656 + s->timers[0].latch = 0xffff;
  657 + set_counter(s, &s->timers[0], 0xffff);
  658 +
  659 + s->timers[1].latch = 0;
  660 + set_counter(s, &s->timers[1], 0xffff);
  661 +}
  662 +
636 663 void cuda_init (int *cuda_mem_index, qemu_irq irq)
637 664 {
638 665 CUDAState *s = &cuda_state;
... ... @@ -641,15 +668,11 @@ void cuda_init (int *cuda_mem_index, qemu_irq irq)
641 668  
642 669 s->timers[0].index = 0;
643 670 s->timers[0].timer = qemu_new_timer(vm_clock, cuda_timer1, s);
644   - s->timers[0].latch = 0xffff;
645   - set_counter(s, &s->timers[0], 0xffff);
646 671  
647 672 s->timers[1].index = 1;
648   - s->timers[1].latch = 0;
649   - // s->ier = T1_INT | SR_INT;
650   - s->ier = 0;
651   - set_counter(s, &s->timers[1], 0xffff);
652 673  
653 674 s->adb_poll_timer = qemu_new_timer(vm_clock, cuda_adb_poll, s);
654 675 *cuda_mem_index = cpu_register_io_memory(0, cuda_read, cuda_write, s);
  676 + qemu_register_reset(cuda_reset, s);
  677 + cuda_reset(s);
655 678 }
... ...
hw/grackle_pci.c
  View file @6e6b736
... ... @@ -105,6 +105,10 @@ static void pci_grackle_set_irq(qemu_irq *pic, int irq_num, int level)
105 105 qemu_set_irq(pic[irq_num + 0x15], level);
106 106 }
107 107  
  108 +static void pci_grackle_reset(void *opaque)
  109 +{
  110 +}
  111 +
108 112 PCIBus *pci_grackle_init(uint32_t base, qemu_irq *pic)
109 113 {
110 114 GrackleState *s;
... ... @@ -160,5 +164,8 @@ PCIBus *pci_grackle_init(uint32_t base, qemu_irq *pic)
160 164 d->config[0x26] = 0x00; // prefetchable_memory_limit
161 165 d->config[0x27] = 0x85;
162 166 #endif
  167 + qemu_register_reset(pci_grackle_reset, d);
  168 + pci_grackle_reset(d);
  169 +
163 170 return s->bus;
164 171 }
... ...
hw/heathrow_pic.c
  View file @6e6b736
... ... @@ -165,17 +165,33 @@ static void heathrow_pic_set_irq(void *opaque, int num, int level)
165 165 heathrow_pic_update(s);
166 166 }
167 167  
  168 +static void heathrow_pic_reset_one(HeathrowPIC *s)
  169 +{
  170 + memset(s, '\0', sizeof(HeathrowPIC));
  171 +}
  172 +
  173 +static void heathrow_pic_reset(void *opaque)
  174 +{
  175 + HeathrowPICS *s = opaque;
  176 +
  177 + heathrow_pic_reset_one(&s->pics[0]);
  178 + heathrow_pic_reset_one(&s->pics[1]);
  179 +
  180 + s->pics[0].level_triggered = 0;
  181 + s->pics[1].level_triggered = 0x1ff00000;
  182 +}
  183 +
168 184 qemu_irq *heathrow_pic_init(int *pmem_index,
169 185 int nb_cpus, qemu_irq **irqs)
170 186 {
171 187 HeathrowPICS *s;
172 188  
173 189 s = qemu_mallocz(sizeof(HeathrowPICS));
174   - s->pics[0].level_triggered = 0;
175   - s->pics[1].level_triggered = 0x1ff00000;
176 190 /* only 1 CPU */
177 191 s->irqs = irqs[0];
178 192 *pmem_index = cpu_register_io_memory(0, pic_read, pic_write, s);
179 193  
  194 + qemu_register_reset(heathrow_pic_reset, s);
  195 + heathrow_pic_reset(s);
180 196 return qemu_allocate_irqs(heathrow_pic_set_irq, s, 64);
181 197 }
... ...
hw/ide.c
  View file @6e6b736
... ... @@ -3084,6 +3084,15 @@ static void cmd646_set_irq(void *opaque, int channel, int level)
3084 3084 cmd646_update_irq(d);
3085 3085 }
3086 3086  
  3087 +static void cmd646_reset(void *opaque)
  3088 +{
  3089 + PCIIDEState *d = opaque;
  3090 + unsigned int i;
  3091 +
  3092 + for (i = 0; i < 2; i++)
  3093 + ide_dma_cancel(&d->bmdma[i]);
  3094 +}
  3095 +
3087 3096 /* CMD646 PCI IDE controller */
3088 3097 void pci_cmd646_ide_init(PCIBus *bus, BlockDriverState **hd_table,
3089 3098 int secondary_ide_enabled)
... ... @@ -3135,6 +3144,9 @@ void pci_cmd646_ide_init(PCIBus *bus, BlockDriverState **hd_table,
3135 3144 irq = qemu_allocate_irqs(cmd646_set_irq, d, 2);
3136 3145 ide_init2(&d->ide_if[0], hd_table[0], hd_table[1], irq[0]);
3137 3146 ide_init2(&d->ide_if[2], hd_table[2], hd_table[3], irq[1]);
  3147 +
  3148 + qemu_register_reset(cmd646_reset, d);
  3149 + cmd646_reset(d);
3138 3150 }
3139 3151  
3140 3152 static void pci_ide_save(QEMUFile* f, void *opaque)
... ... @@ -3405,6 +3417,14 @@ static CPUReadMemoryFunc *pmac_ide_read[] = {
3405 3417 pmac_ide_readl,
3406 3418 };
3407 3419  
  3420 +static void pmac_ide_reset(void *opaque)
  3421 +{
  3422 + IDEState *s = (IDEState *)opaque;
  3423 +
  3424 + ide_reset(&s[0]);
  3425 + ide_reset(&s[1]);
  3426 +}
  3427 +
3408 3428 /* hd_table must contain 4 block drivers */
3409 3429 /* PowerMac uses memory mapped registers, not I/O. Return the memory
3410 3430 I/O index to access the ide. */
... ... @@ -3418,6 +3438,8 @@ int pmac_ide_init (BlockDriverState **hd_table, qemu_irq irq)
3418 3438  
3419 3439 pmac_ide_memory = cpu_register_io_memory(0, pmac_ide_read,
3420 3440 pmac_ide_write, &ide_if[0]);
  3441 + qemu_register_reset(pmac_ide_reset, &ide_if[0]);
  3442 + pmac_ide_reset(&ide_if[0]);
3421 3443 return pmac_ide_memory;
3422 3444 }
3423 3445  
... ...
hw/m48t59.c
  View file @6e6b736
... ... @@ -604,6 +604,8 @@ static void m48t59_reset(void *opaque)
604 604 {
605 605 m48t59_t *NVRAM = opaque;
606 606  
  607 + NVRAM->addr = 0;
  608 + NVRAM->lock = 0;
607 609 if (NVRAM->alrm_timer != NULL)
608 610 qemu_del_timer(NVRAM->alrm_timer);
609 611  
... ... @@ -630,7 +632,6 @@ m48t59_t *m48t59_init (qemu_irq IRQ, target_phys_addr_t mem_base,
630 632 s->IRQ = IRQ;
631 633 s->size = size;
632 634 s->io_base = io_base;
633   - s->addr = 0;
634 635 s->type = type;
635 636 if (io_base != 0) {
636 637 register_ioport_read(io_base, 0x04, 1, NVRAM_readb, s);
... ... @@ -644,7 +645,6 @@ m48t59_t *m48t59_init (qemu_irq IRQ, target_phys_addr_t mem_base,
644 645 s->alrm_timer = qemu_new_timer(vm_clock, &alarm_cb, s);
645 646 s->wd_timer = qemu_new_timer(vm_clock, &watchdog_cb, s);
646 647 }
647   - s->lock = 0;
648 648 qemu_get_timedate(&s->alarm, 0);
649 649  
650 650 qemu_register_reset(m48t59_reset, s);
... ...
hw/mac_dbdma.c
  View file @6e6b736
... ... @@ -88,7 +88,13 @@ static CPUReadMemoryFunc *dbdma_read[] = {
88 88 &dbdma_readl,
89 89 };
90 90  
  91 +static void dbdma_reset(void *opaque)
  92 +{
  93 +}
  94 +
91 95 void dbdma_init (int *dbdma_mem_index)
92 96 {
93 97 *dbdma_mem_index = cpu_register_io_memory(0, dbdma_read, dbdma_write, NULL);
  98 + qemu_register_reset(dbdma_reset, NULL);
  99 + dbdma_reset(NULL);
94 100 }
... ...
hw/mac_nvram.c
  View file @6e6b736
... ... @@ -104,6 +104,10 @@ static CPUReadMemoryFunc *nvram_read[] = {
104 104 &macio_nvram_readb,
105 105 };
106 106  
  107 +static void macio_nvram_reset(void *opaque)
  108 +{
  109 +}
  110 +
107 111 MacIONVRAMState *macio_nvram_init (int *mem_index, target_phys_addr_t size)
108 112 {
109 113 MacIONVRAMState *s;
... ... @@ -120,6 +124,8 @@ MacIONVRAMState *macio_nvram_init (int *mem_index, target_phys_addr_t size)
120 124  
121 125 s->mem_index = cpu_register_io_memory(0, nvram_read, nvram_write, s);
122 126 *mem_index = s->mem_index;
  127 + qemu_register_reset(macio_nvram_reset, s);
  128 + macio_nvram_reset(s);
123 129  
124 130 return s;
125 131 }
... ...
hw/vga.c
  View file @6e6b736
... ... @@ -1826,10 +1826,73 @@ static void vga_invalidate_display(void *opaque)
1826 1826 s->last_height = -1;
1827 1827 }
1828 1828  
1829   -static void vga_reset(VGAState *s)
  1829 +static void vga_reset(void *opaque)
1830 1830 {
1831   - memset(s, 0, sizeof(VGAState));
  1831 + VGAState *s = (VGAState *) opaque;
  1832 +
  1833 + s->lfb_addr = 0;
  1834 + s->lfb_end = 0;
  1835 + s->map_addr = 0;
  1836 + s->map_end = 0;
  1837 + s->lfb_vram_mapped = 0;
  1838 + s->bios_offset = 0;
  1839 + s->bios_size = 0;
  1840 + s->sr_index = 0;
  1841 + memset(s->sr, '\0', sizeof(s->sr));
  1842 + s->gr_index = 0;
  1843 + memset(s->gr, '\0', sizeof(s->gr));
  1844 + s->ar_index = 0;
  1845 + memset(s->ar, '\0', sizeof(s->ar));
  1846 + s->ar_flip_flop = 0;
  1847 + s->cr_index = 0;
  1848 + memset(s->cr, '\0', sizeof(s->cr));
  1849 + s->msr = 0;
  1850 + s->fcr = 0;
  1851 + s->st00 = 0;
  1852 + s->st01 = 0;
  1853 + s->dac_state = 0;
  1854 + s->dac_sub_index = 0;
  1855 + s->dac_read_index = 0;
  1856 + s->dac_write_index = 0;
  1857 + memset(s->dac_cache, '\0', sizeof(s->dac_cache));
  1858 + s->dac_8bit = 0;
  1859 + memset(s->palette, '\0', sizeof(s->palette));
  1860 + s->bank_offset = 0;
  1861 +#ifdef CONFIG_BOCHS_VBE
  1862 + s->vbe_index = 0;
  1863 + memset(s->vbe_regs, '\0', sizeof(s->vbe_regs));
  1864 + s->vbe_regs[VBE_DISPI_INDEX_ID] = VBE_DISPI_ID0;
  1865 + s->vbe_start_addr = 0;
  1866 + s->vbe_line_offset = 0;
  1867 + s->vbe_bank_mask = (s->vram_size >> 16) - 1;
  1868 +#endif
  1869 + memset(s->font_offsets, '\0', sizeof(s->font_offsets));
1832 1870 s->graphic_mode = -1; /* force full update */
  1871 + s->shift_control = 0;
  1872 + s->double_scan = 0;
  1873 + s->line_offset = 0;
  1874 + s->line_compare = 0;
  1875 + s->start_addr = 0;
  1876 + s->plane_updated = 0;
  1877 + s->last_cw = 0;
  1878 + s->last_ch = 0;
  1879 + s->last_width = 0;
  1880 + s->last_height = 0;
  1881 + s->last_scr_width = 0;
  1882 + s->last_scr_height = 0;
  1883 + s->cursor_start = 0;
  1884 + s->cursor_end = 0;
  1885 + s->cursor_offset = 0;
  1886 + memset(s->invalidated_y_table, '\0', sizeof(s->invalidated_y_table));
  1887 + memset(s->last_palette, '\0', sizeof(s->last_palette));
  1888 + memset(s->last_ch_attr, '\0', sizeof(s->last_ch_attr));
  1889 + switch (vga_retrace_method) {
  1890 + case VGA_RETRACE_DUMB:
  1891 + break;
  1892 + case VGA_RETRACE_PRECISE:
  1893 + memset(&s->retrace_info, 0, sizeof (s->retrace_info));
  1894 + break;
  1895 + }
1833 1896 }
1834 1897  
1835 1898 #define TEXTMODE_X(x) ((x) % width)
... ... @@ -2179,8 +2242,6 @@ void vga_common_init(VGAState *s, DisplayState *ds, uint8_t *vga_ram_base,
2179 2242 expand4to8[i] = v;
2180 2243 }
2181 2244  
2182   - vga_reset(s);
2183   -
2184 2245 s->vram_ptr = vga_ram_base;
2185 2246 s->vram_offset = vga_ram_offset;
2186 2247 s->vram_size = vga_ram_size;
... ... @@ -2201,9 +2262,10 @@ void vga_common_init(VGAState *s, DisplayState *ds, uint8_t *vga_ram_base,
2201 2262 case VGA_RETRACE_PRECISE:
2202 2263 s->retrace = vga_precise_retrace;
2203 2264 s->update_retrace_info = vga_precise_update_retrace_info;
2204   - memset(&s->retrace_info, 0, sizeof (s->retrace_info));
2205 2265 break;
2206 2266 }
  2267 + qemu_register_reset(vga_reset, s);
  2268 + vga_reset(s);
2207 2269 }
2208 2270  
2209 2271 /* used by both ISA and PCI */
... ... @@ -2229,8 +2291,6 @@ void vga_init(VGAState *s)
2229 2291 s->bank_offset = 0;
2230 2292  
2231 2293 #ifdef CONFIG_BOCHS_VBE
2232   - s->vbe_regs[VBE_DISPI_INDEX_ID] = VBE_DISPI_ID0;
2233   - s->vbe_bank_mask = ((s->vram_size >> 16) - 1);
2234 2294 #if defined (TARGET_I386)
2235 2295 register_ioport_read(0x1ce, 1, 2, vbe_ioport_read_index, s);
2236 2296 register_ioport_read(0x1cf, 1, 2, vbe_ioport_read_data, s);
... ...