Commit 6dc2d0daee4ca38c81b3d755ef3efd31fcd2fda2

Authored by balrog
1 parent d5e49a81

x86 pextrw destination operand can be r64.


git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5367 c046a42c-6fe2-441c-8c8c-71466251a162
Showing 1 changed file with 2 additions and 1 deletions
target-i386/translate.c
@@ -3452,6 +3452,7 @@ static void gen_sse(DisasContext *s, int b, target_ulong pc_start, int rex_r) @@ -3452,6 +3452,7 @@ static void gen_sse(DisasContext *s, int b, target_ulong pc_start, int rex_r)
3452 case 0x1c5: 3452 case 0x1c5:
3453 if (mod != 3) 3453 if (mod != 3)
3454 goto illegal_op; 3454 goto illegal_op;
  3455 + ot = (s->dflag == 2) ? OT_QUAD : OT_LONG;
3455 val = ldub_code(s->pc++); 3456 val = ldub_code(s->pc++);
3456 if (b1) { 3457 if (b1) {
3457 val &= 7; 3458 val &= 7;
@@ -3465,7 +3466,7 @@ static void gen_sse(DisasContext *s, int b, target_ulong pc_start, int rex_r) @@ -3465,7 +3466,7 @@ static void gen_sse(DisasContext *s, int b, target_ulong pc_start, int rex_r)
3465 offsetof(CPUX86State,fpregs[rm].mmx.MMX_W(val))); 3466 offsetof(CPUX86State,fpregs[rm].mmx.MMX_W(val)));
3466 } 3467 }
3467 reg = ((modrm >> 3) & 7) | rex_r; 3468 reg = ((modrm >> 3) & 7) | rex_r;
3468 - gen_op_mov_reg_T0(OT_LONG, reg); 3469 + gen_op_mov_reg_T0(ot, reg);
3469 break; 3470 break;
3470 case 0x1d6: /* movq ea, xmm */ 3471 case 0x1d6: /* movq ea, xmm */
3471 if (mod != 3) { 3472 if (mod != 3) {