gwj / at91sam9263 · Commits

Commit 6d5f237a592706773733e71e6da81dcd625fbb24

Authored by blueswir1
1 parent bc4edd79

CPU specific boot mode (Robert Reif) 


git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3542 c046a42c-6fe2-441c-8c8c-71466251a162
Inline Side-by-side
Showing 5 changed files with 15 additions and 10 deletions
cpu-exec.c
  View file @6d5f237
... ... @@ -181,10 +181,8 @@ static inline TranslationBlock *tb_find_fast(void)
181 181 flags = (((env->pstate & PS_PEF) >> 1) | ((env->fprs & FPRS_FEF) << 2))
182 182 | (env->pstate & PS_PRIV) | ((env->lsu & (DMMU_E | IMMU_E)) >> 2);
183 183 #else
184   - // FPU enable . MMU Boot . MMU enabled . MMU no-fault . Supervisor
185   - flags = (env->psref << 4) | (((env->mmuregs[0] & MMU_BM) >> 14) << 3)
186   - | ((env->mmuregs[0] & (MMU_E | MMU_NF)) << 1)
187   - | env->psrs;
  184 + // FPU enable . Supervisor
  185 + flags = (env->psref << 4) | env->psrs;
188 186 #endif
189 187 cs_base = env->npc;
190 188 pc = env->pc;
... ...
target-sparc/cpu.h
  View file @6d5f237
... ... @@ -147,7 +147,6 @@
147 147 /* MMU */
148 148 #define MMU_E (1<<0)
149 149 #define MMU_NF (1<<1)
150   -#define MMU_BM (1<<14)
151 150  
152 151 #define PTE_ENTRYTYPE_MASK 3
153 152 #define PTE_ACCESS_MASK 0x1c
... ... @@ -200,6 +199,7 @@ typedef struct CPUSPARCState {
200 199 int interrupt_index;
201 200 int interrupt_request;
202 201 int halted;
  202 + uint32_t mmu_bm;
203 203 /* NOTE: we allow 8 more registers to handle wrapping */
204 204 target_ulong regbase[NWINDOWS * 16 + 8];
205 205  
... ...
target-sparc/helper.c
  View file @6d5f237
... ... @@ -114,7 +114,7 @@ int get_physical_address (CPUState *env, target_phys_addr_t *physical, int *prot
114 114  
115 115 if ((env->mmuregs[0] & MMU_E) == 0) { /* MMU disabled */
116 116 // Boot mode: instruction fetches are taken from PROM
117   - if (rw == 2 && (env->mmuregs[0] & MMU_BM)) {
  117 + if (rw == 2 && (env->mmuregs[0] & env->mmu_bm)) {
118 118 *physical = 0xff0000000ULL | (address & 0x3ffffULL);
119 119 *prot = PAGE_READ | PAGE_EXEC;
120 120 return 0;
... ...
target-sparc/op_helper.c
  View file @6d5f237
... ... @@ -493,8 +493,8 @@ void helper_st_asi(int asi, int size)
493 493 oldreg = env->mmuregs[reg];
494 494 switch(reg) {
495 495 case 0:
496   - env->mmuregs[reg] &= ~(MMU_E | MMU_NF | MMU_BM);
497   - env->mmuregs[reg] |= T1 & (MMU_E | MMU_NF | MMU_BM);
  496 + env->mmuregs[reg] &= ~(MMU_E | MMU_NF | env->mmu_bm);
  497 + env->mmuregs[reg] |= T1 & (MMU_E | MMU_NF | env->mmu_bm);
498 498 // Mappings generated during no-fault mode or MMU
499 499 // disabled mode are invalid in normal mode
500 500 if (oldreg != env->mmuregs[reg])
... ...
target-sparc/translate.c
  View file @6d5f237
... ... @@ -59,6 +59,7 @@ struct sparc_def_t {
59 59 target_ulong iu_version;
60 60 uint32_t fpu_version;
61 61 uint32_t mmu_version;
  62 + uint32_t mmu_bm;
62 63 };
63 64  
64 65 static uint16_t *gen_opc_ptr;
... ... @@ -3482,7 +3483,7 @@ void cpu_reset(CPUSPARCState *env)
3482 3483 #else
3483 3484 env->pc = 0;
3484 3485 env->mmuregs[0] &= ~(MMU_E | MMU_NF);
3485   - env->mmuregs[0] |= MMU_BM;
  3486 + env->mmuregs[0] |= env->mmu_bm;
3486 3487 #endif
3487 3488 env->npc = env->pc + 4;
3488 3489 #endif
... ... @@ -3496,7 +3497,6 @@ CPUSPARCState *cpu_sparc_init(void)
3496 3497 if (!env)
3497 3498 return NULL;
3498 3499 cpu_exec_init(env);
3499   - cpu_reset(env);
3500 3500 return (env);
3501 3501 }
3502 3502  
... ... @@ -3515,30 +3515,35 @@ static const sparc_def_t sparc_defs[] = {
3515 3515 .iu_version = 0x04 << 24, /* Impl 0, ver 4 */
3516 3516 .fpu_version = 4 << 17, /* FPU version 4 (Meiko) */
3517 3517 .mmu_version = 0x04 << 24, /* Impl 0, ver 4 */
  3518 + .mmu_bm = 0x00004000,
3518 3519 },
3519 3520 {
3520 3521 .name = "Fujitsu MB86907",
3521 3522 .iu_version = 0x05 << 24, /* Impl 0, ver 5 */
3522 3523 .fpu_version = 4 << 17, /* FPU version 4 (Meiko) */
3523 3524 .mmu_version = 0x05 << 24, /* Impl 0, ver 5 */
  3525 + .mmu_bm = 0x00004000,
3524 3526 },
3525 3527 {
3526 3528 .name = "TI MicroSparc I",
3527 3529 .iu_version = 0x41000000,
3528 3530 .fpu_version = 4 << 17,
3529 3531 .mmu_version = 0x41000000,
  3532 + .mmu_bm = 0x00004000,
3530 3533 },
3531 3534 {
3532 3535 .name = "TI SuperSparc II",
3533 3536 .iu_version = 0x40000000,
3534 3537 .fpu_version = 0 << 17,
3535 3538 .mmu_version = 0x04000000,
  3539 + .mmu_bm = 0x00002000,
3536 3540 },
3537 3541 {
3538 3542 .name = "Ross RT620",
3539 3543 .iu_version = 0x1e000000,
3540 3544 .fpu_version = 1 << 17,
3541 3545 .mmu_version = 0x17000000,
  3546 + .mmu_bm = 0x00004000,
3542 3547 },
3543 3548 #endif
3544 3549 };
... ... @@ -3579,9 +3584,11 @@ int cpu_sparc_register (CPUSPARCState *env, const sparc_def_t *def, unsigned int
3579 3584 env->version = def->iu_version;
3580 3585 env->fsr = def->fpu_version;
3581 3586 #if !defined(TARGET_SPARC64)
  3587 + env->mmu_bm = def->mmu_bm;
3582 3588 env->mmuregs[0] |= def->mmu_version;
3583 3589 env->mxccregs[7] = ((cpu + 8) & 0xf) << 24;
3584 3590 #endif
  3591 + cpu_reset(env);
3585 3592 return 0;
3586 3593 }
3587 3594  
... ...