Commit 6d1f1778319aa03e57f80dd1aed88f80abb9b03b
1 parent
d66846a1
Fix memory allocation on mainstone2 and convert to qemu_ram_alloc.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3889 c046a42c-6fe2-441c-8c8c-71466251a162
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26 additions
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32 deletions
Changelog
... | ... | @@ -19,7 +19,7 @@ |
19 | 19 | - OMAP310 MPU emulation plus Palm T|E machine (Andrzej Zaborowski) |
20 | 20 | - ARM v6, v7, NEON SIMD and SMP emulation (Paul Brook/CodeSourcery) |
21 | 21 | - Gumstix boards: connex and verdex emulation (Thorsten Zitterell) |
22 | - - Intel mainstone board emulation (Armin Kuster) | |
22 | + - Intel mainstone II board emulation (Armin Kuster) | |
23 | 23 | - VMware SVGA II graphics card support (Andrzej Zaborowski) |
24 | 24 | |
25 | 25 | version 0.9.0: | ... | ... |
hw/mainstone.c
... | ... | @@ -64,19 +64,24 @@ static void mainstone_common_init(int ram_size, int vga_ram_size, |
64 | 64 | const char *kernel_cmdline, const char *initrd_filename, |
65 | 65 | const char *cpu_model, enum mainstone_model_e model, int arm_id) |
66 | 66 | { |
67 | - uint32_t mainstone_ram = 0x04000000; | |
68 | - uint32_t mainstone_rom = 0x00800000; | |
67 | + uint32_t mainstone_ram = 0x04000000; | |
68 | + uint32_t mainstone_rom = 0x00800000; | |
69 | + uint32_t mainstone_flash = 0x02000000; | |
70 | + uint32_t sector_len = 256 * 1024; | |
71 | + target_phys_addr_t mainstone_flash_base[] = { MST_FLASH_0, MST_FLASH_1 }; | |
69 | 72 | struct pxa2xx_state_s *cpu; |
70 | 73 | qemu_irq *mst_irq; |
71 | - int index; | |
74 | + int i, index; | |
72 | 75 | |
73 | 76 | if (!cpu_model) |
74 | 77 | cpu_model = "pxa270-c5"; |
75 | 78 | |
76 | 79 | /* Setup CPU & memory */ |
77 | - if (ram_size < mainstone_ram + mainstone_rom + PXA2XX_INTERNAL_SIZE) { | |
80 | + if (ram_size < mainstone_ram + mainstone_rom + 2 * mainstone_flash + | |
81 | + PXA2XX_INTERNAL_SIZE) { | |
78 | 82 | fprintf(stderr, "This platform requires %i bytes of memory\n", |
79 | - mainstone_ram + mainstone_rom + PXA2XX_INTERNAL_SIZE); | |
83 | + mainstone_ram + mainstone_rom + 2 * mainstone_flash + | |
84 | + PXA2XX_INTERNAL_SIZE); | |
80 | 85 | exit(1); |
81 | 86 | } |
82 | 87 | |
... | ... | @@ -88,32 +93,21 @@ static void mainstone_common_init(int ram_size, int vga_ram_size, |
88 | 93 | cpu->env->regs[15] = PXA2XX_SDRAM_BASE; |
89 | 94 | |
90 | 95 | /* There are two 32MiB flash devices on the board */ |
91 | - index = drive_get_index(IF_PFLASH, 0, 0); | |
92 | - if (index == -1) { | |
93 | - fprintf(stderr, "Two flash images must be given with the " | |
94 | - "'pflash' parameter\n"); | |
95 | - exit(1); | |
96 | - } | |
97 | - if (!pflash_cfi01_register(MST_FLASH_0, | |
98 | - mainstone_ram + PXA2XX_INTERNAL_SIZE, | |
99 | - drives_table[index].bdrv, | |
100 | - 256 * 1024, 128, 4, 0, 0, 0, 0)) { | |
101 | - fprintf(stderr, "qemu: Error registering flash memory.\n"); | |
102 | - exit(1); | |
103 | - } | |
104 | - | |
105 | - index = drive_get_index(IF_PFLASH, 0, 1); | |
106 | - if (index == -1) { | |
107 | - fprintf(stderr, "Two flash images must be given with the " | |
108 | - "'pflash' parameter\n"); | |
109 | - exit(1); | |
110 | - } | |
111 | - if (!pflash_cfi01_register(MST_FLASH_1, | |
112 | - mainstone_ram + PXA2XX_INTERNAL_SIZE, | |
113 | - drives_table[index].bdrv, | |
114 | - 256 * 1024, 128, 4, 0, 0, 0, 0)) { | |
115 | - fprintf(stderr, "qemu: Error registering flash memory.\n"); | |
116 | - exit(1); | |
96 | + for (i = 0; i < 2; i ++) { | |
97 | + index = drive_get_index(IF_PFLASH, 0, i); | |
98 | + if (index == -1) { | |
99 | + fprintf(stderr, "Two flash images must be given with the " | |
100 | + "'pflash' parameter\n"); | |
101 | + exit(1); | |
102 | + } | |
103 | + | |
104 | + if (!pflash_cfi01_register(mainstone_flash_base[i], | |
105 | + qemu_ram_alloc(mainstone_flash), | |
106 | + drives_table[index].bdrv, sector_len, | |
107 | + mainstone_flash / sector_len, 4, 0, 0, 0, 0)) { | |
108 | + fprintf(stderr, "qemu: Error registering flash memory.\n"); | |
109 | + exit(1); | |
110 | + } | |
117 | 111 | } |
118 | 112 | |
119 | 113 | mst_irq = mst_irq_init(cpu, MST_FPGA_PHYS, PXA2XX_PIC_GPIO_0); | ... | ... |