gwj / at91sam9263 · Commits

Commit 6d0662746bf66fa01337a776be17ff1f3ad7d342

Authored by aurel32
1 parent 0c0ed03b

target-mips: don't map FP registers as TCG global variables 

Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6950 c046a42c-6fe2-441c-8c8c-71466251a162
Inline Side-by-side
Showing 1 changed file with 30 additions and 35 deletions
target-mips/translate.c
  View file @6d06627
... ... @@ -431,7 +431,6 @@ static TCGv cpu_gpr[32], cpu_PC;
431 431 static TCGv cpu_HI[MIPS_DSP_ACC], cpu_LO[MIPS_DSP_ACC], cpu_ACX[MIPS_DSP_ACC];
432 432 static TCGv cpu_dspctrl, btarget, bcond;
433 433 static TCGv_i32 hflags;
434   -static TCGv_i32 fpu_fpr32[32], fpu_fpr32h[32];
435 434 static TCGv_i32 fpu_fcr0, fpu_fcr31;
436 435  
437 436 #include "gen-icount.h"
... ... @@ -500,12 +499,6 @@ static const char *fregnames[] =
500 499 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
501 500 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31", };
502 501  
503   -static const char *fregnames_h[] =
504   - { "h0", "h1", "h2", "h3", "h4", "h5", "h6", "h7",
505   - "h8", "h9", "h10", "h11", "h12", "h13", "h14", "h15",
506   - "h16", "h17", "h18", "h19", "h20", "h21", "h22", "h23",
507   - "h24", "h25", "h26", "h27", "h28", "h29", "h30", "h31", };
508   -
509 502 #ifdef MIPS_DEBUG_DISAS
510 503 #define MIPS_DEBUG(fmt, args...) \
511 504 qemu_log_mask(CPU_LOG_TB_IN_ASM, \
... ... @@ -600,46 +593,56 @@ static inline void gen_store_srsgpr (int from, int to)
600 593 /* Floating point register moves. */
601 594 static inline void gen_load_fpr32 (TCGv_i32 t, int reg)
602 595 {
603   - tcg_gen_mov_i32(t, fpu_fpr32[reg]);
  596 + tcg_gen_ld_i32(t, cpu_env, offsetof(CPUState, active_fpu.fpr[reg].w[FP_ENDIAN_IDX]));
604 597 }
605 598  
606 599 static inline void gen_store_fpr32 (TCGv_i32 t, int reg)
607 600 {
608   - tcg_gen_mov_i32(fpu_fpr32[reg], t);
  601 + tcg_gen_st_i32(t, cpu_env, offsetof(CPUState, active_fpu.fpr[reg].w[FP_ENDIAN_IDX]));
  602 +}
  603 +
  604 +static inline void gen_load_fpr32h (TCGv_i32 t, int reg)
  605 +{
  606 + tcg_gen_ld_i32(t, cpu_env, offsetof(CPUState, active_fpu.fpr[reg].w[!FP_ENDIAN_IDX]));
  607 +}
  608 +
  609 +static inline void gen_store_fpr32h (TCGv_i32 t, int reg)
  610 +{
  611 + tcg_gen_st_i32(t, cpu_env, offsetof(CPUState, active_fpu.fpr[reg].w[!FP_ENDIAN_IDX]));
609 612 }
610 613  
611 614 static inline void gen_load_fpr64 (DisasContext *ctx, TCGv_i64 t, int reg)
612 615 {
613 616 if (ctx->hflags & MIPS_HFLAG_F64) {
614   - tcg_gen_concat_i32_i64(t, fpu_fpr32[reg], fpu_fpr32h[reg]);
  617 + tcg_gen_ld_i64(t, cpu_env, offsetof(CPUState, active_fpu.fpr[reg].d));
615 618 } else {
616   - tcg_gen_concat_i32_i64(t, fpu_fpr32[reg & ~1], fpu_fpr32[reg | 1]);
  619 + TCGv_i32 t0 = tcg_temp_new_i32();
  620 + TCGv_i32 t1 = tcg_temp_new_i32();
  621 + gen_load_fpr32(t0, reg & ~1);
  622 + gen_load_fpr32(t1, reg | 1);
  623 + tcg_gen_concat_i32_i64(t, t0, t1);
  624 + tcg_temp_free_i32(t0);
  625 + tcg_temp_free_i32(t1);
617 626 }
618 627 }
619 628  
620 629 static inline void gen_store_fpr64 (DisasContext *ctx, TCGv_i64 t, int reg)
621 630 {
622 631 if (ctx->hflags & MIPS_HFLAG_F64) {
623   - tcg_gen_trunc_i64_i32(fpu_fpr32[reg], t);
624   - tcg_gen_shri_i64(t, t, 32);
625   - tcg_gen_trunc_i64_i32(fpu_fpr32h[reg], t);
  632 + tcg_gen_st_i64(t, cpu_env, offsetof(CPUState, active_fpu.fpr[reg].d));
626 633 } else {
627   - tcg_gen_trunc_i64_i32(fpu_fpr32[reg & ~1], t);
628   - tcg_gen_shri_i64(t, t, 32);
629   - tcg_gen_trunc_i64_i32(fpu_fpr32[reg | 1], t);
  634 + TCGv_i64 t0 = tcg_temp_new_i64();
  635 + TCGv_i32 t1 = tcg_temp_new_i32();
  636 + tcg_gen_trunc_i64_i32(t1, t);
  637 + gen_store_fpr32(t1, reg & ~1);
  638 + tcg_gen_shri_i64(t0, t, 32);
  639 + tcg_gen_trunc_i64_i32(t1, t0);
  640 + gen_store_fpr32(t1, reg | 1);
  641 + tcg_temp_free_i32(t1);
  642 + tcg_temp_free_i64(t0);
630 643 }
631 644 }
632 645  
633   -static inline void gen_load_fpr32h (TCGv_i32 t, int reg)
634   -{
635   - tcg_gen_mov_i32(t, fpu_fpr32h[reg]);
636   -}
637   -
638   -static inline void gen_store_fpr32h (TCGv_i32 t, int reg)
639   -{
640   - tcg_gen_mov_i32(fpu_fpr32h[reg], t);
641   -}
642   -
643 646 static inline void get_fp_cond (TCGv_i32 t)
644 647 {
645 648 TCGv_i32 r_tmp1 = tcg_temp_new_i32();
... ... @@ -8408,14 +8411,6 @@ static void mips_tcg_init(void)
8408 8411 hflags = tcg_global_mem_new_i32(TCG_AREG0,
8409 8412 offsetof(CPUState, hflags), "hflags");
8410 8413  
8411   - for (i = 0; i < 32; i++)
8412   - fpu_fpr32[i] = tcg_global_mem_new_i32(TCG_AREG0,
8413   - offsetof(CPUState, active_fpu.fpr[i].w[FP_ENDIAN_IDX]),
8414   - fregnames[i]);
8415   - for (i = 0; i < 32; i++)
8416   - fpu_fpr32h[i] = tcg_global_mem_new_i32(TCG_AREG0,
8417   - offsetof(CPUState, active_fpu.fpr[i].w[!FP_ENDIAN_IDX]),
8418   - fregnames_h[i]);
8419 8414 fpu_fcr0 = tcg_global_mem_new_i32(TCG_AREG0,
8420 8415 offsetof(CPUState, active_fpu.fcr0),
8421 8416 "fcr0");
... ...