gwj / at91sam9263 · Commits

Commit 6c5c1e2057e558fa26c1dcde042ef1f7e35193ea

Authored by ths
1 parent 8ff9cbf7

Use temporaries instead of fixed registers for some instructions. 


git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4784 c046a42c-6fe2-441c-8c8c-71466251a162
Inline Side-by-side
Showing 3 changed files with 408 additions and 303 deletions
target-mips/helper.h
  View file @6c5c1e2
... ... @@ -152,11 +152,11 @@ DEF_HELPER(target_ulong, do_dmt, (target_ulong t0))
152 152 DEF_HELPER(target_ulong, do_emt, (target_ulong t0))
153 153 DEF_HELPER(target_ulong, do_dvpe, (target_ulong t0))
154 154 DEF_HELPER(target_ulong, do_evpe, (target_ulong t0))
155   -DEF_HELPER(target_ulong, do_fork, (target_ulong t0, target_ulong t1))
  155 +DEF_HELPER(void, do_fork, (target_ulong t0, target_ulong t1))
156 156 DEF_HELPER(target_ulong, do_yield, (target_ulong t0))
157 157  
158 158 /* CP1 functions */
159   -DEF_HELPER(target_ulong, do_cfc1, (target_ulong t0, uint32_t reg))
  159 +DEF_HELPER(target_ulong, do_cfc1, (uint32_t reg))
160 160 DEF_HELPER(void, do_ctc1, (target_ulong t0, uint32_t reg))
161 161  
162 162 DEF_HELPER(void, do_float_cvtd_s, (void))
... ... @@ -241,8 +241,8 @@ FOP_PROTO(ngt)
241 241 /* Special functions */
242 242 DEF_HELPER(target_ulong, do_di, (target_ulong t0))
243 243 DEF_HELPER(target_ulong, do_ei, (target_ulong t0))
244   -DEF_HELPER(void, do_eret, (target_ulong t0))
245   -DEF_HELPER(void, do_deret, (target_ulong t0))
  244 +DEF_HELPER(void, do_eret, (void))
  245 +DEF_HELPER(void, do_deret, (void))
246 246 DEF_HELPER(target_ulong, do_rdhwr_cpunum, (target_ulong t0))
247 247 DEF_HELPER(target_ulong, do_rdhwr_synci_step, (target_ulong t0))
248 248 DEF_HELPER(target_ulong, do_rdhwr_cc, (target_ulong t0))
... ...
target-mips/op_helper.c
  View file @6c5c1e2
... ... @@ -1438,13 +1438,11 @@ target_ulong do_evpe(target_ulong t0)
1438 1438 return t0;
1439 1439 }
1440 1440  
1441   -target_ulong do_fork(target_ulong t0, target_ulong t1)
  1441 +void do_fork(target_ulong t0, target_ulong t1)
1442 1442 {
1443 1443 // t0 = rt, t1 = rs
1444 1444 t0 = 0;
1445 1445 // TODO: store to TC register
1446   -
1447   - return t0;
1448 1446 }
1449 1447  
1450 1448 target_ulong do_yield(target_ulong t0)
... ... @@ -1684,7 +1682,7 @@ void debug_post_eret (void)
1684 1682 }
1685 1683 }
1686 1684  
1687   -void do_eret (target_ulong t0)
  1685 +void do_eret (void)
1688 1686 {
1689 1687 if (loglevel & CPU_LOG_EXEC)
1690 1688 debug_pre_eret();
... ... @@ -1701,7 +1699,7 @@ void do_eret (target_ulong t0)
1701 1699 env->CP0_LLAddr = 1;
1702 1700 }
1703 1701  
1704   -void do_deret (target_ulong t0)
  1702 +void do_deret (void)
1705 1703 {
1706 1704 if (loglevel & CPU_LOG_EXEC)
1707 1705 debug_pre_eret();
... ... @@ -1918,8 +1916,10 @@ unsigned int ieee_rm[] = {
1918 1916 #define RESTORE_ROUNDING_MODE \
1919 1917 set_float_rounding_mode(ieee_rm[env->fpu->fcr31 & 3], &env->fpu->fp_status)
1920 1918  
1921   -target_ulong do_cfc1 (target_ulong t0, uint32_t reg)
  1919 +target_ulong do_cfc1 (uint32_t reg)
1922 1920 {
  1921 + target_ulong t0;
  1922 +
1923 1923 switch (reg) {
1924 1924 case 0:
1925 1925 t0 = (int32_t)env->fpu->fcr0;
... ...
target-mips/translate.c
  View file @6c5c1e2
... ... @@ -472,6 +472,14 @@ static inline void tcg_gen_helper_0_2ii(void *func, TCGv arg1, TCGv arg2, TCGv a
472 472 tcg_temp_free(tmp2);
473 473 }
474 474  
  475 +static inline void tcg_gen_helper_1_i(void *func, TCGv ret, TCGv arg)
  476 +{
  477 + TCGv tmp = tcg_const_i32(arg);
  478 +
  479 + tcg_gen_helper_1_1(func, ret, tmp);
  480 + tcg_temp_free(tmp);
  481 +}
  482 +
475 483 static inline void tcg_gen_helper_1_1i(void *func, TCGv ret, TCGv arg1, TCGv arg2)
476 484 {
477 485 TCGv tmp = tcg_const_i32(arg2);
... ... @@ -2233,112 +2241,123 @@ static void gen_mul_vr54xx (DisasContext *ctx, uint32_t opc,
2233 2241 int rd, int rs, int rt)
2234 2242 {
2235 2243 const char *opn = "mul vr54xx";
  2244 + TCGv t0 = tcg_temp_local_new(TCG_TYPE_TL);
  2245 + TCGv t1 = tcg_temp_local_new(TCG_TYPE_TL);
2236 2246  
2237   - gen_load_gpr(cpu_T[0], rs);
2238   - gen_load_gpr(cpu_T[1], rt);
  2247 + gen_load_gpr(t0, rs);
  2248 + gen_load_gpr(t1, rt);
2239 2249  
2240 2250 switch (opc) {
2241 2251 case OPC_VR54XX_MULS:
2242   - tcg_gen_helper_1_2(do_muls, cpu_T[0], cpu_T[0], cpu_T[1]);
  2252 + tcg_gen_helper_1_2(do_muls, t0, t0, t1);
2243 2253 opn = "muls";
2244 2254 break;
2245 2255 case OPC_VR54XX_MULSU:
2246   - tcg_gen_helper_1_2(do_mulsu, cpu_T[0], cpu_T[0], cpu_T[1]);
  2256 + tcg_gen_helper_1_2(do_mulsu, t0, t0, t1);
2247 2257 opn = "mulsu";
2248 2258 break;
2249 2259 case OPC_VR54XX_MACC:
2250   - tcg_gen_helper_1_2(do_macc, cpu_T[0], cpu_T[0], cpu_T[1]);
  2260 + tcg_gen_helper_1_2(do_macc, t0, t0, t1);
2251 2261 opn = "macc";
2252 2262 break;
2253 2263 case OPC_VR54XX_MACCU:
2254   - tcg_gen_helper_1_2(do_maccu, cpu_T[0], cpu_T[0], cpu_T[1]);
  2264 + tcg_gen_helper_1_2(do_maccu, t0, t0, t1);
2255 2265 opn = "maccu";
2256 2266 break;
2257 2267 case OPC_VR54XX_MSAC:
2258   - tcg_gen_helper_1_2(do_msac, cpu_T[0], cpu_T[0], cpu_T[1]);
  2268 + tcg_gen_helper_1_2(do_msac, t0, t0, t1);
2259 2269 opn = "msac";
2260 2270 break;
2261 2271 case OPC_VR54XX_MSACU:
2262   - tcg_gen_helper_1_2(do_msacu, cpu_T[0], cpu_T[0], cpu_T[1]);
  2272 + tcg_gen_helper_1_2(do_msacu, t0, t0, t1);
2263 2273 opn = "msacu";
2264 2274 break;
2265 2275 case OPC_VR54XX_MULHI:
2266   - tcg_gen_helper_1_2(do_mulhi, cpu_T[0], cpu_T[0], cpu_T[1]);
  2276 + tcg_gen_helper_1_2(do_mulhi, t0, t0, t1);
2267 2277 opn = "mulhi";
2268 2278 break;
2269 2279 case OPC_VR54XX_MULHIU:
2270   - tcg_gen_helper_1_2(do_mulhiu, cpu_T[0], cpu_T[0], cpu_T[1]);
  2280 + tcg_gen_helper_1_2(do_mulhiu, t0, t0, t1);
2271 2281 opn = "mulhiu";
2272 2282 break;
2273 2283 case OPC_VR54XX_MULSHI:
2274   - tcg_gen_helper_1_2(do_mulshi, cpu_T[0], cpu_T[0], cpu_T[1]);
  2284 + tcg_gen_helper_1_2(do_mulshi, t0, t0, t1);
2275 2285 opn = "mulshi";
2276 2286 break;
2277 2287 case OPC_VR54XX_MULSHIU:
2278   - tcg_gen_helper_1_2(do_mulshiu, cpu_T[0], cpu_T[0], cpu_T[1]);
  2288 + tcg_gen_helper_1_2(do_mulshiu, t0, t0, t1);
2279 2289 opn = "mulshiu";
2280 2290 break;
2281 2291 case OPC_VR54XX_MACCHI:
2282   - tcg_gen_helper_1_2(do_macchi, cpu_T[0], cpu_T[0], cpu_T[1]);
  2292 + tcg_gen_helper_1_2(do_macchi, t0, t0, t1);
2283 2293 opn = "macchi";
2284 2294 break;
2285 2295 case OPC_VR54XX_MACCHIU:
2286   - tcg_gen_helper_1_2(do_macchiu, cpu_T[0], cpu_T[0], cpu_T[1]);
  2296 + tcg_gen_helper_1_2(do_macchiu, t0, t0, t1);
2287 2297 opn = "macchiu";
2288 2298 break;
2289 2299 case OPC_VR54XX_MSACHI:
2290   - tcg_gen_helper_1_2(do_msachi, cpu_T[0], cpu_T[0], cpu_T[1]);
  2300 + tcg_gen_helper_1_2(do_msachi, t0, t0, t1);
2291 2301 opn = "msachi";
2292 2302 break;
2293 2303 case OPC_VR54XX_MSACHIU:
2294   - tcg_gen_helper_1_2(do_msachiu, cpu_T[0], cpu_T[0], cpu_T[1]);
  2304 + tcg_gen_helper_1_2(do_msachiu, t0, t0, t1);
2295 2305 opn = "msachiu";
2296 2306 break;
2297 2307 default:
2298 2308 MIPS_INVAL("mul vr54xx");
2299 2309 generate_exception(ctx, EXCP_RI);
2300   - return;
  2310 + goto out;
2301 2311 }
2302   - gen_store_gpr(cpu_T[0], rd);
  2312 + gen_store_gpr(t0, rd);
2303 2313 MIPS_DEBUG("%s %s, %s, %s", opn, regnames[rd], regnames[rs], regnames[rt]);
  2314 +
  2315 + out:
  2316 + tcg_temp_free(t0);
  2317 + tcg_temp_free(t1);
2304 2318 }
2305 2319  
2306 2320 static void gen_cl (DisasContext *ctx, uint32_t opc,
2307 2321 int rd, int rs)
2308 2322 {
2309 2323 const char *opn = "CLx";
  2324 + TCGv t0 = tcg_temp_local_new(TCG_TYPE_TL);
  2325 +
2310 2326 if (rd == 0) {
2311 2327 /* Treat as NOP. */
2312 2328 MIPS_DEBUG("NOP");
2313   - return;
  2329 + goto out;
2314 2330 }
2315   - gen_load_gpr(cpu_T[0], rs);
  2331 + gen_load_gpr(t0, rs);
2316 2332 switch (opc) {
2317 2333 case OPC_CLO:
2318   - tcg_gen_helper_1_1(do_clo, cpu_T[0], cpu_T[0]);
  2334 + tcg_gen_helper_1_1(do_clo, t0, t0);
2319 2335 opn = "clo";
2320 2336 break;
2321 2337 case OPC_CLZ:
2322   - tcg_gen_helper_1_1(do_clz, cpu_T[0], cpu_T[0]);
  2338 + tcg_gen_helper_1_1(do_clz, t0, t0);
2323 2339 opn = "clz";
2324 2340 break;
2325 2341 #if defined(TARGET_MIPS64)
2326 2342 case OPC_DCLO:
2327   - tcg_gen_helper_1_1(do_dclo, cpu_T[0], cpu_T[0]);
  2343 + tcg_gen_helper_1_1(do_dclo, t0, t0);
2328 2344 opn = "dclo";
2329 2345 break;
2330 2346 case OPC_DCLZ:
2331   - tcg_gen_helper_1_1(do_dclz, cpu_T[0], cpu_T[0]);
  2347 + tcg_gen_helper_1_1(do_dclz, t0, t0);
2332 2348 opn = "dclz";
2333 2349 break;
2334 2350 #endif
2335 2351 default:
2336 2352 MIPS_INVAL(opn);
2337 2353 generate_exception(ctx, EXCP_RI);
2338   - return;
  2354 + goto out;
2339 2355 }
2340   - gen_store_gpr(cpu_T[0], rd);
  2356 + gen_store_gpr(t0, rd);
2341 2357 MIPS_DEBUG("%s %s, %s", opn, regnames[rd], regnames[rs]);
  2358 +
  2359 + out:
  2360 + tcg_temp_free(t0);
2342 2361 }
2343 2362  
2344 2363 /* Traps */
... ... @@ -2470,6 +2489,8 @@ static void gen_compute_branch (DisasContext *ctx, uint32_t opc,
2470 2489 target_ulong btarget = -1;
2471 2490 int blink = 0;
2472 2491 int bcond = 0;
  2492 + TCGv t0 = tcg_temp_local_new(TCG_TYPE_TL);
  2493 + TCGv t1 = tcg_temp_local_new(TCG_TYPE_TL);
2473 2494  
2474 2495 if (ctx->hflags & MIPS_HFLAG_BMASK) {
2475 2496 #ifdef MIPS_DEBUG_DISAS
... ... @@ -2480,7 +2501,7 @@ static void gen_compute_branch (DisasContext *ctx, uint32_t opc,
2480 2501 }
2481 2502 #endif
2482 2503 generate_exception(ctx, EXCP_RI);
2483   - return;
  2504 + goto out;
2484 2505 }
2485 2506  
2486 2507 /* Load needed operands */
... ... @@ -2491,8 +2512,8 @@ static void gen_compute_branch (DisasContext *ctx, uint32_t opc,
2491 2512 case OPC_BNEL:
2492 2513 /* Compare two registers */
2493 2514 if (rs != rt) {
2494   - gen_load_gpr(cpu_T[0], rs);
2495   - gen_load_gpr(cpu_T[1], rt);
  2515 + gen_load_gpr(t0, rs);
  2516 + gen_load_gpr(t1, rt);
2496 2517 bcond = 1;
2497 2518 }
2498 2519 btarget = ctx->pc + 4 + offset;
... ... @@ -2511,7 +2532,7 @@ static void gen_compute_branch (DisasContext *ctx, uint32_t opc,
2511 2532 case OPC_BLTZL:
2512 2533 /* Compare to zero */
2513 2534 if (rs != 0) {
2514   - gen_load_gpr(cpu_T[0], rs);
  2535 + gen_load_gpr(t0, rs);
2515 2536 bcond = 1;
2516 2537 }
2517 2538 btarget = ctx->pc + 4 + offset;
... ... @@ -2529,14 +2550,14 @@ static void gen_compute_branch (DisasContext *ctx, uint32_t opc,
2529 2550 others are reserved. */
2530 2551 MIPS_INVAL("jump hint");
2531 2552 generate_exception(ctx, EXCP_RI);
2532   - return;
  2553 + goto out;
2533 2554 }
2534 2555 gen_save_breg_target(rs);
2535 2556 break;
2536 2557 default:
2537 2558 MIPS_INVAL("branch/jump");
2538 2559 generate_exception(ctx, EXCP_RI);
2539   - return;
  2560 + goto out;
2540 2561 }
2541 2562 if (bcond == 0) {
2542 2563 /* No condition to be computed */
... ... @@ -2563,26 +2584,26 @@ static void gen_compute_branch (DisasContext *ctx, uint32_t opc,
2563 2584 case OPC_BLTZ: /* 0 < 0 */
2564 2585 /* Treat as NOP. */
2565 2586 MIPS_DEBUG("bnever (NOP)");
2566   - return;
  2587 + goto out;
2567 2588 case OPC_BLTZAL: /* 0 < 0 */
2568   - tcg_gen_movi_tl(cpu_T[0], ctx->pc + 8);
2569   - gen_store_gpr(cpu_T[0], 31);
  2589 + tcg_gen_movi_tl(t0, ctx->pc + 8);
  2590 + gen_store_gpr(t0, 31);
2570 2591 MIPS_DEBUG("bnever and link");
2571   - return;
  2592 + goto out;
2572 2593 case OPC_BLTZALL: /* 0 < 0 likely */
2573   - tcg_gen_movi_tl(cpu_T[0], ctx->pc + 8);
2574   - gen_store_gpr(cpu_T[0], 31);
  2594 + tcg_gen_movi_tl(t0, ctx->pc + 8);
  2595 + gen_store_gpr(t0, 31);
2575 2596 /* Skip the instruction in the delay slot */
2576 2597 MIPS_DEBUG("bnever, link and skip");
2577 2598 ctx->pc += 4;
2578   - return;
  2599 + goto out;
2579 2600 case OPC_BNEL: /* rx != rx likely */
2580 2601 case OPC_BGTZL: /* 0 > 0 likely */
2581 2602 case OPC_BLTZL: /* 0 < 0 likely */
2582 2603 /* Skip the instruction in the delay slot */
2583 2604 MIPS_DEBUG("bnever and skip");
2584 2605 ctx->pc += 4;
2585   - return;
  2606 + goto out;
2586 2607 case OPC_J:
2587 2608 ctx->hflags |= MIPS_HFLAG_B;
2588 2609 MIPS_DEBUG("j " TARGET_FMT_lx, btarget);
... ... @@ -2604,92 +2625,92 @@ static void gen_compute_branch (DisasContext *ctx, uint32_t opc,
2604 2625 default:
2605 2626 MIPS_INVAL("branch/jump");
2606 2627 generate_exception(ctx, EXCP_RI);
2607   - return;
  2628 + goto out;
2608 2629 }
2609 2630 } else {
2610 2631 switch (opc) {
2611 2632 case OPC_BEQ:
2612   - gen_op_eq(cpu_T[0], cpu_T[1]);
  2633 + gen_op_eq(t0, t1);
2613 2634 MIPS_DEBUG("beq %s, %s, " TARGET_FMT_lx,
2614 2635 regnames[rs], regnames[rt], btarget);
2615 2636 goto not_likely;
2616 2637 case OPC_BEQL:
2617   - gen_op_eq(cpu_T[0], cpu_T[1]);
  2638 + gen_op_eq(t0, t1);
2618 2639 MIPS_DEBUG("beql %s, %s, " TARGET_FMT_lx,
2619 2640 regnames[rs], regnames[rt], btarget);
2620 2641 goto likely;
2621 2642 case OPC_BNE:
2622   - gen_op_ne(cpu_T[0], cpu_T[1]);
  2643 + gen_op_ne(t0, t1);
2623 2644 MIPS_DEBUG("bne %s, %s, " TARGET_FMT_lx,
2624 2645 regnames[rs], regnames[rt], btarget);
2625 2646 goto not_likely;
2626 2647 case OPC_BNEL:
2627   - gen_op_ne(cpu_T[0], cpu_T[1]);
  2648 + gen_op_ne(t0, t1);
2628 2649 MIPS_DEBUG("bnel %s, %s, " TARGET_FMT_lx,
2629 2650 regnames[rs], regnames[rt], btarget);
2630 2651 goto likely;
2631 2652 case OPC_BGEZ:
2632   - gen_op_gez(cpu_T[0]);
  2653 + gen_op_gez(t0);
2633 2654 MIPS_DEBUG("bgez %s, " TARGET_FMT_lx, regnames[rs], btarget);
2634 2655 goto not_likely;
2635 2656 case OPC_BGEZL:
2636   - gen_op_gez(cpu_T[0]);
  2657 + gen_op_gez(t0);
2637 2658 MIPS_DEBUG("bgezl %s, " TARGET_FMT_lx, regnames[rs], btarget);
2638 2659 goto likely;
2639 2660 case OPC_BGEZAL:
2640   - gen_op_gez(cpu_T[0]);
  2661 + gen_op_gez(t0);
2641 2662 MIPS_DEBUG("bgezal %s, " TARGET_FMT_lx, regnames[rs], btarget);
2642 2663 blink = 31;
2643 2664 goto not_likely;
2644 2665 case OPC_BGEZALL:
2645   - gen_op_gez(cpu_T[0]);
  2666 + gen_op_gez(t0);
2646 2667 blink = 31;
2647 2668 MIPS_DEBUG("bgezall %s, " TARGET_FMT_lx, regnames[rs], btarget);
2648 2669 goto likely;
2649 2670 case OPC_BGTZ:
2650   - gen_op_gtz(cpu_T[0]);
  2671 + gen_op_gtz(t0);
2651 2672 MIPS_DEBUG("bgtz %s, " TARGET_FMT_lx, regnames[rs], btarget);
2652 2673 goto not_likely;
2653 2674 case OPC_BGTZL:
2654   - gen_op_gtz(cpu_T[0]);
  2675 + gen_op_gtz(t0);
2655 2676 MIPS_DEBUG("bgtzl %s, " TARGET_FMT_lx, regnames[rs], btarget);
2656 2677 goto likely;
2657 2678 case OPC_BLEZ:
2658   - gen_op_lez(cpu_T[0]);
  2679 + gen_op_lez(t0);
2659 2680 MIPS_DEBUG("blez %s, " TARGET_FMT_lx, regnames[rs], btarget);
2660 2681 goto not_likely;
2661 2682 case OPC_BLEZL:
2662   - gen_op_lez(cpu_T[0]);
  2683 + gen_op_lez(t0);
2663 2684 MIPS_DEBUG("blezl %s, " TARGET_FMT_lx, regnames[rs], btarget);
2664 2685 goto likely;
2665 2686 case OPC_BLTZ:
2666   - gen_op_ltz(cpu_T[0]);
  2687 + gen_op_ltz(t0);
2667 2688 MIPS_DEBUG("bltz %s, " TARGET_FMT_lx, regnames[rs], btarget);
2668 2689 goto not_likely;
2669 2690 case OPC_BLTZL:
2670   - gen_op_ltz(cpu_T[0]);
  2691 + gen_op_ltz(t0);
2671 2692 MIPS_DEBUG("bltzl %s, " TARGET_FMT_lx, regnames[rs], btarget);
2672 2693 goto likely;
2673 2694 case OPC_BLTZAL:
2674   - gen_op_ltz(cpu_T[0]);
  2695 + gen_op_ltz(t0);
2675 2696 blink = 31;
2676 2697 MIPS_DEBUG("bltzal %s, " TARGET_FMT_lx, regnames[rs], btarget);
2677 2698 not_likely:
2678 2699 ctx->hflags |= MIPS_HFLAG_BC;
2679   - tcg_gen_st_tl(cpu_T[0], cpu_env, offsetof(CPUState, bcond));
  2700 + tcg_gen_st_tl(t0, cpu_env, offsetof(CPUState, bcond));
2680 2701 break;
2681 2702 case OPC_BLTZALL:
2682   - gen_op_ltz(cpu_T[0]);
  2703 + gen_op_ltz(t0);
2683 2704 blink = 31;
2684 2705 MIPS_DEBUG("bltzall %s, " TARGET_FMT_lx, regnames[rs], btarget);
2685 2706 likely:
2686 2707 ctx->hflags |= MIPS_HFLAG_BL;
2687   - tcg_gen_st_tl(cpu_T[0], cpu_env, offsetof(CPUState, bcond));
  2708 + tcg_gen_st_tl(t0, cpu_env, offsetof(CPUState, bcond));
2688 2709 break;
2689 2710 default:
2690 2711 MIPS_INVAL("conditional branch/jump");
2691 2712 generate_exception(ctx, EXCP_RI);
2692   - return;
  2713 + goto out;
2693 2714 }
2694 2715 }
2695 2716 MIPS_DEBUG("enter ds: link %d cond %02x target " TARGET_FMT_lx,
... ... @@ -2697,72 +2718,83 @@ static void gen_compute_branch (DisasContext *ctx, uint32_t opc,
2697 2718  
2698 2719 ctx->btarget = btarget;
2699 2720 if (blink > 0) {
2700   - tcg_gen_movi_tl(cpu_T[0], ctx->pc + 8);
2701   - gen_store_gpr(cpu_T[0], blink);
  2721 + tcg_gen_movi_tl(t0, ctx->pc + 8);
  2722 + gen_store_gpr(t0, blink);
2702 2723 }
  2724 +
  2725 + out:
  2726 + tcg_temp_free(t0);
  2727 + tcg_temp_free(t1);
2703 2728 }
2704 2729  
2705 2730 /* special3 bitfield operations */
2706 2731 static void gen_bitops (DisasContext *ctx, uint32_t opc, int rt,
2707 2732 int rs, int lsb, int msb)
2708 2733 {
2709   - gen_load_gpr(cpu_T[1], rs);
  2734 + TCGv t0 = tcg_temp_local_new(TCG_TYPE_TL);
  2735 + TCGv t1 = tcg_temp_local_new(TCG_TYPE_TL);
  2736 +
  2737 + gen_load_gpr(t1, rs);
2710 2738 switch (opc) {
2711 2739 case OPC_EXT:
2712 2740 if (lsb + msb > 31)
2713 2741 goto fail;
2714   - tcg_gen_helper_1_2ii(do_ext, cpu_T[0], cpu_T[0], cpu_T[1], lsb, msb + 1);
  2742 + tcg_gen_helper_1_2ii(do_ext, t0, t0, t1, lsb, msb + 1);
2715 2743 break;
2716 2744 #if defined(TARGET_MIPS64)
2717 2745 case OPC_DEXTM:
2718 2746 if (lsb + msb > 63)
2719 2747 goto fail;
2720   - tcg_gen_helper_1_2ii(do_dext, cpu_T[0], cpu_T[0], cpu_T[1], lsb, msb + 1 + 32);
  2748 + tcg_gen_helper_1_2ii(do_dext, t0, t0, t1, lsb, msb + 1 + 32);
2721 2749 break;
2722 2750 case OPC_DEXTU:
2723 2751 if (lsb + msb > 63)
2724 2752 goto fail;
2725   - tcg_gen_helper_1_2ii(do_dext, cpu_T[0], cpu_T[0], cpu_T[1], lsb + 32, msb + 1);
  2753 + tcg_gen_helper_1_2ii(do_dext, t0, t0, t1, lsb + 32, msb + 1);
2726 2754 break;
2727 2755 case OPC_DEXT:
2728 2756 if (lsb + msb > 63)
2729 2757 goto fail;
2730   - tcg_gen_helper_1_2ii(do_dext, cpu_T[0], cpu_T[0], cpu_T[1], lsb, msb + 1);
  2758 + tcg_gen_helper_1_2ii(do_dext, t0, t0, t1, lsb, msb + 1);
2731 2759 break;
2732 2760 #endif
2733 2761 case OPC_INS:
2734 2762 if (lsb > msb)
2735 2763 goto fail;
2736   - gen_load_gpr(cpu_T[0], rt);
2737   - tcg_gen_helper_1_2ii(do_ins, cpu_T[0], cpu_T[0], cpu_T[1], lsb, msb - lsb + 1);
  2764 + gen_load_gpr(t0, rt);
  2765 + tcg_gen_helper_1_2ii(do_ins, t0, t0, t1, lsb, msb - lsb + 1);
2738 2766 break;
2739 2767 #if defined(TARGET_MIPS64)
2740 2768 case OPC_DINSM:
2741 2769 if (lsb > msb)
2742 2770 goto fail;
2743   - gen_load_gpr(cpu_T[0], rt);
2744   - tcg_gen_helper_1_2ii(do_dins, cpu_T[0], cpu_T[0], cpu_T[1], lsb, msb - lsb + 1 + 32);
  2771 + gen_load_gpr(t0, rt);
  2772 + tcg_gen_helper_1_2ii(do_dins, t0, t0, t1, lsb, msb - lsb + 1 + 32);
2745 2773 break;
2746 2774 case OPC_DINSU:
2747 2775 if (lsb > msb)
2748 2776 goto fail;
2749   - gen_load_gpr(cpu_T[0], rt);
2750   - tcg_gen_helper_1_2ii(do_dins, cpu_T[0], cpu_T[0], cpu_T[1], lsb + 32, msb - lsb + 1);
  2777 + gen_load_gpr(t0, rt);
  2778 + tcg_gen_helper_1_2ii(do_dins, t0, t0, t1, lsb + 32, msb - lsb + 1);
2751 2779 break;
2752 2780 case OPC_DINS:
2753 2781 if (lsb > msb)
2754 2782 goto fail;
2755   - gen_load_gpr(cpu_T[0], rt);
2756   - tcg_gen_helper_1_2ii(do_dins, cpu_T[0], cpu_T[0], cpu_T[1], lsb, msb - lsb + 1);
  2783 + gen_load_gpr(t0, rt);
  2784 + tcg_gen_helper_1_2ii(do_dins, t0, t0, t1, lsb, msb - lsb + 1);
2757 2785 break;
2758 2786 #endif
2759 2787 default:
2760 2788 fail:
2761 2789 MIPS_INVAL("bitops");
2762 2790 generate_exception(ctx, EXCP_RI);
  2791 + tcg_temp_free(t0);
  2792 + tcg_temp_free(t1);
2763 2793 return;
2764 2794 }
2765   - gen_store_gpr(cpu_T[0], rt);
  2795 + gen_store_gpr(t0, rt);
  2796 + tcg_temp_free(t0);
  2797 + tcg_temp_free(t1);
2766 2798 }
2767 2799  
2768 2800 /* CP0 (MMU and control) */
... ... @@ -5134,7 +5166,7 @@ die:
5134 5166 }
5135 5167 #endif /* TARGET_MIPS64 */
5136 5168  
5137   -static void gen_mftr(CPUState *env, DisasContext *ctx, int rt,
  5169 +static void gen_mftr(CPUState *env, DisasContext *ctx, int rt, int rd,
5138 5170 int u, int sel, int h)
5139 5171 {
5140 5172 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
... ... @@ -5286,6 +5318,7 @@ static void gen_mftr(CPUState *env, DisasContext *ctx, int rt,
5286 5318 rt, u, sel, h);
5287 5319 }
5288 5320 #endif
  5321 + gen_store_gpr(cpu_T[0], rd);
5289 5322 return;
5290 5323  
5291 5324 die:
... ... @@ -5298,11 +5331,12 @@ die:
5298 5331 generate_exception(ctx, EXCP_RI);
5299 5332 }
5300 5333  
5301   -static void gen_mttr(CPUState *env, DisasContext *ctx, int rd,
  5334 +static void gen_mttr(CPUState *env, DisasContext *ctx, int rd, int rt,
5302 5335 int u, int sel, int h)
5303 5336 {
5304 5337 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
5305 5338  
  5339 + gen_load_gpr(cpu_T[0], rt);
5306 5340 if ((env->CP0_VPEConf0 & (1 << CP0VPEC0_MVP)) == 0 &&
5307 5341 ((env->CP0_TCBind[other_tc] & (0xf << CP0TCBd_CurVPE)) !=
5308 5342 (env->CP0_TCBind[env->current_tc] & (0xf << CP0TCBd_CurVPE))))
... ... @@ -5507,15 +5541,13 @@ static void gen_cp0 (CPUState *env, DisasContext *ctx, uint32_t opc, int rt, int
5507 5541 /* Treat as NOP. */
5508 5542 return;
5509 5543 }
5510   - gen_mftr(env, ctx, rt, (ctx->opcode >> 5) & 1,
  5544 + gen_mftr(env, ctx, rt, rd, (ctx->opcode >> 5) & 1,
5511 5545 ctx->opcode & 0x7, (ctx->opcode >> 4) & 1);
5512   - gen_store_gpr(cpu_T[0], rd);
5513 5546 opn = "mftr";
5514 5547 break;
5515 5548 case OPC_MTTR:
5516 5549 check_insn(env, ctx, ASE_MT);
5517   - gen_load_gpr(cpu_T[0], rt);
5518   - gen_mttr(env, ctx, rd, (ctx->opcode >> 5) & 1,
  5550 + gen_mttr(env, ctx, rd, rt, (ctx->opcode >> 5) & 1,
5519 5551 ctx->opcode & 0x7, (ctx->opcode >> 4) & 1);
5520 5552 opn = "mttr";
5521 5553 break;
... ... @@ -5547,7 +5579,7 @@ static void gen_cp0 (CPUState *env, DisasContext *ctx, uint32_t opc, int rt, int
5547 5579 opn = "eret";
5548 5580 check_insn(env, ctx, ISA_MIPS2);
5549 5581 save_cpu_state(ctx, 1);
5550   - tcg_gen_helper_0_1(do_eret, cpu_T[0]);
  5582 + tcg_gen_helper_0_0(do_eret);
5551 5583 ctx->bstate = BS_EXCP;
5552 5584 break;
5553 5585 case OPC_DERET:
... ... @@ -5558,7 +5590,7 @@ static void gen_cp0 (CPUState *env, DisasContext *ctx, uint32_t opc, int rt, int
5558 5590 generate_exception(ctx, EXCP_RI);
5559 5591 } else {
5560 5592 save_cpu_state(ctx, 1);
5561   - tcg_gen_helper_0_1(do_deret, cpu_T[0]);
  5593 + tcg_gen_helper_0_0(do_deret);
5562 5594 ctx->bstate = BS_EXCP;
5563 5595 }
5564 5596 break;
... ... @@ -5588,6 +5620,8 @@ static void gen_compute_branch1 (CPUState *env, DisasContext *ctx, uint32_t op,
5588 5620 {
5589 5621 target_ulong btarget;
5590 5622 const char *opn = "cp1 cond branch";
  5623 + TCGv t0 = tcg_temp_local_new(TCG_TYPE_TL);
  5624 + TCGv t1 = tcg_temp_local_new(TCG_TYPE_TL);
5591 5625  
5592 5626 if (cc != 0)
5593 5627 check_insn(env, ctx, ISA_MIPS4 | ISA_MIPS32);
... ... @@ -5602,16 +5636,16 @@ static void gen_compute_branch1 (CPUState *env, DisasContext *ctx, uint32_t op,
5602 5636 TCGv r_tmp1 = tcg_temp_new(TCG_TYPE_I32);
5603 5637  
5604 5638 get_fp_cond(r_tmp1);
5605   - tcg_gen_ext_i32_tl(cpu_T[0], r_tmp1);
  5639 + tcg_gen_ext_i32_tl(t0, r_tmp1);
5606 5640 tcg_temp_free(r_tmp1);
5607   - tcg_gen_not_tl(cpu_T[0], cpu_T[0]);
5608   - tcg_gen_movi_tl(cpu_T[1], 0x1 << cc);
5609   - tcg_gen_and_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
5610   - tcg_gen_brcondi_tl(TCG_COND_NE, cpu_T[0], 0, l1);
5611   - tcg_gen_movi_tl(cpu_T[0], 0);
  5641 + tcg_gen_not_tl(t0, t0);
  5642 + tcg_gen_movi_tl(t1, 0x1 << cc);
  5643 + tcg_gen_and_tl(t0, t0, t1);
  5644 + tcg_gen_brcondi_tl(TCG_COND_NE, t0, 0, l1);
  5645 + tcg_gen_movi_tl(t0, 0);
5612 5646 tcg_gen_br(l2);
5613 5647 gen_set_label(l1);
5614   - tcg_gen_movi_tl(cpu_T[0], 1);
  5648 + tcg_gen_movi_tl(t0, 1);
5615 5649 gen_set_label(l2);
5616 5650 }
5617 5651 opn = "bc1f";
... ... @@ -5623,16 +5657,16 @@ static void gen_compute_branch1 (CPUState *env, DisasContext *ctx, uint32_t op,
5623 5657 TCGv r_tmp1 = tcg_temp_new(TCG_TYPE_I32);
5624 5658  
5625 5659 get_fp_cond(r_tmp1);
5626   - tcg_gen_ext_i32_tl(cpu_T[0], r_tmp1);
  5660 + tcg_gen_ext_i32_tl(t0, r_tmp1);
5627 5661 tcg_temp_free(r_tmp1);
5628   - tcg_gen_not_tl(cpu_T[0], cpu_T[0]);
5629   - tcg_gen_movi_tl(cpu_T[1], 0x1 << cc);
5630   - tcg_gen_and_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
5631   - tcg_gen_brcondi_tl(TCG_COND_NE, cpu_T[0], 0, l1);
5632   - tcg_gen_movi_tl(cpu_T[0], 0);
  5662 + tcg_gen_not_tl(t0, t0);
  5663 + tcg_gen_movi_tl(t1, 0x1 << cc);
  5664 + tcg_gen_and_tl(t0, t0, t1);
  5665 + tcg_gen_brcondi_tl(TCG_COND_NE, t0, 0, l1);
  5666 + tcg_gen_movi_tl(t0, 0);
5633 5667 tcg_gen_br(l2);
5634 5668 gen_set_label(l1);
5635   - tcg_gen_movi_tl(cpu_T[0], 1);
  5669 + tcg_gen_movi_tl(t0, 1);
5636 5670 gen_set_label(l2);
5637 5671 }
5638 5672 opn = "bc1fl";
... ... @@ -5644,15 +5678,15 @@ static void gen_compute_branch1 (CPUState *env, DisasContext *ctx, uint32_t op,
5644 5678 TCGv r_tmp1 = tcg_temp_new(TCG_TYPE_I32);
5645 5679  
5646 5680 get_fp_cond(r_tmp1);
5647   - tcg_gen_ext_i32_tl(cpu_T[0], r_tmp1);
  5681 + tcg_gen_ext_i32_tl(t0, r_tmp1);
5648 5682 tcg_temp_free(r_tmp1);
5649   - tcg_gen_movi_tl(cpu_T[1], 0x1 << cc);
5650   - tcg_gen_and_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
5651   - tcg_gen_brcondi_tl(TCG_COND_NE, cpu_T[0], 0, l1);
5652   - tcg_gen_movi_tl(cpu_T[0], 0);
  5683 + tcg_gen_movi_tl(t1, 0x1 << cc);
  5684 + tcg_gen_and_tl(t0, t0, t1);
  5685 + tcg_gen_brcondi_tl(TCG_COND_NE, t0, 0, l1);
  5686 + tcg_gen_movi_tl(t0, 0);
5653 5687 tcg_gen_br(l2);
5654 5688 gen_set_label(l1);
5655   - tcg_gen_movi_tl(cpu_T[0], 1);
  5689 + tcg_gen_movi_tl(t0, 1);
5656 5690 gen_set_label(l2);
5657 5691 }
5658 5692 opn = "bc1t";
... ... @@ -5664,21 +5698,21 @@ static void gen_compute_branch1 (CPUState *env, DisasContext *ctx, uint32_t op,
5664 5698 TCGv r_tmp1 = tcg_temp_new(TCG_TYPE_I32);
5665 5699  
5666 5700 get_fp_cond(r_tmp1);
5667   - tcg_gen_ext_i32_tl(cpu_T[0], r_tmp1);
  5701 + tcg_gen_ext_i32_tl(t0, r_tmp1);
5668 5702 tcg_temp_free(r_tmp1);
5669   - tcg_gen_movi_tl(cpu_T[1], 0x1 << cc);
5670   - tcg_gen_and_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
5671   - tcg_gen_brcondi_tl(TCG_COND_NE, cpu_T[0], 0, l1);
5672   - tcg_gen_movi_tl(cpu_T[0], 0);
  5703 + tcg_gen_movi_tl(t1, 0x1 << cc);
  5704 + tcg_gen_and_tl(t0, t0, t1);
  5705 + tcg_gen_brcondi_tl(TCG_COND_NE, t0, 0, l1);
  5706 + tcg_gen_movi_tl(t0, 0);
5673 5707 tcg_gen_br(l2);
5674 5708 gen_set_label(l1);
5675   - tcg_gen_movi_tl(cpu_T[0], 1);
  5709 + tcg_gen_movi_tl(t0, 1);
5676 5710 gen_set_label(l2);
5677 5711 }
5678 5712 opn = "bc1tl";
5679 5713 likely:
5680 5714 ctx->hflags |= MIPS_HFLAG_BL;
5681   - tcg_gen_st_tl(cpu_T[0], cpu_env, offsetof(CPUState, bcond));
  5715 + tcg_gen_st_tl(t0, cpu_env, offsetof(CPUState, bcond));
5682 5716 break;
5683 5717 case OPC_BC1FANY2:
5684 5718 {
... ... @@ -5687,16 +5721,16 @@ static void gen_compute_branch1 (CPUState *env, DisasContext *ctx, uint32_t op,
5687 5721 TCGv r_tmp1 = tcg_temp_new(TCG_TYPE_I32);
5688 5722  
5689 5723 get_fp_cond(r_tmp1);
5690   - tcg_gen_ext_i32_tl(cpu_T[0], r_tmp1);
  5724 + tcg_gen_ext_i32_tl(t0, r_tmp1);
5691 5725 tcg_temp_free(r_tmp1);
5692   - tcg_gen_not_tl(cpu_T[0], cpu_T[0]);
5693   - tcg_gen_movi_tl(cpu_T[1], 0x3 << cc);
5694   - tcg_gen_and_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
5695   - tcg_gen_brcondi_tl(TCG_COND_NE, cpu_T[0], 0, l1);
5696   - tcg_gen_movi_tl(cpu_T[0], 0);
  5726 + tcg_gen_not_tl(t0, t0);
  5727 + tcg_gen_movi_tl(t1, 0x3 << cc);
  5728 + tcg_gen_and_tl(t0, t0, t1);
  5729 + tcg_gen_brcondi_tl(TCG_COND_NE, t0, 0, l1);
  5730 + tcg_gen_movi_tl(t0, 0);
5697 5731 tcg_gen_br(l2);
5698 5732 gen_set_label(l1);
5699   - tcg_gen_movi_tl(cpu_T[0], 1);
  5733 + tcg_gen_movi_tl(t0, 1);
5700 5734 gen_set_label(l2);
5701 5735 }
5702 5736 opn = "bc1any2f";
... ... @@ -5708,15 +5742,15 @@ static void gen_compute_branch1 (CPUState *env, DisasContext *ctx, uint32_t op,
5708 5742 TCGv r_tmp1 = tcg_temp_new(TCG_TYPE_I32);
5709 5743  
5710 5744 get_fp_cond(r_tmp1);
5711   - tcg_gen_ext_i32_tl(cpu_T[0], r_tmp1);
  5745 + tcg_gen_ext_i32_tl(t0, r_tmp1);
5712 5746 tcg_temp_free(r_tmp1);
5713   - tcg_gen_movi_tl(cpu_T[1], 0x3 << cc);
5714   - tcg_gen_and_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
5715   - tcg_gen_brcondi_tl(TCG_COND_NE, cpu_T[0], 0, l1);
5716   - tcg_gen_movi_tl(cpu_T[0], 0);
  5747 + tcg_gen_movi_tl(t1, 0x3 << cc);
  5748 + tcg_gen_and_tl(t0, t0, t1);
  5749 + tcg_gen_brcondi_tl(TCG_COND_NE, t0, 0, l1);
  5750 + tcg_gen_movi_tl(t0, 0);
5717 5751 tcg_gen_br(l2);
5718 5752 gen_set_label(l1);
5719   - tcg_gen_movi_tl(cpu_T[0], 1);
  5753 + tcg_gen_movi_tl(t0, 1);
5720 5754 gen_set_label(l2);
5721 5755 }
5722 5756 opn = "bc1any2t";
... ... @@ -5728,16 +5762,16 @@ static void gen_compute_branch1 (CPUState *env, DisasContext *ctx, uint32_t op,
5728 5762 TCGv r_tmp1 = tcg_temp_new(TCG_TYPE_I32);
5729 5763  
5730 5764 get_fp_cond(r_tmp1);
5731   - tcg_gen_ext_i32_tl(cpu_T[0], r_tmp1);
  5765 + tcg_gen_ext_i32_tl(t0, r_tmp1);
5732 5766 tcg_temp_free(r_tmp1);
5733   - tcg_gen_not_tl(cpu_T[0], cpu_T[0]);
5734   - tcg_gen_movi_tl(cpu_T[1], 0xf << cc);
5735   - tcg_gen_and_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
5736   - tcg_gen_brcondi_tl(TCG_COND_NE, cpu_T[0], 0, l1);
5737   - tcg_gen_movi_tl(cpu_T[0], 0);
  5767 + tcg_gen_not_tl(t0, t0);
  5768 + tcg_gen_movi_tl(t1, 0xf << cc);
  5769 + tcg_gen_and_tl(t0, t0, t1);
  5770 + tcg_gen_brcondi_tl(TCG_COND_NE, t0, 0, l1);
  5771 + tcg_gen_movi_tl(t0, 0);
5738 5772 tcg_gen_br(l2);
5739 5773 gen_set_label(l1);
5740   - tcg_gen_movi_tl(cpu_T[0], 1);
  5774 + tcg_gen_movi_tl(t0, 1);
5741 5775 gen_set_label(l2);
5742 5776 }
5743 5777 opn = "bc1any4f";
... ... @@ -5749,30 +5783,34 @@ static void gen_compute_branch1 (CPUState *env, DisasContext *ctx, uint32_t op,
5749 5783 TCGv r_tmp1 = tcg_temp_new(TCG_TYPE_I32);
5750 5784  
5751 5785 get_fp_cond(r_tmp1);
5752   - tcg_gen_ext_i32_tl(cpu_T[0], r_tmp1);
  5786 + tcg_gen_ext_i32_tl(t0, r_tmp1);
5753 5787 tcg_temp_free(r_tmp1);
5754   - tcg_gen_movi_tl(cpu_T[1], 0xf << cc);
5755   - tcg_gen_and_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
5756   - tcg_gen_brcondi_tl(TCG_COND_NE, cpu_T[0], 0, l1);
5757   - tcg_gen_movi_tl(cpu_T[0], 0);
  5788 + tcg_gen_movi_tl(t1, 0xf << cc);
  5789 + tcg_gen_and_tl(t0, t0, t1);
  5790 + tcg_gen_brcondi_tl(TCG_COND_NE, t0, 0, l1);
  5791 + tcg_gen_movi_tl(t0, 0);
5758 5792 tcg_gen_br(l2);
5759 5793 gen_set_label(l1);
5760   - tcg_gen_movi_tl(cpu_T[0], 1);
  5794 + tcg_gen_movi_tl(t0, 1);
5761 5795 gen_set_label(l2);
5762 5796 }
5763 5797 opn = "bc1any4t";
5764 5798 not_likely:
5765 5799 ctx->hflags |= MIPS_HFLAG_BC;
5766   - tcg_gen_st_tl(cpu_T[0], cpu_env, offsetof(CPUState, bcond));
  5800 + tcg_gen_st_tl(t0, cpu_env, offsetof(CPUState, bcond));
5767 5801 break;
5768 5802 default:
5769 5803 MIPS_INVAL(opn);
5770 5804 generate_exception (ctx, EXCP_RI);
5771   - return;
  5805 + goto out;
5772 5806 }
5773 5807 MIPS_DEBUG("%s: cond %02x target " TARGET_FMT_lx, opn,
5774 5808 ctx->hflags, btarget);
5775 5809 ctx->btarget = btarget;
  5810 +
  5811 + out:
  5812 + tcg_temp_free(t0);
  5813 + tcg_temp_free(t1);
5776 5814 }
5777 5815  
5778 5816 /* Coprocessor 1 (FPU) */
... ... @@ -5782,60 +5820,64 @@ static void gen_compute_branch1 (CPUState *env, DisasContext *ctx, uint32_t op,
5782 5820 static void gen_cp1 (DisasContext *ctx, uint32_t opc, int rt, int fs)
5783 5821 {
5784 5822 const char *opn = "cp1 move";
  5823 + TCGv t0 = tcg_temp_local_new(TCG_TYPE_TL);
5785 5824  
5786 5825 switch (opc) {
5787 5826 case OPC_MFC1:
5788 5827 gen_load_fpr32(fpu32_T[0], fs);
5789   - tcg_gen_ext_i32_tl(cpu_T[0], fpu32_T[0]);
5790   - gen_store_gpr(cpu_T[0], rt);
  5828 + tcg_gen_ext_i32_tl(t0, fpu32_T[0]);
  5829 + gen_store_gpr(t0, rt);
5791 5830 opn = "mfc1";
5792 5831 break;
5793 5832 case OPC_MTC1:
5794   - gen_load_gpr(cpu_T[0], rt);
5795   - tcg_gen_trunc_tl_i32(fpu32_T[0], cpu_T[0]);
  5833 + gen_load_gpr(t0, rt);
  5834 + tcg_gen_trunc_tl_i32(fpu32_T[0], t0);
5796 5835 gen_store_fpr32(fpu32_T[0], fs);
5797 5836 opn = "mtc1";
5798 5837 break;
5799 5838 case OPC_CFC1:
5800   - tcg_gen_helper_1_1i(do_cfc1, cpu_T[0], cpu_T[0], fs);
5801   - gen_store_gpr(cpu_T[0], rt);
  5839 + tcg_gen_helper_1_i(do_cfc1, t0, fs);
  5840 + gen_store_gpr(t0, rt);
5802 5841 opn = "cfc1";
5803 5842 break;
5804 5843 case OPC_CTC1:
5805   - gen_load_gpr(cpu_T[0], rt);
5806   - tcg_gen_helper_0_1i(do_ctc1, cpu_T[0], fs);
  5844 + gen_load_gpr(t0, rt);
  5845 + tcg_gen_helper_0_1i(do_ctc1, t0, fs);
5807 5846 opn = "ctc1";
5808 5847 break;
5809 5848 case OPC_DMFC1:
5810 5849 gen_load_fpr64(ctx, fpu64_T[0], fs);
5811   - tcg_gen_mov_tl(cpu_T[0], fpu64_T[0]);
5812   - gen_store_gpr(cpu_T[0], rt);
  5850 + tcg_gen_mov_tl(t0, fpu64_T[0]);
  5851 + gen_store_gpr(t0, rt);
5813 5852 opn = "dmfc1";
5814 5853 break;
5815 5854 case OPC_DMTC1:
5816   - gen_load_gpr(cpu_T[0], rt);
5817   - tcg_gen_mov_tl(fpu64_T[0], cpu_T[0]);
  5855 + gen_load_gpr(t0, rt);
  5856 + tcg_gen_mov_tl(fpu64_T[0], t0);
5818 5857 gen_store_fpr64(ctx, fpu64_T[0], fs);
5819 5858 opn = "dmtc1";
5820 5859 break;
5821 5860 case OPC_MFHC1:
5822 5861 gen_load_fpr32h(fpu32h_T[0], fs);
5823   - tcg_gen_ext_i32_tl(cpu_T[0], fpu32h_T[0]);
5824   - gen_store_gpr(cpu_T[0], rt);
  5862 + tcg_gen_ext_i32_tl(t0, fpu32h_T[0]);
  5863 + gen_store_gpr(t0, rt);
5825 5864 opn = "mfhc1";
5826 5865 break;
5827 5866 case OPC_MTHC1:
5828   - gen_load_gpr(cpu_T[0], rt);
5829   - tcg_gen_trunc_tl_i32(fpu32h_T[0], cpu_T[0]);
  5867 + gen_load_gpr(t0, rt);
  5868 + tcg_gen_trunc_tl_i32(fpu32h_T[0], t0);
5830 5869 gen_store_fpr32h(fpu32h_T[0], fs);
5831 5870 opn = "mthc1";
5832 5871 break;
5833 5872 default:
5834 5873 MIPS_INVAL(opn);
5835 5874 generate_exception (ctx, EXCP_RI);
5836   - return;
  5875 + goto out;
5837 5876 }
5838 5877 MIPS_DEBUG("%s %s %s", opn, regnames[rt], fregnames[fs]);
  5878 +
  5879 + out:
  5880 + tcg_temp_free(t0);
5839 5881 }
5840 5882  
5841 5883 static void gen_movci (DisasContext *ctx, int rd, int rs, int cc, int tf)
... ... @@ -5843,6 +5885,8 @@ static void gen_movci (DisasContext *ctx, int rd, int rs, int cc, int tf)
5843 5885 int l1 = gen_new_label();
5844 5886 uint32_t ccbit;
5845 5887 TCGCond cond;
  5888 + TCGv t0 = tcg_temp_local_new(TCG_TYPE_TL);
  5889 + TCGv t1 = tcg_temp_local_new(TCG_TYPE_TL);
5846 5890  
5847 5891 if (cc)
5848 5892 ccbit = 1 << (24 + cc);
... ... @@ -5853,8 +5897,8 @@ static void gen_movci (DisasContext *ctx, int rd, int rs, int cc, int tf)
5853 5897 else
5854 5898 cond = TCG_COND_NE;
5855 5899  
5856   - gen_load_gpr(cpu_T[0], rd);
5857   - gen_load_gpr(cpu_T[1], rs);
  5900 + gen_load_gpr(t0, rd);
  5901 + gen_load_gpr(t1, rs);
5858 5902 {
5859 5903 TCGv r_ptr = tcg_temp_new(TCG_TYPE_PTR);
5860 5904 TCGv r_tmp = tcg_temp_local_new(TCG_TYPE_I32);
... ... @@ -5866,10 +5910,12 @@ static void gen_movci (DisasContext *ctx, int rd, int rs, int cc, int tf)
5866 5910 tcg_gen_brcondi_i32(cond, r_tmp, 0, l1);
5867 5911 tcg_temp_free(r_tmp);
5868 5912 }
5869   - tcg_gen_mov_tl(cpu_T[0], cpu_T[1]);
  5913 + tcg_gen_mov_tl(t0, t1);
  5914 + tcg_temp_free(t1);
5870 5915  
5871 5916 gen_set_label(l1);
5872   - gen_store_gpr(cpu_T[0], rd);
  5917 + gen_store_gpr(t0, rd);
  5918 + tcg_temp_free(t0);
5873 5919 }
5874 5920  
5875 5921 static inline void gen_movcf_s (int cc, int tf)
... ... @@ -6109,13 +6155,15 @@ static void gen_farith (DisasContext *ctx, uint32_t op1,
6109 6155 opn = "movcf.s";
6110 6156 break;
6111 6157 case FOP(18, 16):
6112   - gen_load_gpr(cpu_T[0], ft);
6113 6158 gen_load_fpr32(fpu32_T[0], fs);
6114 6159 gen_load_fpr32(fpu32_T[2], fd);
6115 6160 {
6116 6161 int l1 = gen_new_label();
  6162 + TCGv t0 = tcg_temp_local_new(TCG_TYPE_TL);
6117 6163  
6118   - tcg_gen_brcondi_tl(TCG_COND_NE, cpu_T[0], 0, l1);
  6164 + gen_load_gpr(t0, ft);
  6165 + tcg_gen_brcondi_tl(TCG_COND_NE, t0, 0, l1);
  6166 + tcg_temp_free(t0);
6119 6167 tcg_gen_mov_i32(fpu32_T[2], fpu32_T[0]);
6120 6168 gen_set_label(l1);
6121 6169 }
... ... @@ -6123,13 +6171,15 @@ static void gen_farith (DisasContext *ctx, uint32_t op1,
6123 6171 opn = "movz.s";
6124 6172 break;
6125 6173 case FOP(19, 16):
6126   - gen_load_gpr(cpu_T[0], ft);
6127 6174 gen_load_fpr32(fpu32_T[0], fs);
6128 6175 gen_load_fpr32(fpu32_T[2], fd);
6129 6176 {
6130 6177 int l1 = gen_new_label();
  6178 + TCGv t0 = tcg_temp_local_new(TCG_TYPE_TL);
6131 6179  
6132   - tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_T[0], 0, l1);
  6180 + gen_load_gpr(t0, ft);
  6181 + tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0, l1);
  6182 + tcg_temp_free(t0);
6133 6183 tcg_gen_mov_i32(fpu32_T[2], fpu32_T[0]);
6134 6184 gen_set_label(l1);
6135 6185 }
... ... @@ -6365,13 +6415,15 @@ static void gen_farith (DisasContext *ctx, uint32_t op1,
6365 6415 opn = "movcf.d";
6366 6416 break;
6367 6417 case FOP(18, 17):
6368   - gen_load_gpr(cpu_T[0], ft);
6369 6418 gen_load_fpr64(ctx, fpu64_T[0], fs);
6370 6419 gen_load_fpr64(ctx, fpu64_T[2], fd);
6371 6420 {
6372 6421 int l1 = gen_new_label();
  6422 + TCGv t0 = tcg_temp_local_new(TCG_TYPE_TL);
6373 6423  
6374   - tcg_gen_brcondi_tl(TCG_COND_NE, cpu_T[0], 0, l1);
  6424 + gen_load_gpr(t0, ft);
  6425 + tcg_gen_brcondi_tl(TCG_COND_NE, t0, 0, l1);
  6426 + tcg_temp_free(t0);
6375 6427 tcg_gen_mov_i64(fpu64_T[2], fpu64_T[0]);
6376 6428 gen_set_label(l1);
6377 6429 }
... ... @@ -6379,13 +6431,15 @@ static void gen_farith (DisasContext *ctx, uint32_t op1,
6379 6431 opn = "movz.d";
6380 6432 break;
6381 6433 case FOP(19, 17):
6382   - gen_load_gpr(cpu_T[0], ft);
6383 6434 gen_load_fpr64(ctx, fpu64_T[0], fs);
6384 6435 gen_load_fpr64(ctx, fpu64_T[2], fd);
6385 6436 {
6386 6437 int l1 = gen_new_label();
  6438 + TCGv t0 = tcg_temp_local_new(TCG_TYPE_TL);
6387 6439  
6388   - tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_T[0], 0, l1);
  6440 + gen_load_gpr(t0, ft);
  6441 + tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0, l1);
  6442 + tcg_temp_free(t0);
6389 6443 tcg_gen_mov_i64(fpu64_T[2], fpu64_T[0]);
6390 6444 gen_set_label(l1);
6391 6445 }
... ... @@ -6594,15 +6648,17 @@ static void gen_farith (DisasContext *ctx, uint32_t op1,
6594 6648 break;
6595 6649 case FOP(18, 22):
6596 6650 check_cp1_64bitmode(ctx);
6597   - gen_load_gpr(cpu_T[0], ft);
6598 6651 gen_load_fpr32(fpu32_T[0], fs);
6599 6652 gen_load_fpr32h(fpu32h_T[0], fs);
6600 6653 gen_load_fpr32(fpu32_T[2], fd);
6601 6654 gen_load_fpr32h(fpu32h_T[2], fd);
6602 6655 {
6603 6656 int l1 = gen_new_label();
  6657 + TCGv t0 = tcg_temp_local_new(TCG_TYPE_TL);
6604 6658  
6605   - tcg_gen_brcondi_tl(TCG_COND_NE, cpu_T[0], 0, l1);
  6659 + gen_load_gpr(t0, ft);
  6660 + tcg_gen_brcondi_tl(TCG_COND_NE, t0, 0, l1);
  6661 + tcg_temp_free(t0);
6606 6662 tcg_gen_mov_i32(fpu32_T[2], fpu32_T[0]);
6607 6663 tcg_gen_mov_i32(fpu32h_T[2], fpu32h_T[0]);
6608 6664 gen_set_label(l1);
... ... @@ -6613,15 +6669,17 @@ static void gen_farith (DisasContext *ctx, uint32_t op1,
6613 6669 break;
6614 6670 case FOP(19, 22):
6615 6671 check_cp1_64bitmode(ctx);
6616   - gen_load_gpr(cpu_T[0], ft);
6617 6672 gen_load_fpr32(fpu32_T[0], fs);
6618 6673 gen_load_fpr32h(fpu32h_T[0], fs);
6619 6674 gen_load_fpr32(fpu32_T[2], fd);
6620 6675 gen_load_fpr32h(fpu32h_T[2], fd);
6621 6676 {
6622 6677 int l1 = gen_new_label();
  6678 + TCGv t0 = tcg_temp_local_new(TCG_TYPE_TL);
6623 6679  
6624   - tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_T[0], 0, l1);
  6680 + gen_load_gpr(t0, ft);
  6681 + tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0, l1);
  6682 + tcg_temp_free(t0);
6625 6683 tcg_gen_mov_i32(fpu32_T[2], fpu32_T[0]);
6626 6684 tcg_gen_mov_i32(fpu32h_T[2], fpu32h_T[0]);
6627 6685 gen_set_label(l1);
... ... @@ -6800,43 +6858,45 @@ static void gen_flt3_ldst (DisasContext *ctx, uint32_t opc,
6800 6858 {
6801 6859 const char *opn = "extended float load/store";
6802 6860 int store = 0;
  6861 + TCGv t0 = tcg_temp_local_new(TCG_TYPE_TL);
  6862 + TCGv t1 = tcg_temp_local_new(TCG_TYPE_TL);
6803 6863  
6804 6864 if (base == 0) {
6805   - gen_load_gpr(cpu_T[0], index);
  6865 + gen_load_gpr(t0, index);
6806 6866 } else if (index == 0) {
6807   - gen_load_gpr(cpu_T[0], base);
  6867 + gen_load_gpr(t0, base);
6808 6868 } else {
6809   - gen_load_gpr(cpu_T[0], base);
6810   - gen_load_gpr(cpu_T[1], index);
6811   - gen_op_addr_add(cpu_T[0], cpu_T[1]);
  6869 + gen_load_gpr(t0, base);
  6870 + gen_load_gpr(t1, index);
  6871 + gen_op_addr_add(t0, t1);
6812 6872 }
6813 6873 /* Don't do NOP if destination is zero: we must perform the actual
6814 6874 memory access. */
6815 6875 switch (opc) {
6816 6876 case OPC_LWXC1:
6817 6877 check_cop1x(ctx);
6818   - tcg_gen_qemu_ld32s(fpu32_T[0], cpu_T[0], ctx->mem_idx);
  6878 + tcg_gen_qemu_ld32s(fpu32_T[0], t0, ctx->mem_idx);
6819 6879 gen_store_fpr32(fpu32_T[0], fd);
6820 6880 opn = "lwxc1";
6821 6881 break;
6822 6882 case OPC_LDXC1:
6823 6883 check_cop1x(ctx);
6824 6884 check_cp1_registers(ctx, fd);
6825   - tcg_gen_qemu_ld64(fpu64_T[0], cpu_T[0], ctx->mem_idx);
  6885 + tcg_gen_qemu_ld64(fpu64_T[0], t0, ctx->mem_idx);
6826 6886 gen_store_fpr64(ctx, fpu64_T[0], fd);
6827 6887 opn = "ldxc1";
6828 6888 break;
6829 6889 case OPC_LUXC1:
6830 6890 check_cp1_64bitmode(ctx);
6831   - tcg_gen_andi_tl(cpu_T[0], cpu_T[0], ~0x7);
6832   - tcg_gen_qemu_ld64(fpu64_T[0], cpu_T[0], ctx->mem_idx);
  6891 + tcg_gen_andi_tl(t0, t0, ~0x7);
  6892 + tcg_gen_qemu_ld64(fpu64_T[0], t0, ctx->mem_idx);
6833 6893 gen_store_fpr64(ctx, fpu64_T[0], fd);
6834 6894 opn = "luxc1";
6835 6895 break;
6836 6896 case OPC_SWXC1:
6837 6897 check_cop1x(ctx);
6838 6898 gen_load_fpr32(fpu32_T[0], fs);
6839   - tcg_gen_qemu_st32(fpu32_T[0], cpu_T[0], ctx->mem_idx);
  6899 + tcg_gen_qemu_st32(fpu32_T[0], t0, ctx->mem_idx);
6840 6900 opn = "swxc1";
6841 6901 store = 1;
6842 6902 break;
... ... @@ -6844,23 +6904,27 @@ static void gen_flt3_ldst (DisasContext *ctx, uint32_t opc,
6844 6904 check_cop1x(ctx);
6845 6905 check_cp1_registers(ctx, fs);
6846 6906 gen_load_fpr64(ctx, fpu64_T[0], fs);
6847   - tcg_gen_qemu_st64(fpu64_T[0], cpu_T[0], ctx->mem_idx);
  6907 + tcg_gen_qemu_st64(fpu64_T[0], t0, ctx->mem_idx);
6848 6908 opn = "sdxc1";
6849 6909 store = 1;
6850 6910 break;
6851 6911 case OPC_SUXC1:
6852 6912 check_cp1_64bitmode(ctx);
6853 6913 gen_load_fpr64(ctx, fpu64_T[0], fs);
6854   - tcg_gen_andi_tl(cpu_T[0], cpu_T[0], ~0x7);
6855   - tcg_gen_qemu_st64(fpu64_T[0], cpu_T[0], ctx->mem_idx);
  6914 + tcg_gen_andi_tl(t0, t0, ~0x7);
  6915 + tcg_gen_qemu_st64(fpu64_T[0], t0, ctx->mem_idx);
6856 6916 opn = "suxc1";
6857 6917 store = 1;
6858 6918 break;
6859 6919 default:
6860 6920 MIPS_INVAL(opn);
6861 6921 generate_exception(ctx, EXCP_RI);
  6922 + tcg_temp_free(t0);
  6923 + tcg_temp_free(t1);
6862 6924 return;
6863 6925 }
  6926 + tcg_temp_free(t0);
  6927 + tcg_temp_free(t1);
6864 6928 MIPS_DEBUG("%s %s, %s(%s)", opn, fregnames[store ? fs : fd],
6865 6929 regnames[index], regnames[base]);
6866 6930 }
... ... @@ -6873,22 +6937,25 @@ static void gen_flt3_arith (DisasContext *ctx, uint32_t opc,
6873 6937 switch (opc) {
6874 6938 case OPC_ALNV_PS:
6875 6939 check_cp1_64bitmode(ctx);
6876   - gen_load_gpr(cpu_T[0], fr);
6877   - tcg_gen_andi_tl(cpu_T[0], cpu_T[0], 0x7);
6878   - gen_load_fpr32(fpu32_T[0], fs);
6879   - gen_load_fpr32h(fpu32h_T[0], fs);
6880   - gen_load_fpr32(fpu32_T[1], ft);
6881   - gen_load_fpr32h(fpu32h_T[1], ft);
6882 6940 {
  6941 + TCGv t0 = tcg_temp_local_new(TCG_TYPE_TL);
6883 6942 int l1 = gen_new_label();
6884 6943 int l2 = gen_new_label();
6885 6944  
6886   - tcg_gen_brcondi_tl(TCG_COND_NE, cpu_T[0], 0, l1);
  6945 + gen_load_gpr(t0, fr);
  6946 + tcg_gen_andi_tl(t0, t0, 0x7);
  6947 + gen_load_fpr32(fpu32_T[0], fs);
  6948 + gen_load_fpr32h(fpu32h_T[0], fs);
  6949 + gen_load_fpr32(fpu32_T[1], ft);
  6950 + gen_load_fpr32h(fpu32h_T[1], ft);
  6951 +
  6952 + tcg_gen_brcondi_tl(TCG_COND_NE, t0, 0, l1);
6887 6953 tcg_gen_mov_i32(fpu32_T[2], fpu32_T[0]);
6888 6954 tcg_gen_mov_i32(fpu32h_T[2], fpu32h_T[0]);
6889 6955 tcg_gen_br(l2);
6890 6956 gen_set_label(l1);
6891   - tcg_gen_brcondi_tl(TCG_COND_NE, cpu_T[0], 4, l2);
  6957 + tcg_gen_brcondi_tl(TCG_COND_NE, t0, 4, l2);
  6958 + tcg_temp_free(t0);
6892 6959 #ifdef TARGET_WORDS_BIGENDIAN
6893 6960 tcg_gen_mov_i32(fpu32h_T[2], fpu32_T[0]);
6894 6961 tcg_gen_mov_i32(fpu32_T[2], fpu32h_T[1]);
... ... @@ -7247,70 +7314,96 @@ static void decode_opc (CPUState *env, DisasContext *ctx)
7247 7314 case OPC_BSHFL:
7248 7315 check_insn(env, ctx, ISA_MIPS32R2);
7249 7316 op2 = MASK_BSHFL(ctx->opcode);
7250   - switch (op2) {
7251   - case OPC_WSBH:
7252   - gen_load_gpr(cpu_T[1], rt);
7253   - tcg_gen_helper_1_2(do_wsbh, cpu_T[0], cpu_T[0], cpu_T[1]);
7254   - break;
7255   - case OPC_SEB:
7256   - gen_load_gpr(cpu_T[1], rt);
7257   - tcg_gen_ext8s_tl(cpu_T[0], cpu_T[1]);
7258   - break;
7259   - case OPC_SEH:
7260   - gen_load_gpr(cpu_T[1], rt);
7261   - tcg_gen_ext16s_tl(cpu_T[0], cpu_T[1]);
7262   - break;
7263   - default: /* Invalid */
7264   - MIPS_INVAL("bshfl");
7265   - generate_exception(ctx, EXCP_RI);
7266   - break;
  7317 + {
  7318 + TCGv t0 = tcg_temp_local_new(TCG_TYPE_TL);
  7319 + TCGv t1 = tcg_temp_local_new(TCG_TYPE_TL);
  7320 +
  7321 + switch (op2) {
  7322 + case OPC_WSBH:
  7323 + gen_load_gpr(t1, rt);
  7324 + tcg_gen_helper_1_2(do_wsbh, t0, t0, t1);
  7325 + gen_store_gpr(t0, rd);
  7326 + break;
  7327 + case OPC_SEB:
  7328 + gen_load_gpr(t1, rt);
  7329 + tcg_gen_ext8s_tl(t0, t1);
  7330 + gen_store_gpr(t0, rd);
  7331 + break;
  7332 + case OPC_SEH:
  7333 + gen_load_gpr(t1, rt);
  7334 + tcg_gen_ext16s_tl(t0, t1);
  7335 + gen_store_gpr(t0, rd);
  7336 + break;
  7337 + default: /* Invalid */
  7338 + MIPS_INVAL("bshfl");
  7339 + generate_exception(ctx, EXCP_RI);
  7340 + break;
  7341 + }
  7342 + tcg_temp_free(t0);
  7343 + tcg_temp_free(t1);
7267 7344 }
7268   - gen_store_gpr(cpu_T[0], rd);
7269 7345 break;
7270 7346 case OPC_RDHWR:
7271 7347 check_insn(env, ctx, ISA_MIPS32R2);
7272   - switch (rd) {
7273   - case 0:
7274   - save_cpu_state(ctx, 1);
7275   - tcg_gen_helper_1_1(do_rdhwr_cpunum, cpu_T[0], cpu_T[0]);
7276   - break;
7277   - case 1:
7278   - save_cpu_state(ctx, 1);
7279   - tcg_gen_helper_1_1(do_rdhwr_synci_step, cpu_T[0], cpu_T[0]);
7280   - break;
7281   - case 2:
7282   - save_cpu_state(ctx, 1);
7283   - tcg_gen_helper_1_1(do_rdhwr_cc, cpu_T[0], cpu_T[0]);
7284   - break;
7285   - case 3:
7286   - save_cpu_state(ctx, 1);
7287   - tcg_gen_helper_1_1(do_rdhwr_ccres, cpu_T[0], cpu_T[0]);
7288   - break;
7289   - case 29:
  7348 + {
  7349 + TCGv t0 = tcg_temp_local_new(TCG_TYPE_TL);
  7350 +
  7351 + switch (rd) {
  7352 + case 0:
  7353 + save_cpu_state(ctx, 1);
  7354 + tcg_gen_helper_1_1(do_rdhwr_cpunum, t0, t0);
  7355 + break;
  7356 + case 1:
  7357 + save_cpu_state(ctx, 1);
  7358 + tcg_gen_helper_1_1(do_rdhwr_synci_step, t0, t0);
  7359 + break;
  7360 + case 2:
  7361 + save_cpu_state(ctx, 1);
  7362 + tcg_gen_helper_1_1(do_rdhwr_cc, t0, t0);
  7363 + break;
  7364 + case 3:
  7365 + save_cpu_state(ctx, 1);
  7366 + tcg_gen_helper_1_1(do_rdhwr_ccres, t0, t0);
  7367 + break;
  7368 + case 29:
7290 7369 #if defined (CONFIG_USER_ONLY)
7291   - tcg_gen_ld_tl(cpu_T[0], cpu_env, offsetof(CPUState, tls_value));
7292   - break;
  7370 + tcg_gen_ld_tl(t0, cpu_env, offsetof(CPUState, tls_value));
  7371 + break;
7293 7372 #else
7294   - /* XXX: Some CPUs implement this in hardware. Not supported yet. */
  7373 + /* XXX: Some CPUs implement this in hardware. Not supported yet. */
7295 7374 #endif
7296   - default: /* Invalid */
7297   - MIPS_INVAL("rdhwr");
7298   - generate_exception(ctx, EXCP_RI);
7299   - break;
  7375 + default: /* Invalid */
  7376 + MIPS_INVAL("rdhwr");
  7377 + generate_exception(ctx, EXCP_RI);
  7378 + break;
  7379 + }
  7380 + gen_store_gpr(t0, rt);
  7381 + tcg_temp_free(t0);
7300 7382 }
7301   - gen_store_gpr(cpu_T[0], rt);
7302 7383 break;
7303 7384 case OPC_FORK:
7304 7385 check_insn(env, ctx, ASE_MT);
7305   - gen_load_gpr(cpu_T[0], rt);
7306   - gen_load_gpr(cpu_T[1], rs);
7307   - tcg_gen_helper_1_2(do_fork, cpu_T[0], cpu_T[0], cpu_T[1]);
  7386 + {
  7387 + TCGv t0 = tcg_temp_local_new(TCG_TYPE_TL);
  7388 + TCGv t1 = tcg_temp_local_new(TCG_TYPE_TL);
  7389 +
  7390 + gen_load_gpr(t0, rt);
  7391 + gen_load_gpr(t1, rs);
  7392 + tcg_gen_helper_0_2(do_fork, t0, t1);
  7393 + tcg_temp_free(t0);
  7394 + tcg_temp_free(t1);
  7395 + }
7308 7396 break;
7309 7397 case OPC_YIELD:
7310 7398 check_insn(env, ctx, ASE_MT);
7311   - gen_load_gpr(cpu_T[0], rs);
7312   - tcg_gen_helper_1_1(do_yield, cpu_T[0], cpu_T[0]);
7313   - gen_store_gpr(cpu_T[0], rd);
  7399 + {
  7400 + TCGv t0 = tcg_temp_local_new(TCG_TYPE_TL);
  7401 +
  7402 + gen_load_gpr(t0, rs);
  7403 + tcg_gen_helper_1_1(do_yield, t0, t0);
  7404 + gen_store_gpr(t0, rd);
  7405 + tcg_temp_free(t0);
  7406 + }
7314 7407 break;
7315 7408 #if defined(TARGET_MIPS64)
7316 7409 case OPC_DEXTM ... OPC_DEXT:
... ... @@ -7323,21 +7416,28 @@ static void decode_opc (CPUState *env, DisasContext *ctx)
7323 7416 check_insn(env, ctx, ISA_MIPS64R2);
7324 7417 check_mips_64(ctx);
7325 7418 op2 = MASK_DBSHFL(ctx->opcode);
7326   - switch (op2) {
7327   - case OPC_DSBH:
7328   - gen_load_gpr(cpu_T[1], rt);
7329   - tcg_gen_helper_1_2(do_dsbh, cpu_T[0], cpu_T[0], cpu_T[1]);
7330   - break;
7331   - case OPC_DSHD:
7332   - gen_load_gpr(cpu_T[1], rt);
7333   - tcg_gen_helper_1_2(do_dshd, cpu_T[0], cpu_T[0], cpu_T[1]);
7334   - break;
7335   - default: /* Invalid */
7336   - MIPS_INVAL("dbshfl");
7337   - generate_exception(ctx, EXCP_RI);
7338   - break;
  7419 + {
  7420 + TCGv t0 = tcg_temp_local_new(TCG_TYPE_TL);
  7421 + TCGv t1 = tcg_temp_local_new(TCG_TYPE_TL);
  7422 +
  7423 + switch (op2) {
  7424 + case OPC_DSBH:
  7425 + gen_load_gpr(t1, rt);
  7426 + tcg_gen_helper_1_2(do_dsbh, t0, t0, t1);
  7427 + break;
  7428 + case OPC_DSHD:
  7429 + gen_load_gpr(t1, rt);
  7430 + tcg_gen_helper_1_2(do_dshd, t0, t0, t1);
  7431 + break;
  7432 + default: /* Invalid */
  7433 + MIPS_INVAL("dbshfl");
  7434 + generate_exception(ctx, EXCP_RI);
  7435 + break;
  7436 + }
  7437 + gen_store_gpr(t0, rd);
  7438 + tcg_temp_free(t0);
  7439 + tcg_temp_free(t1);
7339 7440 }
7340   - gen_store_gpr(cpu_T[0], rd);
7341 7441 break;
7342 7442 #endif
7343 7443 default: /* Invalid */
... ... @@ -7390,43 +7490,48 @@ static void decode_opc (CPUState *env, DisasContext *ctx)
7390 7490 break;
7391 7491 case OPC_MFMC0:
7392 7492 op2 = MASK_MFMC0(ctx->opcode);
7393   - switch (op2) {
7394   - case OPC_DMT:
7395   - check_insn(env, ctx, ASE_MT);
7396   - tcg_gen_helper_1_1(do_dmt, cpu_T[0], cpu_T[0]);
7397   - break;
7398   - case OPC_EMT:
7399   - check_insn(env, ctx, ASE_MT);
7400   - tcg_gen_helper_1_1(do_emt, cpu_T[0], cpu_T[0]);
7401   - break;
7402   - case OPC_DVPE:
7403   - check_insn(env, ctx, ASE_MT);
7404   - tcg_gen_helper_1_1(do_dvpe, cpu_T[0], cpu_T[0]);
7405   - break;
7406   - case OPC_EVPE:
7407   - check_insn(env, ctx, ASE_MT);
7408   - tcg_gen_helper_1_1(do_evpe, cpu_T[0], cpu_T[0]);
7409   - break;
7410   - case OPC_DI:
7411   - check_insn(env, ctx, ISA_MIPS32R2);
7412   - save_cpu_state(ctx, 1);
7413   - tcg_gen_helper_1_1(do_di, cpu_T[0], cpu_T[0]);
7414   - /* Stop translation as we may have switched the execution mode */
7415   - ctx->bstate = BS_STOP;
7416   - break;
7417   - case OPC_EI:
7418   - check_insn(env, ctx, ISA_MIPS32R2);
7419   - save_cpu_state(ctx, 1);
7420   - tcg_gen_helper_1_1(do_ei, cpu_T[0], cpu_T[0]);
7421   - /* Stop translation as we may have switched the execution mode */
7422   - ctx->bstate = BS_STOP;
7423   - break;
7424   - default: /* Invalid */
7425   - MIPS_INVAL("mfmc0");
7426   - generate_exception(ctx, EXCP_RI);
7427   - break;
  7493 + {
  7494 + TCGv t0 = tcg_temp_local_new(TCG_TYPE_TL);
  7495 +
  7496 + switch (op2) {
  7497 + case OPC_DMT:
  7498 + check_insn(env, ctx, ASE_MT);
  7499 + tcg_gen_helper_1_1(do_dmt, t0, t0);
  7500 + break;
  7501 + case OPC_EMT:
  7502 + check_insn(env, ctx, ASE_MT);
  7503 + tcg_gen_helper_1_1(do_emt, t0, t0);
  7504 + break;
  7505 + case OPC_DVPE:
  7506 + check_insn(env, ctx, ASE_MT);
  7507 + tcg_gen_helper_1_1(do_dvpe, t0, t0);
  7508 + break;
  7509 + case OPC_EVPE:
  7510 + check_insn(env, ctx, ASE_MT);
  7511 + tcg_gen_helper_1_1(do_evpe, t0, t0);
  7512 + break;
  7513 + case OPC_DI:
  7514 + check_insn(env, ctx, ISA_MIPS32R2);
  7515 + save_cpu_state(ctx, 1);
  7516 + tcg_gen_helper_1_1(do_di, t0, t0);
  7517 + /* Stop translation as we may have switched the execution mode */
  7518 + ctx->bstate = BS_STOP;
  7519 + break;
  7520 + case OPC_EI:
  7521 + check_insn(env, ctx, ISA_MIPS32R2);
  7522 + save_cpu_state(ctx, 1);
  7523 + tcg_gen_helper_1_1(do_ei, t0, t0);
  7524 + /* Stop translation as we may have switched the execution mode */
  7525 + ctx->bstate = BS_STOP;
  7526 + break;
  7527 + default: /* Invalid */
  7528 + MIPS_INVAL("mfmc0");
  7529 + generate_exception(ctx, EXCP_RI);
  7530 + break;
  7531 + }
  7532 + gen_store_gpr(t0, rt);
  7533 + tcg_temp_free(t0);
7428 7534 }
7429   - gen_store_gpr(cpu_T[0], rt);
7430 7535 break;
7431 7536 case OPC_RDPGPR:
7432 7537 check_insn(env, ctx, ISA_MIPS32R2);
... ...