Commit 6bb72b184d7fe0e1e08f9cca722e78d1d24920c2
1 parent
88cbb980
target-mips: proper sign extension for 'SUBU rd, zero, rt'
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
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target-mips/translate.c
| ... | ... | @@ -1604,6 +1604,7 @@ static void gen_arith (CPUState *env, DisasContext *ctx, uint32_t opc, |
| 1604 | 1604 | tcg_gen_ext32s_tl(cpu_gpr[rd], cpu_gpr[rd]); |
| 1605 | 1605 | } else if (rs == 0 && rt != 0) { |
| 1606 | 1606 | tcg_gen_neg_tl(cpu_gpr[rd], cpu_gpr[rt]); |
| 1607 | + tcg_gen_ext32s_tl(cpu_gpr[rd], cpu_gpr[rd]); | |
| 1607 | 1608 | } else if (rs != 0 && rt == 0) { |
| 1608 | 1609 | tcg_gen_mov_tl(cpu_gpr[rd], cpu_gpr[rs]); |
| 1609 | 1610 | } else { | ... | ... |