Commit 6a824ec3d2e3d9b061c31aa14535eb7e08a6846c
1 parent
a7086888
ARM timers qdev conversion
Signed-off-by: Paul Brook <paul@codesourcery.com>
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5 changed files
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39 additions
and
30 deletions
hw/arm_timer.c
@@ -7,9 +7,8 @@ | @@ -7,9 +7,8 @@ | ||
7 | * This code is licenced under the GPL. | 7 | * This code is licenced under the GPL. |
8 | */ | 8 | */ |
9 | 9 | ||
10 | -#include "hw.h" | 10 | +#include "sysbus.h" |
11 | #include "qemu-timer.h" | 11 | #include "qemu-timer.h" |
12 | -#include "primecell.h" | ||
13 | 12 | ||
14 | /* Common timer implementation. */ | 13 | /* Common timer implementation. */ |
15 | 14 | ||
@@ -164,13 +163,12 @@ static int arm_timer_load(QEMUFile *f, void *opaque, int version_id) | @@ -164,13 +163,12 @@ static int arm_timer_load(QEMUFile *f, void *opaque, int version_id) | ||
164 | return 0; | 163 | return 0; |
165 | } | 164 | } |
166 | 165 | ||
167 | -static void *arm_timer_init(uint32_t freq, qemu_irq irq) | 166 | +static arm_timer_state *arm_timer_init(uint32_t freq) |
168 | { | 167 | { |
169 | arm_timer_state *s; | 168 | arm_timer_state *s; |
170 | QEMUBH *bh; | 169 | QEMUBH *bh; |
171 | 170 | ||
172 | s = (arm_timer_state *)qemu_mallocz(sizeof(arm_timer_state)); | 171 | s = (arm_timer_state *)qemu_mallocz(sizeof(arm_timer_state)); |
173 | - s->irq = irq; | ||
174 | s->freq = freq; | 172 | s->freq = freq; |
175 | s->control = TIMER_CTRL_IE; | 173 | s->control = TIMER_CTRL_IE; |
176 | 174 | ||
@@ -186,7 +184,8 @@ static void *arm_timer_init(uint32_t freq, qemu_irq irq) | @@ -186,7 +184,8 @@ static void *arm_timer_init(uint32_t freq, qemu_irq irq) | ||
186 | Integrator/CP timer modules. */ | 184 | Integrator/CP timer modules. */ |
187 | 185 | ||
188 | typedef struct { | 186 | typedef struct { |
189 | - void *timer[2]; | 187 | + SysBusDevice busdev; |
188 | + arm_timer_state *timer[2]; | ||
190 | int level[2]; | 189 | int level[2]; |
191 | qemu_irq irq; | 190 | qemu_irq irq; |
192 | } sp804_state; | 191 | } sp804_state; |
@@ -255,22 +254,23 @@ static int sp804_load(QEMUFile *f, void *opaque, int version_id) | @@ -255,22 +254,23 @@ static int sp804_load(QEMUFile *f, void *opaque, int version_id) | ||
255 | return 0; | 254 | return 0; |
256 | } | 255 | } |
257 | 256 | ||
258 | -void sp804_init(uint32_t base, qemu_irq irq) | 257 | +static void sp804_init(SysBusDevice *dev) |
259 | { | 258 | { |
260 | int iomemtype; | 259 | int iomemtype; |
261 | - sp804_state *s; | 260 | + sp804_state *s = FROM_SYSBUS(sp804_state, dev); |
262 | qemu_irq *qi; | 261 | qemu_irq *qi; |
263 | 262 | ||
264 | - s = (sp804_state *)qemu_mallocz(sizeof(sp804_state)); | ||
265 | qi = qemu_allocate_irqs(sp804_set_irq, s, 2); | 263 | qi = qemu_allocate_irqs(sp804_set_irq, s, 2); |
266 | - s->irq = irq; | 264 | + sysbus_init_irq(dev, &s->irq); |
267 | /* ??? The timers are actually configurable between 32kHz and 1MHz, but | 265 | /* ??? The timers are actually configurable between 32kHz and 1MHz, but |
268 | we don't implement that. */ | 266 | we don't implement that. */ |
269 | - s->timer[0] = arm_timer_init(1000000, qi[0]); | ||
270 | - s->timer[1] = arm_timer_init(1000000, qi[1]); | 267 | + s->timer[0] = arm_timer_init(1000000); |
268 | + s->timer[1] = arm_timer_init(1000000); | ||
269 | + s->timer[0]->irq = qi[0]; | ||
270 | + s->timer[1]->irq = qi[1]; | ||
271 | iomemtype = cpu_register_io_memory(0, sp804_readfn, | 271 | iomemtype = cpu_register_io_memory(0, sp804_readfn, |
272 | sp804_writefn, s); | 272 | sp804_writefn, s); |
273 | - cpu_register_physical_memory(base, 0x00001000, iomemtype); | 273 | + sysbus_init_mmio(dev, 0x1000, iomemtype); |
274 | register_savevm("sp804", -1, 1, sp804_save, sp804_load, s); | 274 | register_savevm("sp804", -1, 1, sp804_save, sp804_load, s); |
275 | } | 275 | } |
276 | 276 | ||
@@ -278,7 +278,8 @@ void sp804_init(uint32_t base, qemu_irq irq) | @@ -278,7 +278,8 @@ void sp804_init(uint32_t base, qemu_irq irq) | ||
278 | /* Integrator/CP timer module. */ | 278 | /* Integrator/CP timer module. */ |
279 | 279 | ||
280 | typedef struct { | 280 | typedef struct { |
281 | - void *timer[3]; | 281 | + SysBusDevice busdev; |
282 | + arm_timer_state *timer[3]; | ||
282 | } icp_pit_state; | 283 | } icp_pit_state; |
283 | 284 | ||
284 | static uint32_t icp_pit_read(void *opaque, target_phys_addr_t offset) | 285 | static uint32_t icp_pit_read(void *opaque, target_phys_addr_t offset) |
@@ -322,21 +323,32 @@ static CPUWriteMemoryFunc *icp_pit_writefn[] = { | @@ -322,21 +323,32 @@ static CPUWriteMemoryFunc *icp_pit_writefn[] = { | ||
322 | icp_pit_write | 323 | icp_pit_write |
323 | }; | 324 | }; |
324 | 325 | ||
325 | -void icp_pit_init(uint32_t base, qemu_irq *pic, int irq) | 326 | +static void icp_pit_init(SysBusDevice *dev) |
326 | { | 327 | { |
327 | int iomemtype; | 328 | int iomemtype; |
328 | - icp_pit_state *s; | 329 | + icp_pit_state *s = FROM_SYSBUS(icp_pit_state, dev); |
329 | 330 | ||
330 | - s = (icp_pit_state *)qemu_mallocz(sizeof(icp_pit_state)); | ||
331 | /* Timer 0 runs at the system clock speed (40MHz). */ | 331 | /* Timer 0 runs at the system clock speed (40MHz). */ |
332 | - s->timer[0] = arm_timer_init(40000000, pic[irq]); | 332 | + s->timer[0] = arm_timer_init(40000000); |
333 | /* The other two timers run at 1MHz. */ | 333 | /* The other two timers run at 1MHz. */ |
334 | - s->timer[1] = arm_timer_init(1000000, pic[irq + 1]); | ||
335 | - s->timer[2] = arm_timer_init(1000000, pic[irq + 2]); | 334 | + s->timer[1] = arm_timer_init(1000000); |
335 | + s->timer[2] = arm_timer_init(1000000); | ||
336 | + | ||
337 | + sysbus_init_irq(dev, &s->timer[0]->irq); | ||
338 | + sysbus_init_irq(dev, &s->timer[1]->irq); | ||
339 | + sysbus_init_irq(dev, &s->timer[2]->irq); | ||
336 | 340 | ||
337 | iomemtype = cpu_register_io_memory(0, icp_pit_readfn, | 341 | iomemtype = cpu_register_io_memory(0, icp_pit_readfn, |
338 | icp_pit_writefn, s); | 342 | icp_pit_writefn, s); |
339 | - cpu_register_physical_memory(base, 0x00001000, iomemtype); | 343 | + sysbus_init_mmio(dev, 0x1000, iomemtype); |
340 | /* This device has no state to save/restore. The component timers will | 344 | /* This device has no state to save/restore. The component timers will |
341 | save themselves. */ | 345 | save themselves. */ |
342 | } | 346 | } |
347 | + | ||
348 | +static void arm_timer_register_devices(void) | ||
349 | +{ | ||
350 | + sysbus_register_dev("integrator_pit", sizeof(icp_pit_state), icp_pit_init); | ||
351 | + sysbus_register_dev("sp804", sizeof(sp804_state), sp804_init); | ||
352 | +} | ||
353 | + | ||
354 | +device_init(arm_timer_register_devices) |
hw/integratorcp.c
@@ -486,8 +486,9 @@ static void integratorcp_init(ram_addr_t ram_size, | @@ -486,8 +486,9 @@ static void integratorcp_init(ram_addr_t ram_size, | ||
486 | for (i = 0; i < 32; i++) { | 486 | for (i = 0; i < 32; i++) { |
487 | pic[i] = qdev_get_irq_sink(dev, i); | 487 | pic[i] = qdev_get_irq_sink(dev, i); |
488 | } | 488 | } |
489 | - dev = sysbus_create_simple("integrator_pic", 0xca000000, pic[26]); | ||
490 | - icp_pit_init(0x13000000, pic, 5); | 489 | + sysbus_create_simple("integrator_pic", 0xca000000, pic[26]); |
490 | + sysbus_create_varargs("integrator_pit", 0x13000000, | ||
491 | + pic[5], pic[6], pic[7], NULL); | ||
491 | sysbus_create_simple("pl031", 0x15000000, pic[8]); | 492 | sysbus_create_simple("pl031", 0x15000000, pic[8]); |
492 | sysbus_create_simple("pl011", 0x16000000, pic[1]); | 493 | sysbus_create_simple("pl011", 0x16000000, pic[1]); |
493 | sysbus_create_simple("pl011", 0x17000000, pic[2]); | 494 | sysbus_create_simple("pl011", 0x17000000, pic[2]); |
hw/primecell.h
@@ -26,10 +26,6 @@ qemu_irq *realview_gic_init(uint32_t base, qemu_irq parent_irq); | @@ -26,10 +26,6 @@ qemu_irq *realview_gic_init(uint32_t base, qemu_irq parent_irq); | ||
26 | /* mpcore.c */ | 26 | /* mpcore.c */ |
27 | extern qemu_irq *mpcore_irq_init(qemu_irq *cpu_irq); | 27 | extern qemu_irq *mpcore_irq_init(qemu_irq *cpu_irq); |
28 | 28 | ||
29 | -/* arm-timer.c */ | ||
30 | -void sp804_init(uint32_t base, qemu_irq irq); | ||
31 | -void icp_pit_init(uint32_t base, qemu_irq *pic, int irq); | ||
32 | - | ||
33 | /* arm_sysctl.c */ | 29 | /* arm_sysctl.c */ |
34 | void arm_sysctl_init(uint32_t base, uint32_t sys_id); | 30 | void arm_sysctl_init(uint32_t base, uint32_t sys_id); |
35 | 31 |
hw/realview.c
@@ -91,8 +91,8 @@ static void realview_init(ram_addr_t ram_size, | @@ -91,8 +91,8 @@ static void realview_init(ram_addr_t ram_size, | ||
91 | /* DMA controller is optional, apparently. */ | 91 | /* DMA controller is optional, apparently. */ |
92 | pl080_init(0x10030000, pic[24], 2); | 92 | pl080_init(0x10030000, pic[24], 2); |
93 | 93 | ||
94 | - sp804_init(0x10011000, pic[4]); | ||
95 | - sp804_init(0x10012000, pic[5]); | 94 | + sysbus_create_simple("sp804", 0x10011000, pic[4]); |
95 | + sysbus_create_simple("sp804", 0x10012000, pic[5]); | ||
96 | 96 | ||
97 | sysbus_create_simple("pl110_versatile", 0x10020000, pic[23]); | 97 | sysbus_create_simple("pl110_versatile", 0x10020000, pic[23]); |
98 | 98 |
hw/versatilepb.c
@@ -216,8 +216,8 @@ static void versatile_init(ram_addr_t ram_size, | @@ -216,8 +216,8 @@ static void versatile_init(ram_addr_t ram_size, | ||
216 | sysbus_create_simple("pl011", 0x10009000, sic[6]); | 216 | sysbus_create_simple("pl011", 0x10009000, sic[6]); |
217 | 217 | ||
218 | pl080_init(0x10130000, pic[17], 8); | 218 | pl080_init(0x10130000, pic[17], 8); |
219 | - sp804_init(0x101e2000, pic[4]); | ||
220 | - sp804_init(0x101e3000, pic[5]); | 219 | + sysbus_create_simple("sp804", 0x101e2000, pic[4]); |
220 | + sysbus_create_simple("sp804", 0x101e3000, pic[5]); | ||
221 | 221 | ||
222 | /* The versatile/PB actually has a modified Color LCD controller | 222 | /* The versatile/PB actually has a modified Color LCD controller |
223 | that includes hardware cursor support from the PL111. */ | 223 | that includes hardware cursor support from the PL111. */ |