gwj / at91sam9263 · Commits

Commit 69efbf189af64aff53b4ee20a7078ba2fed982fc

Authored by Evgeniy Dushistov
1 parent 2d106186

- use pmc module 

- use pitc,aic and dbgu shared modules,
- replace home made pio IP block with at91_pio
- add tc, and reset controller:
- reset from redboot not working
- fix usage of tc device in at91sam9263 emulation
- use emac code in at91sam9
Inline Side-by-side
Showing 2 changed files with 50 additions and 378 deletions
hw/at91sam9.c
  View file @69efbf1
... ... @@ -17,11 +17,12 @@
17 17 #include "boards.h"
18 18 #include "qemu-char.h"
19 19 #include "qemu-timer.h"
  20 +#include "sysbus.h"
20 21  
21 22 #include "at91sam9263_defs.h"
22 23  
23 24 //#define AT91_TRACE_ON
24   -//#define AT91_DEBUG_ON
  25 +#define AT91_DEBUG_ON
25 26  
26 27 #define ARM_AIC_CPU_IRQ 0
27 28 #define ARM_AIC_CPU_FIQ 1
... ... @@ -56,15 +57,10 @@ struct dbgu_state {
56 57 };
57 58  
58 59 struct at91sam9_state {
59   - uint32_t pmc_regs[28];
60   - uint32_t dbgu_regs[0x124 / 4];
61 60 uint32_t bus_matrix_regs[0x100 / 4];
62 61 uint32_t ccfg_regs[(0x01FC - 0x0110 + 1) / sizeof(uint32_t)];
63   - uint32_t pio_regs[(AT91_PMC_BASE - AT91_PIO_BASE) / sizeof(uint32_t)];
64 62 uint32_t sdramc0_regs[(AT91_SMC0_BASE - AT91_SDRAMC0_BASE) / sizeof(uint32_t)];
65 63 uint32_t smc0_regs[(AT91_ECC1_BASE - AT91_SMC0_BASE) / sizeof(uint32_t)];
66   - uint32_t pitc_regs[80];
67   - uint32_t aic_regs[(AT91_PIO_BASE - AT91_AIC_BASE) / sizeof(uint32_t)];
68 64 uint32_t usart0_regs[0x1000 / sizeof(uint32_t)];
69 65 struct dbgu_state dbgu;
70 66 pflash_t *norflash;
... ... @@ -74,149 +70,8 @@ struct at91sam9_state {
74 70 int timer_active;
75 71 CPUState *env;
76 72 qemu_irq *qirq;
77   - uint64_t char_transmit_time;
78 73 };
79 74  
80   -static uint32_t at91_pmc_read(void *opaque, target_phys_addr_t offset)
81   -{
82   - struct at91sam9_state *sam9 = (struct at91sam9_state *)opaque;
83   - TRACE("pmc read offset %X\n", offset);
84   - return sam9->pmc_regs[offset / 4];
85   -}
86   -
87   -static void at91_pmc_write(void *opaque, target_phys_addr_t offset,
88   - uint32_t value)
89   -{
90   - struct at91sam9_state *sam9 = (struct at91sam9_state *)opaque;
91   -
92   - TRACE("pmc write offset %X, value %X\n", offset, value);
93   - switch (offset / 4) {
94   - case AT91_PMC_MCKR:
95   - sam9->pmc_regs[AT91_PMC_MCKR] = value;
96   - switch (value & AT91_PMC_CSS) {
97   - case 1:
98   - //Main clock is selected
99   - sam9->pmc_regs[AT91_PMC_SR] |= AT91_PMC_MCKRDY | AT91_PMC_MOSCS;
100   - break;
101   - default:
102   - DEBUG("unimplemented\n");
103   - break;
104   - }
105   - break;
106   - case AT91_PMC_MOR:
107   - sam9->pmc_regs[AT91_PMC_MOR] = value;
108   - if (value & 1) {
109   - sam9->pmc_regs[AT91_PMC_SR] |= AT91_PMC_MOSCS;
110   - }
111   - break;
112   - case AT91_PMC_PLLAR:
113   - sam9->pmc_regs[AT91_PMC_PLLAR] = value;
114   - sam9->pmc_regs[AT91_PMC_SR] |= AT91_PMC_LOCKA;
115   - break;
116   - case AT91_PMC_PLLBR:
117   - sam9->pmc_regs[AT91_PMC_PLLBR] = value;
118   - sam9->pmc_regs[AT91_PMC_SR] |= AT91_PMC_LOCKB;
119   - break;
120   - case AT91_PMC_PCER:
121   - sam9->pmc_regs[AT91_PMC_PCER] |= value;
122   - break;
123   - default:
124   - //DEBUG("unimplemented, offset %X\n", offset);
125   - break;
126   - }
127   -}
128   -
129   -static uint32_t at91_dbgu_read(void *opaque, target_phys_addr_t offset)
130   -{
131   - struct at91sam9_state *sam9 = (struct at91sam9_state *)opaque;
132   -
133   - offset /= 4;
134   - if (offset == AT91_DBGU_RHR) {
135   - sam9->dbgu_regs[AT91_DBGU_SR] &= (uint32_t)~1;
136   - }/* else if (offset == AT91_DBGU_SR)*/
137   -
138   - return sam9->dbgu_regs[offset];
139   -}
140   -
141   -static void at91_dbgu_state_changed(struct at91sam9_state *sam9)
142   -{
143   - if ((sam9->aic_regs[AT91_AIC_IECR] & (1 << AT91_PERIPH_SYS_ID)) &&
144   - (sam9->dbgu_regs[AT91_DBGU_IMR] & sam9->dbgu_regs[AT91_DBGU_SR])) {
145   - sam9->aic_regs[AT91_AIC_ISR] = AT91_PERIPH_SYS_ID;
146   - sam9->aic_regs[AT91_AIC_IVR] = sam9->aic_regs[AT91_AIC_SVR0 + AT91_PERIPH_SYS_ID];
147   - qemu_irq_raise(sam9->qirq[0]);
148   - }
149   -}
150   -
151   -static void dbgu_serial_end_xmit(void *opaque)
152   -{
153   - struct at91sam9_state *sam9 = (struct at91sam9_state *)opaque;
154   - sam9->dbgu_regs[AT91_DBGU_SR] |= (AT91_US_TXEMPTY | AT91_US_TXRDY);
155   - at91_dbgu_state_changed(sam9);
156   -}
157   -
158   -static void at91_dbgu_write(void *opaque, target_phys_addr_t offset,
159   - uint32_t value)
160   -{
161   - unsigned char ch;
162   - struct at91sam9_state *sam9 = (struct at91sam9_state *)opaque;
163   -
164   - switch (offset / 4) {
165   - case AT91_DBGU_CR:
166   - sam9->dbgu_regs[AT91_DBGU_CR] = value;
167   - if (value & AT91_US_TXEN)
168   - sam9->dbgu_regs[AT91_DBGU_SR] |= AT91_US_TXRDY | AT91_US_TXEMPTY;
169   - if (value & AT91_US_TXDIS)
170   - sam9->dbgu_regs[AT91_DBGU_SR] &= ~(AT91_US_TXRDY | AT91_US_TXEMPTY);
171   - break;
172   - case AT91_DBGU_IER:
173   - sam9->dbgu_regs[AT91_DBGU_IMR] |= value;
174   - at91_dbgu_state_changed(sam9);
175   - break;
176   - case AT91_DBGU_IDR:
177   - sam9->dbgu_regs[AT91_DBGU_IMR] &= ~value;
178   - break;
179   - case AT91_DBGU_THR:
180   - sam9->dbgu_regs[AT91_DBGU_THR] = value;
181   - sam9->dbgu_regs[AT91_DBGU_SR] &= ~(AT91_US_TXEMPTY | AT91_US_TXRDY);
182   - ch = value;
183   - if (sam9->dbgu.chr)
184   - qemu_chr_write(sam9->dbgu.chr, &ch, 1);
185   -// qemu_mod_timer(sam9->dbgu_tr_timer , qemu_get_clock(vm_clock) + sam9->char_transmit_time);
186   - dbgu_serial_end_xmit(sam9);
187   - break;
188   - default:
189   - //DEBUG("unimplemented\n");
190   - break;
191   - }
192   -}
193   -
194   -static int at91_dbgu_can_receive(void *opaque)
195   -{
196   - struct at91sam9_state *sam9 = (struct at91sam9_state *)opaque;
197   -
198   - return (sam9->dbgu_regs[AT91_DBGU_SR] & AT91_US_RXRDY) == 0;
199   -}
200   -
201   -static void at91_dbgu_receive(void *opaque, const uint8_t *buf, int size)
202   -{
203   - struct at91sam9_state *sam9 = (struct at91sam9_state *)opaque;
204   - int i;
205   - /*! \todo if not one character we need wait before irq handled,
206   - but from other hand at91_dbgu_can_receive should prevent this
207   - */
208   - for (i = 0; i < size; ++i) {
209   - sam9->dbgu_regs[AT91_DBGU_RHR] = buf[i];
210   - sam9->dbgu_regs[AT91_DBGU_SR] |= AT91_US_RXRDY;
211   - at91_dbgu_state_changed(sam9);
212   - }
213   -}
214   -
215   -static void at91_dbgu_event(void *opaque, int event)
216   -{
217   - DEBUG("begin\n");
218   -}
219   -
220 75 static uint32_t at91_bus_matrix_read(void *opaque, target_phys_addr_t offset)
221 76 {
222 77 struct at91sam9_state *sam9 = (struct at91sam9_state *)opaque;
... ... @@ -244,38 +99,12 @@ static void at91_bus_matrix_write(void *opaque, target_phys_addr_t offset,
244 99 }
245 100 }
246 101  
247   -static void at91_init_pmc(struct at91sam9_state *sam9)
248   -{
249   - DEBUG("begin\n");
250   - sam9->pmc_regs[AT91_PMC_MCKR] = 0;
251   - sam9->pmc_regs[AT91_PMC_MOR] = 0;
252   - sam9->pmc_regs[AT91_PMC_SR] = 0x08;
253   - sam9->pmc_regs[AT91_PMC_PLLAR] = 0x3F00;
254   - sam9->pmc_regs[AT91_PMC_PLLBR] = 0x3F00;
255   -}
256   -
257 102 static void at91_init_bus_matrix(struct at91sam9_state *sam9)
258 103 {
259 104 DEBUG("begin\n");
260 105 memset(&sam9->bus_matrix_regs, 0, sizeof(sam9->bus_matrix_regs));
261 106 }
262 107  
263   -static void at91_init_dbgu(struct at91sam9_state *sam9, CharDriverState *chr)
264   -{
265   - DEBUG("begin\n");
266   -
267   - memset(&sam9->dbgu_regs, 0, sizeof(sam9->dbgu_regs));
268   - sam9->dbgu_regs[AT91_DBGU_SR] = AT91_US_TXEMPTY | AT91_US_TXRDY;
269   -
270   - sam9->dbgu.chr = chr;
271   - sam9->dbgu_tr_timer = qemu_new_timer(vm_clock, (QEMUTimerCB *)dbgu_serial_end_xmit, sam9);
272   -// sam9->char_transmit_time = (get_ticks_per_sec() / 115200) * 10;
273   - if (chr)
274   - qemu_chr_add_handlers(chr, at91_dbgu_can_receive,
275   - at91_dbgu_receive,
276   - at91_dbgu_event, sam9);
277   -}
278   -
279 108 static uint32_t at91_ccfg_read(void *opaque, target_phys_addr_t offset)
280 109 {
281 110 struct at91sam9_state *sam9 = (struct at91sam9_state *)opaque;
... ... @@ -293,23 +122,6 @@ static void at91_ccfg_write(void *opaque, target_phys_addr_t offset,
293 122 sam9->ccfg_regs[offset / sizeof(sam9->ccfg_regs[0])] = value;
294 123 }
295 124  
296   -static uint32_t at91_pio_read(void *opaque, target_phys_addr_t offset)
297   -{
298   - struct at91sam9_state *sam9 = (struct at91sam9_state *)opaque;
299   -
300   - TRACE("pio read offset %X\n", offset);
301   - return sam9->pio_regs[offset / sizeof(sam9->pio_regs[0])];
302   -}
303   -
304   -static void at91_pio_write(void *opaque, target_phys_addr_t offset,
305   - uint32_t value)
306   -{
307   - struct at91sam9_state *sam9 = (struct at91sam9_state *)opaque;
308   -
309   - TRACE("pio write offset %X, value %X\n", offset, value);
310   - sam9->pio_regs[offset / sizeof(sam9->pio_regs[0])] = value;
311   -}
312   -
313 125 static uint32_t at91_sdramc0_read(void *opaque, target_phys_addr_t offset)
314 126 {
315 127 struct at91sam9_state *sam9 = (struct at91sam9_state *)opaque;
... ... @@ -344,155 +156,6 @@ static void at91_smc0_write(void *opaque, target_phys_addr_t offset,
344 156 sam9->smc0_regs[offset / sizeof(sam9->smc0_regs[0])] = value;
345 157 }
346 158  
347   -static void at91_pitc_timer_tick(void * opaque)
348   -{
349   - struct at91sam9_state *sam9 = (struct at91sam9_state *)opaque;
350   - uint64_t val = ptimer_get_count(sam9->pitc_timer);
351   -
352   - unsigned int tick = (sam9->pitc_regs[AT91_PITC_PIIR] >> 20) + 1;
353   - sam9->pitc_regs[AT91_PITC_PIIR] = (val & ((1 << 21) - 1)) | (tick << 20);
354   - sam9->pitc_regs[AT91_PITC_PIVR] = sam9->pitc_regs[AT91_PITC_PIIR];
355   -
356   - if ((sam9->pitc_regs[AT91_PITC_MR] & AT91_PTIC_MR_PITIEN) &&
357   - (sam9->aic_regs[AT91_AIC_IECR] & (1 << AT91_PERIPH_SYS_ID)) &&
358   - !sam9->pitc_regs[AT91_PITC_SR]) {
359   - sam9->aic_regs[AT91_AIC_ISR] = AT91_PERIPH_SYS_ID;
360   - sam9->aic_regs[AT91_AIC_IVR] = sam9->aic_regs[AT91_AIC_SVR0 + AT91_PERIPH_SYS_ID];
361   -
362   - sam9->pitc_regs[AT91_PITC_SR] = 1;
363   - qemu_irq_raise(sam9->qirq[0]);
364   - }
365   -}
366   -
367   -static uint32_t at91_pitc_read(void *opaque, target_phys_addr_t offset)
368   -{
369   - struct at91sam9_state *sam9 = (struct at91sam9_state *)opaque;
370   - int pitc_enable = !!(sam9->pitc_regs[AT91_PITC_MR] & AT91_PTIC_MR_PITEN);
371   - int idx;
372   -
373   - idx = offset / sizeof(sam9->pitc_regs[0]);
374   - switch (idx) {
375   - case AT91_PITC_SR:
376   -// DEBUG("read sr: %X\n", sam9->pitc_regs[idx]);
377   - break;
378   - case AT91_PITC_PIVR:
379   - if (pitc_enable) {
380   -// DEBUG("clear sr\n");
381   - sam9->pitc_regs[AT91_PITC_SR] = 0;
382   - } else {
383   -// DEBUG("pitc disabled\n");
384   - break;
385   - }
386   - case AT91_PITC_PIIR:
387   - if (pitc_enable) {
388   - uint64_t val = ptimer_get_count(sam9->pitc_timer);
389   - unsigned int tick = (sam9->pitc_regs[AT91_PITC_PIIR] >> 20);
390   - uint32_t res = (tick << 20) | (val & ((1 << 21) - 1));
391   -
392   - if (idx == AT91_PITC_PIVR)
393   - tick = 0;
394   - sam9->pitc_regs[AT91_PITC_PIIR] = (tick << 20) | (val & ((1 << 21) - 1));
395   - sam9->pitc_regs[AT91_PITC_PIVR] = sam9->pitc_regs[AT91_PITC_PIIR];
396   - TRACE("pitc read offset %X, value %X\n", offset, res);
397   - return res;
398   - } else {
399   -// DEBUG("pitc disabled\n");
400   - break;
401   - }
402   -
403   - default:
404   - /*nothing*/break;
405   - }
406   - TRACE("pitc read offset %X, value %X\n", offset, sam9->pitc_regs[idx]);
407   -
408   - return sam9->pitc_regs[idx];
409   -}
410   -
411   -static void at91_pitc_write(void *opaque, target_phys_addr_t offset,
412   - uint32_t value)
413   -{
414   - struct at91sam9_state *sam9 = (struct at91sam9_state *)opaque;
415   -
416   - TRACE("pitc write offset %X, value %X\n", offset, value);
417   - int idx = offset / sizeof(sam9->pitc_regs[0]);
418   - switch (idx) {
419   - case AT91_PITC_MR: {
420   - int pitc_enable = !!(value & AT91_PTIC_MR_PITEN);
421   - unsigned int period = value & 0xFFFFF;
422   -
423   - //DEBUG("set period %u, int enabled? %d\n", period, !!(value & AT91_PTIC_MR_PITIEN));
424   -
425   - if (pitc_enable && period != 0) {
426   - sam9->timer_active = 1;
427   - //! \todo get real value from PLL
428   - ptimer_set_freq(sam9->pitc_timer, (100 * 1000 * 1000) / 16);
429   - ptimer_set_limit(sam9->pitc_timer, period, 1);
430   - ptimer_run(sam9->pitc_timer, 0);
431   - } else if (sam9->timer_active) {
432   - TRACE("disable timer\n");
433   - sam9->pitc_regs[AT91_PITC_PIVR] = 0;
434   - ptimer_stop(sam9->pitc_timer);
435   - }
436   - }
437   - break;
438   - default:
439   - TRACE("unhandled register %d\n", idx);
440   - break;
441   - }
442   - sam9->pitc_regs[idx] = value;
443   -}
444   -
445   -static void at91_init_pitc(struct at91sam9_state *sam9)
446   -{
447   - QEMUBH *bh;
448   -
449   - DEBUG("begin\n");
450   - memset(&sam9->pitc_regs, 0, sizeof(sam9->pitc_regs));
451   - sam9->pitc_regs[AT91_PITC_MR] = 0xFFFFF;
452   - bh = qemu_bh_new(at91_pitc_timer_tick, sam9);
453   - sam9->pitc_timer = ptimer_init(bh);
454   -}
455   -
456   -static uint32_t at91_aic_read(void *opaque, target_phys_addr_t offset)
457   -{
458   - struct at91sam9_state *sam9 = (struct at91sam9_state *)opaque;
459   - unsigned int idx = offset / sizeof(sam9->aic_regs[0]);
460   - if (idx == AT91_AIC_IVR) {
461   - qemu_irq_lower(sam9->qirq[0]);
462   - } else if (idx == AT91_AIC_ISR) {
463   - uint32_t val = sam9->aic_regs[idx];
464   - sam9->aic_regs[idx] = 0;
465   - return val;
466   - }
467   -
468   - return sam9->aic_regs[idx];
469   -}
470   -
471   -static void at91_aic_write(void *opaque, target_phys_addr_t offset,
472   - uint32_t value)
473   -{
474   - struct at91sam9_state *sam9 = (struct at91sam9_state *)opaque;
475   - unsigned int idx = offset / sizeof(sam9->aic_regs[0]);
476   -
477   - switch (idx) {
478   - case AT91_AIC_IECR:
479   - sam9->aic_regs[idx] |= value;
480   - break;
481   - case AT91_AIC_IDCR:
482   - sam9->aic_regs[idx] |= value;
483   - sam9->aic_regs[AT91_AIC_IECR] &= ~value;
484   - break;
485   - case AT91_AIC_IVR://ignore write
486   - break;
487   - case AT91_AIC_EOICR:
488   -// DEBUG("we write to end of interrupt reg\n");
489   - break;
490   - default:
491   - sam9->aic_regs[idx] = value;
492   - break;
493   - }
494   -}
495   -
496 159 static uint32_t at91_usart_read(void *opaque, target_phys_addr_t offset)
497 160 {
498 161 struct at91sam9_state *sam9 = (struct at91sam9_state *)opaque;
... ... @@ -522,11 +185,6 @@ static struct ip_block ip_blocks[] = {
522 185 {AT91_SMC0_BASE - AT91_PERIPH_BASE, AT91_ECC1_BASE - AT91_PERIPH_BASE, at91_smc0_read, at91_smc0_write},
523 186 {AT91_BUS_MATRIX_BASE - AT91_PERIPH_BASE, AT91_CCFG_BASE - AT91_PERIPH_BASE, at91_bus_matrix_read, at91_bus_matrix_write},
524 187 {AT91_CCFG_BASE - AT91_PERIPH_BASE, AT91_DBGU_BASE - AT91_PERIPH_BASE, at91_ccfg_read, at91_ccfg_write},
525   - {AT91_DBGU_BASE - AT91_PERIPH_BASE, AT91_AIC_BASE - AT91_PERIPH_BASE, at91_dbgu_read, at91_dbgu_write},
526   - {AT91_AIC_BASE - AT91_PERIPH_BASE, AT91_PIO_BASE - AT91_PERIPH_BASE, at91_aic_read, at91_aic_write},
527   - {AT91_PIO_BASE - AT91_PERIPH_BASE, AT91_PMC_BASE - AT91_PERIPH_BASE, at91_pio_read, at91_pio_write},
528   - {AT91_PMC_BASE - AT91_PERIPH_BASE, AT91_RSTC_BASE - AT91_PERIPH_BASE, at91_pmc_read, at91_pmc_write},
529   - {AT91_PITC_BASE - AT91_PERIPH_BASE, AT91_WDT_BASE - AT91_PERIPH_BASE, at91_pitc_read, at91_pitc_write},
530 188 };
531 189  
532 190 static uint32_t at91_periph_read(void *opaque, target_phys_addr_t offset)
... ... @@ -553,34 +211,6 @@ static void at91_periph_write(void *opaque, target_phys_addr_t offset,
553 211 DEBUG("write to unsupported periph: addr %X, val %X\n", offset, value);
554 212 }
555 213  
556   -/* Input 0 is IRQ and input 1 is FIQ. */
557   -static void arm_aic_cpu_handler(void *opaque, int irq, int level)
558   -{
559   - CPUState *env = (CPUState *)opaque;
560   - switch (irq) {
561   - case ARM_AIC_CPU_IRQ:
562   - if (level)
563   - cpu_interrupt(env, CPU_INTERRUPT_HARD);
564   - else
565   - cpu_reset_interrupt(env, CPU_INTERRUPT_HARD);
566   - break;
567   - case ARM_AIC_CPU_FIQ:
568   - if (level)
569   - cpu_interrupt(env, CPU_INTERRUPT_FIQ);
570   - else
571   - cpu_reset_interrupt(env, CPU_INTERRUPT_FIQ);
572   - break;
573   - default:
574   - hw_error("arm_pic_cpu_handler: Bad interrput line %d\n", irq);
575   - }
576   -}
577   -
578   -static void at91_aic_init(struct at91sam9_state *sam9)
579   -{
580   - memset(&sam9->aic_regs[0], 0, sizeof(sam9->aic_regs));
581   - sam9->qirq = qemu_allocate_irqs(arm_aic_cpu_handler, sam9->env, 2);
582   -}
583   -
584 214 static CPUReadMemoryFunc *at91_periph_readfn[] = {
585 215 at91_periph_read,
586 216 at91_periph_read,
... ... @@ -605,6 +235,13 @@ static void at91sam9_init(ram_addr_t ram_size,
605 235 DriveInfo *dinfo;
606 236 struct at91sam9_state *sam9;
607 237 int iomemtype;
  238 + qemu_irq *cpu_pic;
  239 + qemu_irq pic[32];
  240 + qemu_irq pic1[32];
  241 + DeviceState *dev;
  242 + DeviceState *pit;
  243 + DeviceState *pmc;
  244 + int i;
608 245  
609 246 DEBUG("begin, ram_size %llu\n", (unsigned long long)ram_size);
610 247 #ifdef TRACE_ON
... ... @@ -635,17 +272,46 @@ static void at91sam9_init(ram_addr_t ram_size,
635 272 iomemtype = cpu_register_io_memory(at91_periph_readfn, at91_periph_writefn, sam9);
636 273 cpu_register_physical_memory(0xF0000000, 0xFFFFFFFF - 0xF0000000, iomemtype);
637 274  
638   - at91_init_pmc(sam9);
  275 + cpu_pic = arm_pic_init_cpu(env);
  276 + dev = sysbus_create_varargs("at91,aic", AT91_AIC_BASE,
  277 + cpu_pic[ARM_PIC_CPU_IRQ],
  278 + cpu_pic[ARM_PIC_CPU_FIQ],
  279 + NULL);
  280 +
  281 + for (i = 0; i < 32; i++) {
  282 + pic[i] = qdev_get_gpio_in(dev, i);
  283 + }
  284 +
  285 + dev = sysbus_create_simple("at91,intor", -1, pic[1]);
  286 + for (i = 0; i < 32; i++) {
  287 + pic1[i] = qdev_get_gpio_in(dev, i);
  288 + }
  289 + sysbus_create_simple("at91,dbgu", AT91_DBGU_BASE, pic1[0]);
  290 + pmc = sysbus_create_simple("at91,pmc", AT91_PMC_BASE, pic1[1]);
  291 + qdev_prop_set_uint32(pmc, "mo_freq", 16000000);
  292 + pit = sysbus_create_simple("at91,pit", AT91_PITC_BASE, pic1[3]);
  293 + sysbus_create_varargs("at91,tc", AT91_TC012_BASE, pic[19], pic[19], pic[19], NULL);
  294 +
639 295 at91_init_bus_matrix(sam9);
640 296 memset(&sam9->ccfg_regs, 0, sizeof(sam9->ccfg_regs));
641   - memset(&sam9->pio_regs, 0, sizeof(sam9->pio_regs));
  297 + sysbus_create_simple("at91,pio", AT91_PIOA_BASE, pic[2]);
  298 + sysbus_create_simple("at91,pio", AT91_PIOB_BASE, pic[3]);
  299 + sysbus_create_simple("at91,pio", AT91_PIOC_BASE, pic[4]);
  300 + sysbus_create_simple("at91,pio", AT91_PIOD_BASE, pic[4]);
  301 + sysbus_create_simple("at91,pio", AT91_PIOE_BASE, pic[4]);
  302 + sysbus_create_varargs("at91,rstc", AT91_RSTC_BASE, NULL);
642 303 memset(&sam9->sdramc0_regs, 0, sizeof(sam9->sdramc0_regs));
643 304 memset(&sam9->smc0_regs, 0, sizeof(sam9->smc0_regs));
644   - at91_init_dbgu(sam9, serial_hds[0]);
645   - at91_init_pitc(sam9);
646   - at91_aic_init(sam9);
647 305 memset(sam9->usart0_regs, 0, sizeof(sam9->usart0_regs));
648 306  
  307 + qemu_check_nic_model(&nd_table[0], "at91");
  308 + dev = qdev_create(NULL, "at91,emac");
  309 + dev->nd = &nd_table[0];
  310 + qdev_init(dev);
  311 + sysbus_mmio_map(sysbus_from_qdev(dev), 0, AT91_EMAC_BASE);
  312 + sysbus_connect_irq(sysbus_from_qdev(dev), 0, pic[21]);
  313 +
  314 +
649 315 /*
650 316 we use variant of booting from external memory (NOR FLASH),
651 317 it mapped to 0x0 at start, and also it is accessable from 0x10000000 address
... ...
hw/at91sam9263_defs.h
  View file @69efbf1
... ... @@ -3,7 +3,9 @@
3 3  
4 4 /* base periph addresses */
5 5 #define AT91_PERIPH_BASE 0xF0000000
  6 +#define AT91_TC012_BASE 0xFFF7C000
6 7 #define AT91_USART0_BASE 0xFFF8C000
  8 +#define AT91_EMAC_BASE 0xFFFBC000
7 9 #define AT91_SDRAMC0_BASE 0xFFFFE200
8 10 #define AT91_SMC0_BASE 0xFFFFE400
9 11 #define AT91_ECC1_BASE 0xFFFFE600
... ... @@ -11,7 +13,11 @@
11 13 #define AT91_CCFG_BASE 0xFFFFED10
12 14 #define AT91_DBGU_BASE 0xFFFFEE00
13 15 #define AT91_AIC_BASE 0xFFFFF000
14   -#define AT91_PIO_BASE 0xFFFFF200
  16 +#define AT91_PIOA_BASE 0xFFFFF200
  17 +#define AT91_PIOB_BASE 0xFFFFF400
  18 +#define AT91_PIOC_BASE 0xFFFFF600
  19 +#define AT91_PIOD_BASE 0xFFFFF800
  20 +#define AT91_PIOE_BASE 0xFFFFFA00
15 21 #define AT91_PMC_BASE 0xFFFFFC00
16 22 #define AT91_RSTC_BASE 0xFFFFFD00
17 23 #define AT91_PITC_BASE 0xFFFFFD30
... ...