Commit 69d6275b0058cf7a8ccba83f74e36b973b951d22
1 parent
c047da1a
SH4: Convert remaining non-fp ops to TCG
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net> git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5120 c046a42c-6fe2-441c-8c8c-71466251a162
Showing
5 changed files
with
130 additions
and
153 deletions
target-sh4/exec.h
@@ -71,10 +71,6 @@ int find_itlb_entry(CPUState * env, target_ulong address, | @@ -71,10 +71,6 @@ int find_itlb_entry(CPUState * env, target_ulong address, | ||
71 | int use_asid, int update); | 71 | int use_asid, int update); |
72 | int find_utlb_entry(CPUState * env, target_ulong address, int use_asid); | 72 | int find_utlb_entry(CPUState * env, target_ulong address, int use_asid); |
73 | 73 | ||
74 | -void helper_div1_T0_T1(void); | ||
75 | -void helper_rotcl(uint32_t * addr); | ||
76 | -void helper_rotcr(uint32_t * addr); | ||
77 | - | ||
78 | void do_interrupt(CPUState * env); | 74 | void do_interrupt(CPUState * env); |
79 | 75 | ||
80 | void cpu_loop_exit(void); | 76 | void cpu_loop_exit(void); |
target-sh4/helper.h
@@ -14,6 +14,7 @@ DEF_HELPER(uint32_t, helper_addc, (uint32_t, uint32_t)) | @@ -14,6 +14,7 @@ DEF_HELPER(uint32_t, helper_addc, (uint32_t, uint32_t)) | ||
14 | DEF_HELPER(uint32_t, helper_subv, (uint32_t, uint32_t)) | 14 | DEF_HELPER(uint32_t, helper_subv, (uint32_t, uint32_t)) |
15 | DEF_HELPER(uint32_t, helper_subc, (uint32_t, uint32_t)) | 15 | DEF_HELPER(uint32_t, helper_subc, (uint32_t, uint32_t)) |
16 | DEF_HELPER(uint32_t, helper_negc, (uint32_t)) | 16 | DEF_HELPER(uint32_t, helper_negc, (uint32_t)) |
17 | +DEF_HELPER(uint32_t, helper_div1, (uint32_t, uint32_t)) | ||
17 | DEF_HELPER(void, helper_macl, (uint32_t, uint32_t)) | 18 | DEF_HELPER(void, helper_macl, (uint32_t, uint32_t)) |
18 | DEF_HELPER(void, helper_macw, (uint32_t, uint32_t)) | 19 | DEF_HELPER(void, helper_macw, (uint32_t, uint32_t)) |
19 | 20 |
target-sh4/op.c
@@ -37,84 +37,6 @@ static inline void cond_t(int cond) | @@ -37,84 +37,6 @@ static inline void cond_t(int cond) | ||
37 | clr_t(); | 37 | clr_t(); |
38 | } | 38 | } |
39 | 39 | ||
40 | -void OPPROTO op_cmp_str_T0_T1(void) | ||
41 | -{ | ||
42 | - cond_t((T0 & 0x000000ff) == (T1 & 0x000000ff) || | ||
43 | - (T0 & 0x0000ff00) == (T1 & 0x0000ff00) || | ||
44 | - (T0 & 0x00ff0000) == (T1 & 0x00ff0000) || | ||
45 | - (T0 & 0xff000000) == (T1 & 0xff000000)); | ||
46 | - RETURN(); | ||
47 | -} | ||
48 | - | ||
49 | -void OPPROTO op_div0s_T0_T1(void) | ||
50 | -{ | ||
51 | - if (T1 & 0x80000000) | ||
52 | - env->sr |= SR_Q; | ||
53 | - else | ||
54 | - env->sr &= ~SR_Q; | ||
55 | - if (T0 & 0x80000000) | ||
56 | - env->sr |= SR_M; | ||
57 | - else | ||
58 | - env->sr &= ~SR_M; | ||
59 | - cond_t((T1 ^ T0) & 0x80000000); | ||
60 | - RETURN(); | ||
61 | -} | ||
62 | - | ||
63 | -void OPPROTO op_div1_T0_T1(void) | ||
64 | -{ | ||
65 | - helper_div1_T0_T1(); | ||
66 | - RETURN(); | ||
67 | -} | ||
68 | - | ||
69 | -void OPPROTO op_shad_T0_T1(void) | ||
70 | -{ | ||
71 | - if ((T0 & 0x80000000) == 0) | ||
72 | - T1 <<= (T0 & 0x1f); | ||
73 | - else if ((T0 & 0x1f) == 0) | ||
74 | - T1 = (T1 & 0x80000000)? 0xffffffff : 0; | ||
75 | - else | ||
76 | - T1 = ((int32_t) T1) >> ((~T0 & 0x1f) + 1); | ||
77 | - RETURN(); | ||
78 | -} | ||
79 | - | ||
80 | -void OPPROTO op_shld_T0_T1(void) | ||
81 | -{ | ||
82 | - if ((T0 & 0x80000000) == 0) | ||
83 | - T1 <<= (T0 & 0x1f); | ||
84 | - else if ((T0 & 0x1f) == 0) | ||
85 | - T1 = 0; | ||
86 | - else | ||
87 | - T1 = ((uint32_t) T1) >> ((~T0 & 0x1f) + 1); | ||
88 | - RETURN(); | ||
89 | -} | ||
90 | - | ||
91 | -void OPPROTO op_rotcl_Rn(void) | ||
92 | -{ | ||
93 | - helper_rotcl(&env->gregs[PARAM1]); | ||
94 | - RETURN(); | ||
95 | -} | ||
96 | - | ||
97 | -void OPPROTO op_rotcr_Rn(void) | ||
98 | -{ | ||
99 | - helper_rotcr(&env->gregs[PARAM1]); | ||
100 | - RETURN(); | ||
101 | -} | ||
102 | - | ||
103 | -void OPPROTO op_rotl_Rn(void) | ||
104 | -{ | ||
105 | - cond_t(env->gregs[PARAM1] & 0x80000000); | ||
106 | - env->gregs[PARAM1] = (env->gregs[PARAM1] << 1) | (env->sr & SR_T); | ||
107 | - RETURN(); | ||
108 | -} | ||
109 | - | ||
110 | -void OPPROTO op_rotr_Rn(void) | ||
111 | -{ | ||
112 | - cond_t(env->gregs[PARAM1] & 1); | ||
113 | - env->gregs[PARAM1] = (env->gregs[PARAM1] >> 1) | | ||
114 | - ((env->sr & SR_T) ? 0x80000000 : 0); | ||
115 | - RETURN(); | ||
116 | -} | ||
117 | - | ||
118 | void OPPROTO op_fmov_frN_FT0(void) | 40 | void OPPROTO op_fmov_frN_FT0(void) |
119 | { | 41 | { |
120 | FT0 = env->fregs[PARAM1]; | 42 | FT0 = env->fregs[PARAM1]; |
target-sh4/op_helper.c
@@ -163,27 +163,27 @@ uint32_t helper_addv(uint32_t arg0, uint32_t arg1) | @@ -163,27 +163,27 @@ uint32_t helper_addv(uint32_t arg0, uint32_t arg1) | ||
163 | #define SETM env->sr |= SR_M | 163 | #define SETM env->sr |= SR_M |
164 | #define CLRM env->sr &= ~SR_M | 164 | #define CLRM env->sr &= ~SR_M |
165 | 165 | ||
166 | -void helper_div1_T0_T1(void) | 166 | +uint32_t helper_div1(uint32_t arg0, uint32_t arg1) |
167 | { | 167 | { |
168 | uint32_t tmp0, tmp2; | 168 | uint32_t tmp0, tmp2; |
169 | uint8_t old_q, tmp1 = 0xff; | 169 | uint8_t old_q, tmp1 = 0xff; |
170 | 170 | ||
171 | - //printf("div1 T0=0x%08x T1=0x%08x M=%d Q=%d T=%d\n", T0, T1, M, Q, T); | 171 | + //printf("div1 arg0=0x%08x arg1=0x%08x M=%d Q=%d T=%d\n", arg0, arg1, M, Q, T); |
172 | old_q = Q; | 172 | old_q = Q; |
173 | - if ((0x80000000 & T1) != 0) | 173 | + if ((0x80000000 & arg1) != 0) |
174 | SETQ; | 174 | SETQ; |
175 | else | 175 | else |
176 | CLRQ; | 176 | CLRQ; |
177 | - tmp2 = T0; | ||
178 | - T1 <<= 1; | ||
179 | - T1 |= T; | 177 | + tmp2 = arg0; |
178 | + arg1 <<= 1; | ||
179 | + arg1 |= T; | ||
180 | switch (old_q) { | 180 | switch (old_q) { |
181 | case 0: | 181 | case 0: |
182 | switch (M) { | 182 | switch (M) { |
183 | case 0: | 183 | case 0: |
184 | - tmp0 = T1; | ||
185 | - T1 -= tmp2; | ||
186 | - tmp1 = T1 > tmp0; | 184 | + tmp0 = arg1; |
185 | + arg1 -= tmp2; | ||
186 | + tmp1 = arg1 > tmp0; | ||
187 | switch (Q) { | 187 | switch (Q) { |
188 | case 0: | 188 | case 0: |
189 | if (tmp1) | 189 | if (tmp1) |
@@ -200,9 +200,9 @@ void helper_div1_T0_T1(void) | @@ -200,9 +200,9 @@ void helper_div1_T0_T1(void) | ||
200 | } | 200 | } |
201 | break; | 201 | break; |
202 | case 1: | 202 | case 1: |
203 | - tmp0 = T1; | ||
204 | - T1 += tmp2; | ||
205 | - tmp1 = T1 < tmp0; | 203 | + tmp0 = arg1; |
204 | + arg1 += tmp2; | ||
205 | + tmp1 = arg1 < tmp0; | ||
206 | switch (Q) { | 206 | switch (Q) { |
207 | case 0: | 207 | case 0: |
208 | if (tmp1 == 0) | 208 | if (tmp1 == 0) |
@@ -223,9 +223,9 @@ void helper_div1_T0_T1(void) | @@ -223,9 +223,9 @@ void helper_div1_T0_T1(void) | ||
223 | case 1: | 223 | case 1: |
224 | switch (M) { | 224 | switch (M) { |
225 | case 0: | 225 | case 0: |
226 | - tmp0 = T1; | ||
227 | - T1 += tmp2; | ||
228 | - tmp1 = T1 < tmp0; | 226 | + tmp0 = arg1; |
227 | + arg1 += tmp2; | ||
228 | + tmp1 = arg1 < tmp0; | ||
229 | switch (Q) { | 229 | switch (Q) { |
230 | case 0: | 230 | case 0: |
231 | if (tmp1) | 231 | if (tmp1) |
@@ -242,9 +242,9 @@ void helper_div1_T0_T1(void) | @@ -242,9 +242,9 @@ void helper_div1_T0_T1(void) | ||
242 | } | 242 | } |
243 | break; | 243 | break; |
244 | case 1: | 244 | case 1: |
245 | - tmp0 = T1; | ||
246 | - T1 -= tmp2; | ||
247 | - tmp1 = T1 > tmp0; | 245 | + tmp0 = arg1; |
246 | + arg1 -= tmp2; | ||
247 | + tmp1 = arg1 > tmp0; | ||
248 | switch (Q) { | 248 | switch (Q) { |
249 | case 0: | 249 | case 0: |
250 | if (tmp1 == 0) | 250 | if (tmp1 == 0) |
@@ -267,7 +267,8 @@ void helper_div1_T0_T1(void) | @@ -267,7 +267,8 @@ void helper_div1_T0_T1(void) | ||
267 | SETT; | 267 | SETT; |
268 | else | 268 | else |
269 | CLRT; | 269 | CLRT; |
270 | - //printf("Output: T1=0x%08x M=%d Q=%d T=%d\n", T1, M, Q, T); | 270 | + //printf("Output: arg1=0x%08x M=%d Q=%d T=%d\n", arg1, M, Q, T); |
271 | + return arg1; | ||
271 | } | 272 | } |
272 | 273 | ||
273 | void helper_macl(uint32_t arg0, uint32_t arg1) | 274 | void helper_macl(uint32_t arg0, uint32_t arg1) |
@@ -365,30 +366,6 @@ uint32_t helper_subv(uint32_t arg0, uint32_t arg1) | @@ -365,30 +366,6 @@ uint32_t helper_subv(uint32_t arg0, uint32_t arg1) | ||
365 | return arg1; | 366 | return arg1; |
366 | } | 367 | } |
367 | 368 | ||
368 | -void helper_rotcl(uint32_t * addr) | ||
369 | -{ | ||
370 | - uint32_t new; | ||
371 | - | ||
372 | - new = (*addr << 1) | (env->sr & SR_T); | ||
373 | - if (*addr & 0x80000000) | ||
374 | - env->sr |= SR_T; | ||
375 | - else | ||
376 | - env->sr &= ~SR_T; | ||
377 | - *addr = new; | ||
378 | -} | ||
379 | - | ||
380 | -void helper_rotcr(uint32_t * addr) | ||
381 | -{ | ||
382 | - uint32_t new; | ||
383 | - | ||
384 | - new = (*addr >> 1) | ((env->sr & SR_T) ? 0x80000000 : 0); | ||
385 | - if (*addr & 1) | ||
386 | - env->sr |= SR_T; | ||
387 | - else | ||
388 | - env->sr &= ~SR_T; | ||
389 | - *addr = new; | ||
390 | -} | ||
391 | - | ||
392 | void helper_ld_fpscr(uint32_t val) | 369 | void helper_ld_fpscr(uint32_t val) |
393 | { | 370 | { |
394 | env->fpscr = val & 0x003fffff; | 371 | env->fpscr = val & 0x003fffff; |
target-sh4/translate.c
@@ -337,6 +337,24 @@ static inline void gen_store_flags(uint32_t flags) | @@ -337,6 +337,24 @@ static inline void gen_store_flags(uint32_t flags) | ||
337 | tcg_gen_ori_i32(cpu_flags, cpu_flags, flags); | 337 | tcg_gen_ori_i32(cpu_flags, cpu_flags, flags); |
338 | } | 338 | } |
339 | 339 | ||
340 | +static inline void gen_copy_bit_i32(TCGv t0, int p0, TCGv t1, int p1) | ||
341 | +{ | ||
342 | + TCGv tmp = tcg_temp_new(TCG_TYPE_I32); | ||
343 | + | ||
344 | + p0 &= 0x1f; | ||
345 | + p1 &= 0x1f; | ||
346 | + | ||
347 | + tcg_gen_andi_i32(tmp, t1, (1 << p1)); | ||
348 | + tcg_gen_andi_i32(t0, t0, ~(1 << p0)); | ||
349 | + if (p0 < p1) | ||
350 | + tcg_gen_shri_i32(tmp, tmp, p1 - p0); | ||
351 | + else if (p0 > p1) | ||
352 | + tcg_gen_shli_i32(tmp, tmp, p0 - p1); | ||
353 | + tcg_gen_or_i32(t0, t0, tmp); | ||
354 | + | ||
355 | + tcg_temp_free(tmp); | ||
356 | +} | ||
357 | + | ||
340 | #define B3_0 (ctx->opcode & 0xf) | 358 | #define B3_0 (ctx->opcode & 0xf) |
341 | #define B6_4 ((ctx->opcode >> 4) & 0x7) | 359 | #define B6_4 ((ctx->opcode >> 4) & 0x7) |
342 | #define B7_4 ((ctx->opcode >> 4) & 0xf) | 360 | #define B7_4 ((ctx->opcode >> 4) & 0xf) |
@@ -643,20 +661,33 @@ void _decode_opc(DisasContext * ctx) | @@ -643,20 +661,33 @@ void _decode_opc(DisasContext * ctx) | ||
643 | gen_cmp(TCG_COND_GEU, cpu_T[0], cpu_T[1]); | 661 | gen_cmp(TCG_COND_GEU, cpu_T[0], cpu_T[1]); |
644 | return; | 662 | return; |
645 | case 0x200c: /* cmp/str Rm,Rn */ | 663 | case 0x200c: /* cmp/str Rm,Rn */ |
646 | - tcg_gen_mov_i32(cpu_T[0], cpu_gregs[REG(B7_4)]); | ||
647 | - tcg_gen_mov_i32(cpu_T[1], cpu_gregs[REG(B11_8)]); | ||
648 | - gen_op_cmp_str_T0_T1(); | 664 | + { |
665 | + int label1 = gen_new_label(); | ||
666 | + int label2 = gen_new_label(); | ||
667 | + tcg_gen_xor_i32(cpu_T[0], cpu_gregs[REG(B7_4)], cpu_gregs[REG(B11_8)]); | ||
668 | + tcg_gen_andi_i32(cpu_T[0], cpu_T[0], 0xff000000); | ||
669 | + tcg_gen_brcondi_i32(TCG_COND_EQ, cpu_T[0], 0, label1); | ||
670 | + tcg_gen_andi_i32(cpu_T[0], cpu_T[0], 0x00ff0000); | ||
671 | + tcg_gen_brcondi_i32(TCG_COND_EQ, cpu_T[0], 0, label1); | ||
672 | + tcg_gen_andi_i32(cpu_T[0], cpu_T[0], 0x0000ff00); | ||
673 | + tcg_gen_brcondi_i32(TCG_COND_EQ, cpu_T[0], 0, label1); | ||
674 | + tcg_gen_andi_i32(cpu_T[0], cpu_T[0], 0x000000ff); | ||
675 | + tcg_gen_brcondi_i32(TCG_COND_EQ, cpu_T[0], 0, label1); | ||
676 | + tcg_gen_andi_i32(cpu_sr, cpu_sr, ~SR_T); | ||
677 | + tcg_gen_br(label2); | ||
678 | + gen_set_label(label1); | ||
679 | + tcg_gen_ori_i32(cpu_sr, cpu_sr, SR_T); | ||
680 | + gen_set_label(label2); | ||
681 | + } | ||
649 | return; | 682 | return; |
650 | case 0x2007: /* div0s Rm,Rn */ | 683 | case 0x2007: /* div0s Rm,Rn */ |
651 | - tcg_gen_mov_i32(cpu_T[0], cpu_gregs[REG(B7_4)]); | ||
652 | - tcg_gen_mov_i32(cpu_T[1], cpu_gregs[REG(B11_8)]); | ||
653 | - gen_op_div0s_T0_T1(); | 684 | + gen_copy_bit_i32(cpu_sr, 8, cpu_gregs[REG(B11_8)], 31); /* SR_Q */ |
685 | + gen_copy_bit_i32(cpu_sr, 9, cpu_gregs[REG(B7_4)], 31); /* SR_M */ | ||
686 | + tcg_gen_xor_i32(cpu_T[0], cpu_gregs[REG(B7_4)], cpu_gregs[REG(B11_8)]); | ||
687 | + gen_copy_bit_i32(cpu_sr, 0, cpu_T[0], 31); /* SR_T */ | ||
654 | return; | 688 | return; |
655 | case 0x3004: /* div1 Rm,Rn */ | 689 | case 0x3004: /* div1 Rm,Rn */ |
656 | - tcg_gen_mov_i32(cpu_T[0], cpu_gregs[REG(B7_4)]); | ||
657 | - tcg_gen_mov_i32(cpu_T[1], cpu_gregs[REG(B11_8)]); | ||
658 | - gen_op_div1_T0_T1(); | ||
659 | - tcg_gen_mov_i32(cpu_gregs[REG(B11_8)], cpu_T[1]); | 690 | + tcg_gen_helper_1_2(helper_div1, cpu_gregs[REG(B11_8)], cpu_gregs[REG(B7_4)], cpu_gregs[REG(B11_8)]); |
660 | return; | 691 | return; |
661 | case 0x300d: /* dmuls.l Rm,Rn */ | 692 | case 0x300d: /* dmuls.l Rm,Rn */ |
662 | { | 693 | { |
@@ -758,16 +789,59 @@ void _decode_opc(DisasContext * ctx) | @@ -758,16 +789,59 @@ void _decode_opc(DisasContext * ctx) | ||
758 | tcg_gen_or_i32(cpu_gregs[REG(B11_8)], cpu_gregs[REG(B11_8)], cpu_gregs[REG(B7_4)]); | 789 | tcg_gen_or_i32(cpu_gregs[REG(B11_8)], cpu_gregs[REG(B11_8)], cpu_gregs[REG(B7_4)]); |
759 | return; | 790 | return; |
760 | case 0x400c: /* shad Rm,Rn */ | 791 | case 0x400c: /* shad Rm,Rn */ |
761 | - tcg_gen_mov_i32(cpu_T[0], cpu_gregs[REG(B7_4)]); | ||
762 | - tcg_gen_mov_i32(cpu_T[1], cpu_gregs[REG(B11_8)]); | ||
763 | - gen_op_shad_T0_T1(); | ||
764 | - tcg_gen_mov_i32(cpu_gregs[REG(B11_8)], cpu_T[1]); | 792 | + { |
793 | + int label1 = gen_new_label(); | ||
794 | + int label2 = gen_new_label(); | ||
795 | + int label3 = gen_new_label(); | ||
796 | + int label4 = gen_new_label(); | ||
797 | + tcg_gen_brcondi_i32(TCG_COND_LT, cpu_gregs[REG(B7_4)], 0, label1); | ||
798 | + /* Rm positive, shift to the left */ | ||
799 | + tcg_gen_andi_i32(cpu_T[0], cpu_gregs[REG(B7_4)], 0x1f); | ||
800 | + tcg_gen_shl_i32(cpu_gregs[REG(B11_8)], cpu_gregs[REG(B11_8)], cpu_T[0]); | ||
801 | + tcg_gen_br(label4); | ||
802 | + /* Rm negative, shift to the right */ | ||
803 | + gen_set_label(label1); | ||
804 | + tcg_gen_andi_i32(cpu_T[0], cpu_gregs[REG(B7_4)], 0x1f); | ||
805 | + tcg_gen_brcondi_i32(TCG_COND_EQ, cpu_T[0], 0, label2); | ||
806 | + tcg_gen_not_i32(cpu_T[0], cpu_gregs[REG(B7_4)]); | ||
807 | + tcg_gen_andi_i32(cpu_T[0], cpu_T[0], 0x1f); | ||
808 | + tcg_gen_addi_i32(cpu_T[0], cpu_T[0], 1); | ||
809 | + tcg_gen_sar_i32(cpu_gregs[REG(B11_8)], cpu_gregs[REG(B11_8)], cpu_T[0]); | ||
810 | + tcg_gen_br(label4); | ||
811 | + /* Rm = -32 */ | ||
812 | + gen_set_label(label2); | ||
813 | + tcg_gen_brcondi_i32(TCG_COND_LT, cpu_gregs[REG(B11_8)], 0, label3); | ||
814 | + tcg_gen_movi_i32(cpu_gregs[REG(B11_8)], 0); | ||
815 | + tcg_gen_br(label4); | ||
816 | + gen_set_label(label3); | ||
817 | + tcg_gen_movi_i32(cpu_gregs[REG(B11_8)], 0xffffffff); | ||
818 | + gen_set_label(label4); | ||
819 | + } | ||
765 | return; | 820 | return; |
766 | case 0x400d: /* shld Rm,Rn */ | 821 | case 0x400d: /* shld Rm,Rn */ |
767 | - tcg_gen_mov_i32(cpu_T[0], cpu_gregs[REG(B7_4)]); | ||
768 | - tcg_gen_mov_i32(cpu_T[1], cpu_gregs[REG(B11_8)]); | ||
769 | - gen_op_shld_T0_T1(); | ||
770 | - tcg_gen_mov_i32(cpu_gregs[REG(B11_8)], cpu_T[1]); | 822 | + { |
823 | + int label1 = gen_new_label(); | ||
824 | + int label2 = gen_new_label(); | ||
825 | + int label3 = gen_new_label(); | ||
826 | + tcg_gen_brcondi_i32(TCG_COND_LT, cpu_gregs[REG(B7_4)], 0, label1); | ||
827 | + /* Rm positive, shift to the left */ | ||
828 | + tcg_gen_andi_i32(cpu_T[0], cpu_gregs[REG(B7_4)], 0x1f); | ||
829 | + tcg_gen_shl_i32(cpu_gregs[REG(B11_8)], cpu_gregs[REG(B11_8)], cpu_T[0]); | ||
830 | + tcg_gen_br(label3); | ||
831 | + /* Rm negative, shift to the right */ | ||
832 | + gen_set_label(label1); | ||
833 | + tcg_gen_andi_i32(cpu_T[0], cpu_gregs[REG(B7_4)], 0x1f); | ||
834 | + tcg_gen_brcondi_i32(TCG_COND_EQ, cpu_T[0], 0, label2); | ||
835 | + tcg_gen_not_i32(cpu_T[0], cpu_gregs[REG(B7_4)]); | ||
836 | + tcg_gen_andi_i32(cpu_T[0], cpu_T[0], 0x1f); | ||
837 | + tcg_gen_addi_i32(cpu_T[0], cpu_T[0], 1); | ||
838 | + tcg_gen_shr_i32(cpu_gregs[REG(B11_8)], cpu_gregs[REG(B11_8)], cpu_T[0]); | ||
839 | + tcg_gen_br(label3); | ||
840 | + /* Rm = -32 */ | ||
841 | + gen_set_label(label2); | ||
842 | + tcg_gen_movi_i32(cpu_gregs[REG(B11_8)], 0); | ||
843 | + gen_set_label(label3); | ||
844 | + } | ||
771 | return; | 845 | return; |
772 | case 0x3008: /* sub Rm,Rn */ | 846 | case 0x3008: /* sub Rm,Rn */ |
773 | tcg_gen_sub_i32(cpu_gregs[REG(B11_8)], cpu_gregs[REG(B11_8)], cpu_gregs[REG(B7_4)]); | 847 | tcg_gen_sub_i32(cpu_gregs[REG(B11_8)], cpu_gregs[REG(B11_8)], cpu_gregs[REG(B7_4)]); |
@@ -1213,31 +1287,38 @@ void _decode_opc(DisasContext * ctx) | @@ -1213,31 +1287,38 @@ void _decode_opc(DisasContext * ctx) | ||
1213 | case 0x0083: /* pref @Rn */ | 1287 | case 0x0083: /* pref @Rn */ |
1214 | return; | 1288 | return; |
1215 | case 0x4024: /* rotcl Rn */ | 1289 | case 0x4024: /* rotcl Rn */ |
1216 | - gen_op_rotcl_Rn(REG(B11_8)); | 1290 | + tcg_gen_mov_i32(cpu_T[0], cpu_sr); |
1291 | + gen_copy_bit_i32(cpu_sr, 0, cpu_gregs[REG(B11_8)], 31); | ||
1292 | + tcg_gen_shli_i32(cpu_gregs[REG(B11_8)], cpu_gregs[REG(B11_8)], 1); | ||
1293 | + gen_copy_bit_i32(cpu_gregs[REG(B11_8)], 0, cpu_T[0], 0); | ||
1217 | return; | 1294 | return; |
1218 | case 0x4025: /* rotcr Rn */ | 1295 | case 0x4025: /* rotcr Rn */ |
1219 | - gen_op_rotcr_Rn(REG(B11_8)); | 1296 | + tcg_gen_mov_i32(cpu_T[0], cpu_sr); |
1297 | + gen_copy_bit_i32(cpu_sr, 0, cpu_gregs[REG(B11_8)], 0); | ||
1298 | + tcg_gen_shri_i32(cpu_gregs[REG(B11_8)], cpu_gregs[REG(B11_8)], 1); | ||
1299 | + gen_copy_bit_i32(cpu_gregs[REG(B11_8)], 31, cpu_T[0], 0); | ||
1220 | return; | 1300 | return; |
1221 | case 0x4004: /* rotl Rn */ | 1301 | case 0x4004: /* rotl Rn */ |
1222 | - gen_op_rotl_Rn(REG(B11_8)); | 1302 | + gen_copy_bit_i32(cpu_sr, 0, cpu_gregs[REG(B11_8)], 31); |
1303 | + tcg_gen_shli_i32(cpu_gregs[REG(B11_8)], cpu_gregs[REG(B11_8)], 1); | ||
1304 | + gen_copy_bit_i32(cpu_gregs[REG(B11_8)], 0, cpu_sr, 0); | ||
1223 | return; | 1305 | return; |
1224 | case 0x4005: /* rotr Rn */ | 1306 | case 0x4005: /* rotr Rn */ |
1225 | - gen_op_rotr_Rn(REG(B11_8)); | 1307 | + gen_copy_bit_i32(cpu_sr, 0, cpu_gregs[REG(B11_8)], 0); |
1308 | + tcg_gen_shri_i32(cpu_gregs[REG(B11_8)], cpu_gregs[REG(B11_8)], 1); | ||
1309 | + gen_copy_bit_i32(cpu_gregs[REG(B11_8)], 31, cpu_sr, 0); | ||
1226 | return; | 1310 | return; |
1227 | case 0x4000: /* shll Rn */ | 1311 | case 0x4000: /* shll Rn */ |
1228 | case 0x4020: /* shal Rn */ | 1312 | case 0x4020: /* shal Rn */ |
1229 | - tcg_gen_andi_i32(cpu_T[0], cpu_gregs[REG(B11_8)], 0x80000000); | ||
1230 | - gen_cmp_imm(TCG_COND_NE, cpu_T[0], 0); | 1313 | + gen_copy_bit_i32(cpu_sr, 0, cpu_gregs[REG(B11_8)], 31); |
1231 | tcg_gen_shli_i32(cpu_gregs[REG(B11_8)], cpu_gregs[REG(B11_8)], 1); | 1314 | tcg_gen_shli_i32(cpu_gregs[REG(B11_8)], cpu_gregs[REG(B11_8)], 1); |
1232 | return; | 1315 | return; |
1233 | case 0x4021: /* shar Rn */ | 1316 | case 0x4021: /* shar Rn */ |
1234 | - tcg_gen_andi_i32(cpu_T[0], cpu_gregs[REG(B11_8)], 1); | ||
1235 | - gen_cmp_imm(TCG_COND_NE, cpu_T[0], 0); | 1317 | + gen_copy_bit_i32(cpu_sr, 0, cpu_gregs[REG(B11_8)], 0); |
1236 | tcg_gen_sari_i32(cpu_gregs[REG(B11_8)], cpu_gregs[REG(B11_8)], 1); | 1318 | tcg_gen_sari_i32(cpu_gregs[REG(B11_8)], cpu_gregs[REG(B11_8)], 1); |
1237 | return; | 1319 | return; |
1238 | case 0x4001: /* shlr Rn */ | 1320 | case 0x4001: /* shlr Rn */ |
1239 | - tcg_gen_andi_i32(cpu_T[0], cpu_gregs[REG(B11_8)], 1); | ||
1240 | - gen_cmp_imm(TCG_COND_NE, cpu_T[0], 0); | 1321 | + gen_copy_bit_i32(cpu_sr, 0, cpu_gregs[REG(B11_8)], 0); |
1241 | tcg_gen_shri_i32(cpu_gregs[REG(B11_8)], cpu_gregs[REG(B11_8)], 1); | 1322 | tcg_gen_shri_i32(cpu_gregs[REG(B11_8)], cpu_gregs[REG(B11_8)], 1); |
1242 | return; | 1323 | return; |
1243 | case 0x4008: /* shll2 Rn */ | 1324 | case 0x4008: /* shll2 Rn */ |